target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0
According to the Vector Reduction Operations section in the RISC-V "V" Vector Extension spec, "If vl=0, no operation is performed and the destination register is not updated." The vd should be updated when vl is larger than 0. Fixes: fe5c9ab1fc ("target/riscv: vector single-width integer reduction instructions") Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR") Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250124101452.2519171-1-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -4659,7 +4659,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
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} \
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} \
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s1 = OP(s1, (TD)s2); \
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s1 = OP(s1, (TD)s2); \
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} \
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} \
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if (vl > 0) { \
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*((TD *)vd + HD(0)) = s1; \
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*((TD *)vd + HD(0)) = s1; \
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} \
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env->vstart = 0; \
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env->vstart = 0; \
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/* set tail elements to 1s */ \
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/* set tail elements to 1s */ \
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vext_set_elems_1s(vd, vta, esz, vlenb); \
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vext_set_elems_1s(vd, vta, esz, vlenb); \
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@ -4745,7 +4747,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
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} \
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} \
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s1 = OP(s1, (TD)s2, &env->fp_status); \
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s1 = OP(s1, (TD)s2, &env->fp_status); \
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} \
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} \
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if (vl > 0) { \
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*((TD *)vd + HD(0)) = s1; \
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*((TD *)vd + HD(0)) = s1; \
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} \
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env->vstart = 0; \
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env->vstart = 0; \
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/* set tail elements to 1s */ \
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/* set tail elements to 1s */ \
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vext_set_elems_1s(vd, vta, esz, vlenb); \
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vext_set_elems_1s(vd, vta, esz, vlenb); \
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