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Misc HW patches

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- Expose v7M System Control Space as little endian (Philippe)
 - Deprecate MipsSim machine (Thomas)
 - Improve some devices categories / descriptions (Philippe)
 - Correct memory_rw_debug() prototype (Richard)
 - Do not expose i.MX 8M SoC as user-creatable (Bernhard)
 - Do not expose some PLL & eFuse devices as user-creatable (Philippe)
 - Do not reset Goldfish RTC time on machine reset (Heinrich)
 - Fix incorrect BCM2835 AUX interrupt ID when RX disabled (Chung-Yi)
 - Fix DesignWare PCI host bridge ATU_UPPER_TARGET register access (Philippe)
 - Memory leak fixes (Bernhard & Zheng Huang)
 - Prevent out-of-bound access in avr_print_insn (Richard)
 - Fixes around MIPS page mask (Richard)
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Merge tag 'hw-misc-20250331' of https://github.com/philmd/qemu into staging

Misc HW patches

- Expose v7M System Control Space as little endian (Philippe)
- Deprecate MipsSim machine (Thomas)
- Improve some devices categories / descriptions (Philippe)
- Correct memory_rw_debug() prototype (Richard)
- Do not expose i.MX 8M SoC as user-creatable (Bernhard)
- Do not expose some PLL & eFuse devices as user-creatable (Philippe)
- Do not reset Goldfish RTC time on machine reset (Heinrich)
- Fix incorrect BCM2835 AUX interrupt ID when RX disabled (Chung-Yi)
- Fix DesignWare PCI host bridge ATU_UPPER_TARGET register access (Philippe)
- Memory leak fixes (Bernhard & Zheng Huang)
- Prevent out-of-bound access in avr_print_insn (Richard)
- Fixes around MIPS page mask (Richard)

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# gpg: Signature made Mon 31 Mar 2025 15:47:34 EDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20250331' of https://github.com/philmd/qemu: (23 commits)
  target/mips: Simplify and fix update_pagemask
  target/mips: Require even maskbits in update_pagemask
  target/mips: Revert TARGET_PAGE_BITS_VARY
  target/sparc: Log unimplemented ASI load/store accesses
  target/avr: Fix buffer read in avr_print_insn
  target/hppa: Remove duplicated CPU_RESOLVING_TYPE definition
  hw/pci-host/designware: Fix ATU_UPPER_TARGET register access
  hw/ufs: free irq on exit
  hw/char/bcm2835_aux: Fix incorrect interrupt ID when RX disabled
  hw/sd/sdhci: free irq on exit
  hw/scsi/lsi53c895a: fix memory leak in lsi_scsi_realize()
  hw/nvram/xlnx-efuse: Do not expose as user-creatable
  hw/misc/pll: Do not expose as user-creatable
  hw/rtc/goldfish: keep time offset when resetting
  hw/mips: Mark the "mipssim" machine as deprecated
  hw/dma/i82374: Categorize and add description
  hw/display/dm163: Add description
  hw/block/m25p80: Categorize and add description
  hw/core/cpu: Use size_t for memory_rw_debug len argument
  hw/arm/fsl-imx8mp: Remove unused define
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-04-01 09:25:14 -04:00
commit fe9d41a734
30 changed files with 99 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
docs/about/deprecated.rst
View File

@ -292,6 +292,19 @@ Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` ma
Both ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` were added for little endian
CPUs. Big endian support is not tested.
Mips ``mipssim`` machine (since 10.0)
'''''''''''''''''''''''''''''''''''''
Linux dropped support for this virtual machine type in kernel v3.7, and
there does not seem to be anybody around who is still using this board
in QEMU: Most former MIPS-related people are working on other architectures
in their everyday job nowadays, and we are also not aware of anybody still
using old binaries with this board (i.e. there is also no binary available
online to check that this board did not completely bitrot yet). It is
recommended to use another MIPS machine for future MIPS code development
instead.
Backend options
---------------

14
hw/arm/armv7m.c
View File

@ -140,7 +140,7 @@ static MemTxResult v7m_sysreg_ns_write(void *opaque, hwaddr addr,
/* S accesses to the alias act like NS accesses to the real region */
attrs.secure = 0;
return memory_region_dispatch_write(mr, addr, value,
size_memop(size) | MO_TE, attrs);
size_memop(size) | MO_LE, attrs);
} else {
/* NS attrs are RAZ/WI for privileged, and BusFault for user */
if (attrs.user) {
@ -160,7 +160,7 @@ static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr,
/* S accesses to the alias act like NS accesses to the real region */
attrs.secure = 0;
return memory_region_dispatch_read(mr, addr, data,
size_memop(size) | MO_TE, attrs);
size_memop(size) | MO_LE, attrs);
} else {
/* NS attrs are RAZ/WI for privileged, and BusFault for user */
if (attrs.user) {
@ -174,7 +174,7 @@ static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr,
static const MemoryRegionOps v7m_sysreg_ns_ops = {
.read_with_attrs = v7m_sysreg_ns_read,
.write_with_attrs = v7m_sysreg_ns_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static MemTxResult v7m_systick_write(void *opaque, hwaddr addr,
@ -187,7 +187,7 @@ static MemTxResult v7m_systick_write(void *opaque, hwaddr addr,
/* Direct the access to the correct systick */
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
return memory_region_dispatch_write(mr, addr, value,
size_memop(size) | MO_TE, attrs);
size_memop(size) | MO_LE, attrs);
}
static MemTxResult v7m_systick_read(void *opaque, hwaddr addr,
@ -199,14 +199,14 @@ static MemTxResult v7m_systick_read(void *opaque, hwaddr addr,
/* Direct the access to the correct systick */
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
attrs);
return memory_region_dispatch_read(mr, addr, data,
size_memop(size) | MO_LE, attrs);
}
static const MemoryRegionOps v7m_systick_ops = {
.read_with_attrs = v7m_systick_read,
.write_with_attrs = v7m_systick_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
};
/*

2
hw/arm/fsl-imx8mp.c
View File

@ -702,7 +702,7 @@ static void fsl_imx8mp_class_init(ObjectClass *oc, void *data)
static const TypeInfo fsl_imx8mp_types[] = {
{
.name = TYPE_FSL_IMX8MP,
.parent = TYPE_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(FslImx8mpState),
.instance_init = fsl_imx8mp_init,
.class_init = fsl_imx8mp_class_init,

2
hw/arm/imx8mp-evk.c
View File

@ -37,7 +37,7 @@ static void imx8mp_evk_init(MachineState *machine)
s = FSL_IMX8MP(object_new(TYPE_FSL_IMX8MP));
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
object_property_set_uint(OBJECT(s), "fec1-phy-num", 1, &error_fatal);
qdev_realize(DEVICE(s), NULL, &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
memory_region_add_subregion(get_system_memory(), FSL_IMX8MP_RAM_START,
machine->ram);

2
hw/block/m25p80.c
View File

@ -1870,7 +1870,9 @@ static void m25p80_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_m25p80;
device_class_set_props(dc, m25p80_properties);
device_class_set_legacy_reset(dc, m25p80_reset);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
mc->pi = data;
dc->desc = "Serial Flash";
}
static const TypeInfo m25p80_info = {

2
hw/char/bcm2835_aux.c
View File

@ -98,7 +98,7 @@ static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
* interrupts are active, besides that this cannot occur. At
* present, we choose to prioritise the rx interrupt, since
* the tx fifo is always empty. */
if (s->read_count != 0) {
if ((s->iir & RX_INT) && s->read_count != 0) {
res |= 0x4;
} else {
res |= 0x2;

2
hw/display/dm163.c
View File

@ -330,7 +330,7 @@ static void dm163_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->desc = "DM163";
dc->desc = "DM163 8x3-channel constant current LED driver";
dc->vmsd = &vmstate_dm163;
dc->realize = dm163_realize;
rc->phases.hold = dm163_reset_hold;

2
hw/dma/i82374.c
View File

@ -150,6 +150,8 @@ static void i82374_class_init(ObjectClass *klass, void *data)
dc->realize = i82374_realize;
dc->vmsd = &vmstate_i82374;
device_class_set_props(dc, i82374_properties);
dc->desc = "Intel 82374 DMA controller";
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
static const TypeInfo i82374_info = {

1
hw/mips/fuloong2e.c
View File

@ -334,7 +334,6 @@ static void mips_fuloong2e_machine_init(MachineClass *mc)
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E");
mc->default_ram_size = 256 * MiB;
mc->default_ram_id = "fuloong2e.ram";
mc->minimum_page_bits = 14;
machine_add_audiodev_property(mc);
}

1
hw/mips/loongson3_virt.c
View File

@ -677,7 +677,6 @@ static void loongson3v_machine_class_init(ObjectClass *oc, void *data)
mc->max_cpus = LOONGSON_MAX_VCPUS;
mc->default_ram_id = "loongson3.highram";
mc->default_ram_size = 1600 * MiB;
mc->minimum_page_bits = 14;
mc->default_nic = "virtio-net-pci";
}

8
hw/misc/bcm2835_cprman.c
View File

@ -137,6 +137,8 @@ static void pll_class_init(ObjectClass *klass, void *data)
device_class_set_legacy_reset(dc, pll_reset);
dc->vmsd = &pll_vmstate;
/* Reason: Part of BCM2835CprmanState component */
dc->user_creatable = false;
}
static const TypeInfo cprman_pll_info = {
@ -241,6 +243,8 @@ static void pll_channel_class_init(ObjectClass *klass, void *data)
device_class_set_legacy_reset(dc, pll_channel_reset);
dc->vmsd = &pll_channel_vmstate;
/* Reason: Part of BCM2835CprmanState component */
dc->user_creatable = false;
}
static const TypeInfo cprman_pll_channel_info = {
@ -362,6 +366,8 @@ static void clock_mux_class_init(ObjectClass *klass, void *data)
device_class_set_legacy_reset(dc, clock_mux_reset);
dc->vmsd = &clock_mux_vmstate;
/* Reason: Part of BCM2835CprmanState component */
dc->user_creatable = false;
}
static const TypeInfo cprman_clock_mux_info = {
@ -416,6 +422,8 @@ static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &dsi0hsck_mux_vmstate;
/* Reason: Part of BCM2835CprmanState component */
dc->user_creatable = false;
}
static const TypeInfo cprman_dsi0hsck_mux_info = {

6
hw/misc/npcm_clk.c
View File

@ -1108,6 +1108,8 @@ static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
dc->desc = "NPCM7xx Clock PLL Module";
dc->vmsd = &vmstate_npcm7xx_clk_pll;
/* Reason: Part of NPCMCLKState component */
dc->user_creatable = false;
}
static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
@ -1116,6 +1118,8 @@ static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
dc->desc = "NPCM7xx Clock SEL Module";
dc->vmsd = &vmstate_npcm7xx_clk_sel;
/* Reason: Part of NPCMCLKState component */
dc->user_creatable = false;
}
static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
@ -1124,6 +1128,8 @@ static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
dc->desc = "NPCM7xx Clock Divider Module";
dc->vmsd = &vmstate_npcm7xx_clk_divider;
/* Reason: Part of NPCMCLKState component */
dc->user_creatable = false;
}
static void npcm_clk_class_init(ObjectClass *klass, void *data)

4
hw/misc/stm32l4x5_rcc.c
View File

@ -150,6 +150,8 @@ static void clock_mux_class_init(ObjectClass *klass, void *data)
rc->phases.hold = clock_mux_reset_hold;
rc->phases.exit = clock_mux_reset_exit;
dc->vmsd = &clock_mux_vmstate;
/* Reason: Part of Stm32l4x5RccState component */
dc->user_creatable = false;
}
static void clock_mux_set_enable(RccClockMuxState *mux, bool enabled)
@ -302,6 +304,8 @@ static void pll_class_init(ObjectClass *klass, void *data)
rc->phases.hold = pll_reset_hold;
rc->phases.exit = pll_reset_exit;
dc->vmsd = &pll_vmstate;
/* Reason: Part of Stm32l4x5RccState component */
dc->user_creatable = false;
}
static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier)

2
hw/nvram/xlnx-efuse.c
View File

@ -280,6 +280,8 @@ static void efuse_class_init(ObjectClass *klass, void *data)
dc->realize = efuse_realize;
device_class_set_props(dc, efuse_properties);
/* Reason: Part of Xilinx SoC */
dc->user_creatable = false;
}
static const TypeInfo efuse_info = {

2
hw/pci-host/designware.c
View File

@ -371,7 +371,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
viewport->target &= 0x00000000FFFFFFFFULL;
viewport->target |= val;
viewport->target |= (uint64_t)val << 32;
break;
case DESIGNWARE_PCIE_ATU_LIMIT:

13
hw/rtc/goldfish_rtc.c
View File

@ -239,15 +239,8 @@ static const VMStateDescription goldfish_rtc_vmstate = {
static void goldfish_rtc_reset(DeviceState *dev)
{
GoldfishRTCState *s = GOLDFISH_RTC(dev);
struct tm tm;
timer_del(s->timer);
qemu_get_timedate(&tm, 0);
s->tick_offset = mktimegm(&tm);
s->tick_offset *= NANOSECONDS_PER_SECOND;
s->tick_offset -= qemu_clock_get_ns(rtc_clock);
s->tick_offset_vmstate = 0;
s->alarm_next = 0;
s->alarm_running = 0;
s->irq_pending = 0;
@ -258,6 +251,7 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
{
SysBusDevice *dev = SYS_BUS_DEVICE(d);
GoldfishRTCState *s = GOLDFISH_RTC(d);
struct tm tm;
memory_region_init_io(&s->iomem, OBJECT(s),
&goldfish_rtc_ops[s->big_endian], s,
@ -267,6 +261,11 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
sysbus_init_irq(dev, &s->irq);
s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s);
qemu_get_timedate(&tm, 0);
s->tick_offset = mktimegm(&tm);
s->tick_offset *= NANOSECONDS_PER_SECOND;
s->tick_offset -= qemu_clock_get_ns(rtc_clock);
}
static const Property goldfish_rtc_properties[] = {

2
hw/scsi/lsi53c895a.c
View File

@ -2372,7 +2372,7 @@ static void lsi_scsi_exit(PCIDevice *dev)
LSIState *s = LSI53C895A(dev);
address_space_destroy(&s->pci_io_as);
timer_del(s->scripts_timer);
timer_free(s->scripts_timer);
}
static void lsi_class_init(ObjectClass *klass, void *data)

2
hw/sd/sdhci-pci.c
View File

@ -18,6 +18,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/sd/sdhci.h"
#include "sdhci-internal.h"
@ -48,6 +49,7 @@ static void sdhci_pci_exit(PCIDevice *dev)
{
SDHCIState *s = PCI_SDHCI(dev);
qemu_free_irq(s->irq);
sdhci_common_unrealize(s);
sdhci_uninitfn(s);
}

3
hw/ufs/ufs.c
View File

@ -25,6 +25,7 @@
#include "qapi/error.h"
#include "migration/vmstate.h"
#include "scsi/constants.h"
#include "hw/irq.h"
#include "trace.h"
#include "ufs.h"
@ -1808,6 +1809,8 @@ static void ufs_exit(PCIDevice *pci_dev)
{
UfsHc *u = UFS(pci_dev);
qemu_free_irq(u->irq);
qemu_bh_delete(u->doorbell_bh);
qemu_bh_delete(u->complete_bh);

4
include/hw/arm/fsl-imx8mp.h
View File

@ -26,6 +26,7 @@
#include "hw/timer/imx_gpt.h"
#include "hw/usb/hcd-dwc3.h"
#include "hw/watchdog/wdt_imx2.h"
#include "hw/sysbus.h"
#include "qom/object.h"
#include "qemu/units.h"
@ -49,7 +50,7 @@ enum FslImx8mpConfiguration {
};
struct FslImx8mpState {
DeviceState parent_obj;
SysBusDevice parent_obj;
ARMCPU cpu[FSL_IMX8MP_NUM_CPUS];
GICv3State gic;
@ -237,7 +238,6 @@ enum FslImx8mpIrqs {
FSL_IMX8MP_ECSPI1_IRQ = 31,
FSL_IMX8MP_ECSPI2_IRQ = 32,
FSL_IMX8MP_ECSPI3_IRQ = 33,
FSL_IMX8MP_ECSPI4_IRQ = 34,
FSL_IMX8MP_I2C1_IRQ = 35,
FSL_IMX8MP_I2C2_IRQ = 36,

2
include/hw/core/cpu.h
View File

@ -154,7 +154,7 @@ struct CPUClass {
int (*mmu_index)(CPUState *cpu, bool ifetch);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
uint8_t *buf, size_t len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value);
int64_t (*get_arch_id)(CPUState *cpu);

19
target/avr/disas.c
View File

@ -68,28 +68,35 @@ static bool decode_insn(DisasContext *ctx, uint16_t insn);
int avr_print_insn(bfd_vma addr, disassemble_info *info)
{
DisasContext ctx;
DisasContext ctx = { info };
DisasContext *pctx = &ctx;
bfd_byte buffer[4];
uint16_t insn;
int status;
ctx.info = info;
status = info->read_memory_func(addr, buffer, 4, info);
status = info->read_memory_func(addr, buffer, 2, info);
if (status != 0) {
info->memory_error_func(status, addr, info);
return -1;
}
insn = bfd_getl16(buffer);
status = info->read_memory_func(addr + 2, buffer + 2, 2, info);
if (status == 0) {
ctx.next_word = bfd_getl16(buffer + 2);
ctx.next_word_used = false;
}
if (!decode_insn(&ctx, insn)) {
output(".db", "0x%02x, 0x%02x", buffer[0], buffer[1]);
}
return ctx.next_word_used ? 4 : 2;
if (!ctx.next_word_used) {
return 2;
} else if (status == 0) {
return 4;
}
info->memory_error_func(status, addr + 2, info);
return -1;
}

2
target/hppa/cpu.h
View File

@ -391,6 +391,4 @@ void hppa_cpu_alarm_timer(void *);
#endif
G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
#endif /* HPPA_CPU_H */

5
target/mips/cpu-param.h
View File

@ -18,12 +18,7 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#endif
#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 12
#else
#define TARGET_PAGE_BITS_VARY
#define TARGET_PAGE_BITS_MIN 12
#endif
#define TCG_GUEST_DEFAULT_MO (0)

32
target/mips/tcg/system/cp0_helper.c
View File

@ -864,36 +864,24 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1)
}
}
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
uint32_t compute_pagemask(uint32_t val)
{
uint32_t mask;
int maskbits;
/* Don't care MASKX as we don't support 1KB page */
mask = extract32((uint32_t)arg1, CP0PM_MASK, 16);
maskbits = cto32(mask);
uint32_t mask = extract32(val, CP0PM_MASK, 16);
int maskbits = cto32(mask);
/* Ensure no more set bit after first zero */
if ((mask >> maskbits) != 0) {
goto invalid;
}
/* We don't support VTLB entry smaller than target page */
if ((maskbits + TARGET_PAGE_BITS_MIN) < TARGET_PAGE_BITS) {
goto invalid;
}
env->CP0_PageMask = mask << CP0PM_MASK;
return;
invalid:
/* Ensure no more set bit after first zero, and maskbits even. */
if ((mask >> maskbits) == 0 && maskbits % 2 == 0) {
return mask << CP0PM_MASK;
} else {
/* When invalid, set to default target page size. */
mask = (~TARGET_PAGE_MASK >> TARGET_PAGE_BITS_MIN);
env->CP0_PageMask = mask << CP0PM_MASK;
return 0;
}
}
void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
{
update_pagemask(env, arg1, &env->CP0_PageMask);
env->CP0_PageMask = compute_pagemask(arg1);
}
void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)

4
target/mips/tcg/system/tlb_helper.c
View File

@ -875,8 +875,8 @@ refill:
break;
}
}
pw_pagemask = m >> TARGET_PAGE_BITS_MIN;
update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask);
pw_pagemask = m >> TARGET_PAGE_BITS;
pw_pagemask = compute_pagemask(pw_pagemask << CP0PM_MASK);
pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
{
target_ulong tmp_entryhi = env->CP0_EntryHi;

2
target/mips/tcg/tcg-internal.h
View File

@ -47,7 +47,7 @@ bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
void mmu_init(CPUMIPSState *env, const mips_def_t *def);
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
uint32_t compute_pagemask(uint32_t val);
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
uint32_t cpu_mips_get_random(CPUMIPSState *env);

2
target/sparc/cpu.h
View File

@ -604,7 +604,7 @@ void dump_mmu(CPUSPARCState *env);
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
uint8_t *buf, size_t len, bool is_write);
#endif
/* translate.c */

6
target/sparc/ldst_helper.c
View File

@ -600,6 +600,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
case 0x0C: /* Leon3 Date Cache config */
if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
ret = leon3_cache_control_ld(env, addr, size);
} else {
qemu_log_mask(LOG_UNIMP, "0x" TARGET_FMT_lx ": unimplemented"
" address, size: %d\n", addr, size);
}
break;
case 0x01c00a00: /* MXCC control register */
@ -816,6 +819,9 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
case 0x0C: /* Leon3 Date Cache config */
if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
leon3_cache_control_st(env, addr, val, size);
} else {
qemu_log_mask(LOG_UNIMP, "0x" TARGET_FMT_lx ": unimplemented"
" address, size: %d\n", addr, size);
}
break;

2
target/sparc/mmu_helper.c
View File

@ -389,7 +389,7 @@ void dump_mmu(CPUSPARCState *env)
* that the sparc ABI is followed.
*/
int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address,
uint8_t *buf, int len, bool is_write)
uint8_t *buf, size_t len, bool is_write)
{
CPUSPARCState *env = cpu_env(cs);
target_ulong addr = address;