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target/mips: Revert TARGET_PAGE_BITS_VARY

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Revert ee3863b9d41 and a08d60bc6c2b.  The logic behind changing
the system page size because of what the Loongson kernel "prefers"
is flawed.

In the Loongson-2E manual, section 5.5, it is clear that the cpu
supports a 4k page size (along with many others).  Similarly for
the Loongson-3 series CPUs, the 4k page size is mentioned in the
section 7.7 (PageMask Register).  Therefore we must continue to
support a 4k page size.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250328175526.368121-2-richard.henderson@linaro.org>
[PMD: Mention Loongson-3 series CPUs]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Richard Henderson 2025-03-28 12:55:24 -05:00 committed by Philippe Mathieu-Daudé
parent 8001d22b0c
commit fca2817fdc
5 changed files with 2 additions and 14 deletions
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1
hw/mips/fuloong2e.c
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@ -334,7 +334,6 @@ static void mips_fuloong2e_machine_init(MachineClass *mc)
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E"); mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E");
mc->default_ram_size = 256 * MiB; mc->default_ram_size = 256 * MiB;
mc->default_ram_id = "fuloong2e.ram"; mc->default_ram_id = "fuloong2e.ram";
mc->minimum_page_bits = 14;
machine_add_audiodev_property(mc); machine_add_audiodev_property(mc);
} }

1
hw/mips/loongson3_virt.c
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@ -677,7 +677,6 @@ static void loongson3v_machine_class_init(ObjectClass *oc, void *data)
mc->max_cpus = LOONGSON_MAX_VCPUS; mc->max_cpus = LOONGSON_MAX_VCPUS;
mc->default_ram_id = "loongson3.highram"; mc->default_ram_id = "loongson3.highram";
mc->default_ram_size = 1600 * MiB; mc->default_ram_size = 1600 * MiB;
mc->minimum_page_bits = 14;
mc->default_nic = "virtio-net-pci"; mc->default_nic = "virtio-net-pci";
} }

5
target/mips/cpu-param.h
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@ -18,12 +18,7 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32 # define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif #endif
#endif #endif
#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 12 #define TARGET_PAGE_BITS 12
#else
#define TARGET_PAGE_BITS_VARY
#define TARGET_PAGE_BITS_MIN 12
#endif
#define TCG_GUEST_DEFAULT_MO (0) #define TCG_GUEST_DEFAULT_MO (0)

7
target/mips/tcg/system/cp0_helper.c
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@ -877,18 +877,13 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
if ((mask >> maskbits) != 0) { if ((mask >> maskbits) != 0) {
goto invalid; goto invalid;
} }
/* We don't support VTLB entry smaller than target page */
if ((maskbits + TARGET_PAGE_BITS_MIN) < TARGET_PAGE_BITS) {
goto invalid;
}
env->CP0_PageMask = mask << CP0PM_MASK; env->CP0_PageMask = mask << CP0PM_MASK;
return; return;
invalid: invalid:
/* When invalid, set to default target page size. */ /* When invalid, set to default target page size. */
mask = (~TARGET_PAGE_MASK >> TARGET_PAGE_BITS_MIN); env->CP0_PageMask = 0;
env->CP0_PageMask = mask << CP0PM_MASK;
} }
void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)

2
target/mips/tcg/system/tlb_helper.c
View File

@ -875,7 +875,7 @@ refill:
break; break;
} }
} }
pw_pagemask = m >> TARGET_PAGE_BITS_MIN; pw_pagemask = m >> TARGET_PAGE_BITS;
update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask); update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask);
pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF); pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
{ {