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rust: pl011: always use reset() method on registers

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For CR, the ugly-ish "0.into()" idiom is already hidden within the
reset method.  Do not repeat it.

For FR, standardize on reset() being equivalent to "*self = Self::default()"
and let reset_fifo toggle only the bits that are related to FIFOs.  This
commit also reproduces C commit 02b1f7f6192 ("hw/char/pl011: Split RX/TX
path of pl011_reset_fifo()", 2024-09-13).

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2024-12-04 16:44:42 +01:00
parent ac096b0bef
commit f65314bdd0
2 changed files with 21 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
rust/hw/char/pl011/src/device.rs
View File

@ -262,7 +262,7 @@ impl PL011State {
self.update(); self.update();
} }
Ok(RSR) => { Ok(RSR) => {
self.receive_status_error_clear = 0.into(); self.receive_status_error_clear.reset();
} }
Ok(FR) => { Ok(FR) => {
// flag writes are ignored // flag writes are ignored
@ -283,7 +283,8 @@ impl PL011State {
if bool::from(self.line_control.fifos_enabled()) if bool::from(self.line_control.fifos_enabled())
^ bool::from(new_val.fifos_enabled()) ^ bool::from(new_val.fifos_enabled())
{ {
self.reset_fifo(); self.reset_rx_fifo();
self.reset_tx_fifo();
} }
if self.line_control.send_break() ^ new_val.send_break() { if self.line_control.send_break() ^ new_val.send_break() {
let mut break_enable: c_int = new_val.send_break().into(); let mut break_enable: c_int = new_val.send_break().into();
@ -442,16 +443,24 @@ impl PL011State {
self.read_trigger = 1; self.read_trigger = 1;
self.ifl = 0x12; self.ifl = 0x12;
self.control.reset(); self.control.reset();
self.flags = 0.into(); self.flags.reset();
self.reset_fifo(); self.reset_rx_fifo();
self.reset_tx_fifo();
} }
pub fn reset_fifo(&mut self) { pub fn reset_rx_fifo(&mut self) {
self.read_count = 0; self.read_count = 0;
self.read_pos = 0; self.read_pos = 0;
/* Reset FIFO flags */ // Reset FIFO flags
self.flags.reset(); self.flags.set_receive_fifo_full(false);
self.flags.set_receive_fifo_empty(true);
}
pub fn reset_tx_fifo(&mut self) {
// Reset FIFO flags
self.flags.set_transmit_fifo_full(false);
self.flags.set_transmit_fifo_empty(true);
} }
pub fn can_receive(&self) -> bool { pub fn can_receive(&self) -> bool {

13
rust/hw/char/pl011/src/lib.rs
View File

@ -230,7 +230,7 @@ pub mod registers {
impl ReceiveStatusErrorClear { impl ReceiveStatusErrorClear {
pub fn reset(&mut self) { pub fn reset(&mut self) {
// All the bits are cleared to 0 on reset. // All the bits are cleared to 0 on reset.
*self = 0.into(); *self = Self::default();
} }
} }
@ -297,19 +297,16 @@ pub mod registers {
impl Flags { impl Flags {
pub fn reset(&mut self) { pub fn reset(&mut self) {
// After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1 *self = Self::default();
self.set_receive_fifo_full(false);
self.set_transmit_fifo_full(false);
self.set_busy(false);
self.set_receive_fifo_empty(true);
self.set_transmit_fifo_empty(true);
} }
} }
impl Default for Flags { impl Default for Flags {
fn default() -> Self { fn default() -> Self {
let mut ret: Self = 0.into(); let mut ret: Self = 0.into();
ret.reset(); // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1
ret.set_receive_fifo_empty(true);
ret.set_transmit_fifo_empty(true);
ret ret
} }
} }