target/arm: Convert handle_fpfpcvt to decodetree
This includes SCVTF, UCVTF, FCVT{N,P,M,Z,A}{S,U}.
Remove disas_fp_fixed_conv as those were the last insns
decoded by that function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
7b0f8dc1ec
commit
f568134a57
@ -1323,6 +1323,46 @@ FMAXV_s 0110 1110 00 11000 01111 10 ..... ..... @rr_q1e2
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FMINV_h 0.00 1110 10 11000 01111 10 ..... ..... @qrr_h
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FMINV_s 0110 1110 10 11000 01111 10 ..... ..... @rr_q1e2
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# Conversion between floating-point and fixed-point (general register)
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&fcvt rd rn esz sf shift
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%fcvt_shift32 10:5 !function=rsub_32
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%fcvt_shift64 10:6 !function=rsub_64
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@fcvt32 0 ....... .. ...... 1..... rn:5 rd:5 \
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&fcvt sf=0 esz=%esz_hsd shift=%fcvt_shift32
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@fcvt64 1 ....... .. ...... ...... rn:5 rd:5 \
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&fcvt sf=1 esz=%esz_hsd shift=%fcvt_shift64
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SCVTF_g . 0011110 .. 000010 ...... ..... ..... @fcvt32
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SCVTF_g . 0011110 .. 000010 ...... ..... ..... @fcvt64
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UCVTF_g . 0011110 .. 000011 ...... ..... ..... @fcvt32
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UCVTF_g . 0011110 .. 000011 ...... ..... ..... @fcvt64
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FCVTZS_g . 0011110 .. 011000 ...... ..... ..... @fcvt32
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FCVTZS_g . 0011110 .. 011000 ...... ..... ..... @fcvt64
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FCVTZU_g . 0011110 .. 011001 ...... ..... ..... @fcvt32
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FCVTZU_g . 0011110 .. 011001 ...... ..... ..... @fcvt64
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# Conversion between floating-point and integer (general register)
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@icvt sf:1 ....... .. ...... ...... rn:5 rd:5 \
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&fcvt esz=%esz_hsd shift=0
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SCVTF_g . 0011110 .. 100010 000000 ..... ..... @icvt
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UCVTF_g . 0011110 .. 100011 000000 ..... ..... @icvt
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FCVTNS_g . 0011110 .. 100000 000000 ..... ..... @icvt
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FCVTNU_g . 0011110 .. 100001 000000 ..... ..... @icvt
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FCVTPS_g . 0011110 .. 101000 000000 ..... ..... @icvt
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FCVTPU_g . 0011110 .. 101001 000000 ..... ..... @icvt
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FCVTMS_g . 0011110 .. 110000 000000 ..... ..... @icvt
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FCVTMU_g . 0011110 .. 110001 000000 ..... ..... @icvt
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FCVTZS_g . 0011110 .. 111000 000000 ..... ..... @icvt
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FCVTZU_g . 0011110 .. 111001 000000 ..... ..... @icvt
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FCVTAS_g . 0011110 .. 100100 000000 ..... ..... @icvt
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FCVTAU_g . 0011110 .. 100101 000000 ..... ..... @icvt
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# Floating-point data processing (1 source)
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FMOV_s 00011110 .. 1 000000 10000 ..... ..... @rr_hsd
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@ -8524,227 +8524,196 @@ static bool trans_FCVT_s_dh(DisasContext *s, arg_rr *a)
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return true;
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}
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/* Handle floating point <=> fixed point conversions. Note that we can
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* also deal with fp <=> integer conversions as a special case (scale == 64)
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* OPTME: consider handling that special case specially or at least skipping
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* the call to scalbn in the helpers for zero shifts.
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*/
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static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
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bool itof, int rmode, int scale, int sf, int type)
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static bool do_cvtf_scalar(DisasContext *s, MemOp esz, int rd, int shift,
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TCGv_i64 tcg_int, bool is_signed)
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{
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bool is_signed = !(opcode & 1);
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TCGv_ptr tcg_fpstatus;
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TCGv_i32 tcg_shift, tcg_single;
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TCGv_i64 tcg_double;
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tcg_fpstatus = fpstatus_ptr(type == 3 ? FPST_FPCR_F16 : FPST_FPCR);
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tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
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tcg_shift = tcg_constant_i32(shift);
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tcg_shift = tcg_constant_i32(64 - scale);
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if (itof) {
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TCGv_i64 tcg_int = cpu_reg(s, rn);
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if (!sf) {
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TCGv_i64 tcg_extend = tcg_temp_new_i64();
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if (is_signed) {
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tcg_gen_ext32s_i64(tcg_extend, tcg_int);
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} else {
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tcg_gen_ext32u_i64(tcg_extend, tcg_int);
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}
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tcg_int = tcg_extend;
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switch (esz) {
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case MO_64:
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tcg_double = tcg_temp_new_i64();
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if (is_signed) {
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gen_helper_vfp_sqtod(tcg_double, tcg_int, tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_uqtod(tcg_double, tcg_int, tcg_shift, tcg_fpstatus);
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}
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write_fp_dreg(s, rd, tcg_double);
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break;
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switch (type) {
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case 1: /* float64 */
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tcg_double = tcg_temp_new_i64();
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if (is_signed) {
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gen_helper_vfp_sqtod(tcg_double, tcg_int,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_uqtod(tcg_double, tcg_int,
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tcg_shift, tcg_fpstatus);
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}
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write_fp_dreg(s, rd, tcg_double);
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break;
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case 0: /* float32 */
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tcg_single = tcg_temp_new_i32();
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if (is_signed) {
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gen_helper_vfp_sqtos(tcg_single, tcg_int,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_uqtos(tcg_single, tcg_int,
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tcg_shift, tcg_fpstatus);
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}
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write_fp_sreg(s, rd, tcg_single);
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break;
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case 3: /* float16 */
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tcg_single = tcg_temp_new_i32();
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if (is_signed) {
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gen_helper_vfp_sqtoh(tcg_single, tcg_int,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_uqtoh(tcg_single, tcg_int,
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tcg_shift, tcg_fpstatus);
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}
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write_fp_sreg(s, rd, tcg_single);
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break;
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default:
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g_assert_not_reached();
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case MO_32:
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tcg_single = tcg_temp_new_i32();
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if (is_signed) {
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gen_helper_vfp_sqtos(tcg_single, tcg_int, tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_uqtos(tcg_single, tcg_int, tcg_shift, tcg_fpstatus);
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}
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} else {
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TCGv_i64 tcg_int = cpu_reg(s, rd);
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TCGv_i32 tcg_rmode;
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write_fp_sreg(s, rd, tcg_single);
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break;
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if (extract32(opcode, 2, 1)) {
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/* There are too many rounding modes to all fit into rmode,
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* so FCVTA[US] is a special case.
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*/
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rmode = FPROUNDING_TIEAWAY;
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case MO_16:
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tcg_single = tcg_temp_new_i32();
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if (is_signed) {
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gen_helper_vfp_sqtoh(tcg_single, tcg_int, tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_uqtoh(tcg_single, tcg_int, tcg_shift, tcg_fpstatus);
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}
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write_fp_sreg(s, rd, tcg_single);
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break;
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tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
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switch (type) {
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case 1: /* float64 */
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tcg_double = read_fp_dreg(s, rn);
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if (is_signed) {
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if (!sf) {
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gen_helper_vfp_tosld(tcg_int, tcg_double,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_tosqd(tcg_int, tcg_double,
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tcg_shift, tcg_fpstatus);
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}
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} else {
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if (!sf) {
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gen_helper_vfp_tould(tcg_int, tcg_double,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_touqd(tcg_int, tcg_double,
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tcg_shift, tcg_fpstatus);
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}
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}
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if (!sf) {
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tcg_gen_ext32u_i64(tcg_int, tcg_int);
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}
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break;
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case 0: /* float32 */
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tcg_single = read_fp_sreg(s, rn);
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if (sf) {
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if (is_signed) {
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gen_helper_vfp_tosqs(tcg_int, tcg_single,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_touqs(tcg_int, tcg_single,
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tcg_shift, tcg_fpstatus);
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}
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} else {
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TCGv_i32 tcg_dest = tcg_temp_new_i32();
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if (is_signed) {
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gen_helper_vfp_tosls(tcg_dest, tcg_single,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_touls(tcg_dest, tcg_single,
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tcg_shift, tcg_fpstatus);
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}
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tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
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}
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break;
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case 3: /* float16 */
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tcg_single = read_fp_sreg(s, rn);
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if (sf) {
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if (is_signed) {
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gen_helper_vfp_tosqh(tcg_int, tcg_single,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_touqh(tcg_int, tcg_single,
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tcg_shift, tcg_fpstatus);
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}
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} else {
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TCGv_i32 tcg_dest = tcg_temp_new_i32();
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if (is_signed) {
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gen_helper_vfp_toslh(tcg_dest, tcg_single,
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tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_toulh(tcg_dest, tcg_single,
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tcg_shift, tcg_fpstatus);
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}
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tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
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}
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break;
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default:
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g_assert_not_reached();
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}
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gen_restore_rmode(tcg_rmode, tcg_fpstatus);
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default:
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g_assert_not_reached();
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}
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return true;
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}
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/* Floating point <-> fixed point conversions
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* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
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* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
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* | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
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* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
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*/
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static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
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static bool do_cvtf_g(DisasContext *s, arg_fcvt *a, bool is_signed)
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{
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int scale = extract32(insn, 10, 6);
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int opcode = extract32(insn, 16, 3);
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int rmode = extract32(insn, 19, 2);
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int type = extract32(insn, 22, 2);
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bool sbit = extract32(insn, 29, 1);
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bool sf = extract32(insn, 31, 1);
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bool itof;
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TCGv_i64 tcg_int;
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int check = fp_access_check_scalar_hsd(s, a->esz);
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if (sbit || (!sf && scale < 32)) {
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unallocated_encoding(s);
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return;
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if (check <= 0) {
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return check == 0;
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}
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switch (type) {
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case 0: /* float32 */
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case 1: /* float64 */
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break;
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case 3: /* float16 */
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if (dc_isar_feature(aa64_fp16, s)) {
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break;
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if (a->sf) {
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tcg_int = cpu_reg(s, a->rn);
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} else {
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tcg_int = read_cpu_reg(s, a->rn, true);
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if (is_signed) {
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tcg_gen_ext32s_i64(tcg_int, tcg_int);
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} else {
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tcg_gen_ext32u_i64(tcg_int, tcg_int);
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}
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/* fallthru */
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default:
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unallocated_encoding(s);
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return;
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}
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switch ((rmode << 3) | opcode) {
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case 0x2: /* SCVTF */
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case 0x3: /* UCVTF */
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itof = true;
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break;
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case 0x18: /* FCVTZS */
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case 0x19: /* FCVTZU */
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itof = false;
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type);
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return do_cvtf_scalar(s, a->esz, a->rd, a->shift, tcg_int, is_signed);
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}
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TRANS(SCVTF_g, do_cvtf_g, a, true)
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TRANS(UCVTF_g, do_cvtf_g, a, false)
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static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
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TCGv_i64 tcg_out, int shift, int rn,
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ARMFPRounding rmode)
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{
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TCGv_ptr tcg_fpstatus;
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TCGv_i32 tcg_shift, tcg_rmode, tcg_single;
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tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
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tcg_shift = tcg_constant_i32(shift);
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tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
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switch (esz) {
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case MO_64:
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read_vec_element(s, tcg_out, rn, 0, MO_64);
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switch (out) {
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case MO_64 | MO_SIGN:
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gen_helper_vfp_tosqd(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
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break;
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case MO_64:
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gen_helper_vfp_touqd(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
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break;
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case MO_32 | MO_SIGN:
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gen_helper_vfp_tosld(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
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break;
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case MO_32:
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gen_helper_vfp_tould(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case MO_32:
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tcg_single = read_fp_sreg(s, rn);
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switch (out) {
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case MO_64 | MO_SIGN:
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gen_helper_vfp_tosqs(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
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break;
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case MO_64:
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gen_helper_vfp_touqs(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
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break;
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case MO_32 | MO_SIGN:
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gen_helper_vfp_tosls(tcg_single, tcg_single,
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tcg_shift, tcg_fpstatus);
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tcg_gen_extu_i32_i64(tcg_out, tcg_single);
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break;
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case MO_32:
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gen_helper_vfp_touls(tcg_single, tcg_single,
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tcg_shift, tcg_fpstatus);
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tcg_gen_extu_i32_i64(tcg_out, tcg_single);
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case MO_16:
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tcg_single = read_fp_hreg(s, rn);
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switch (out) {
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case MO_64 | MO_SIGN:
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gen_helper_vfp_tosqh(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
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break;
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case MO_64:
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gen_helper_vfp_touqh(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
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break;
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case MO_32 | MO_SIGN:
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gen_helper_vfp_toslh(tcg_single, tcg_single,
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tcg_shift, tcg_fpstatus);
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tcg_gen_extu_i32_i64(tcg_out, tcg_single);
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break;
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case MO_32:
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gen_helper_vfp_toulh(tcg_single, tcg_single,
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tcg_shift, tcg_fpstatus);
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tcg_gen_extu_i32_i64(tcg_out, tcg_single);
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break;
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default:
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g_assert_not_reached();
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}
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break;
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default:
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g_assert_not_reached();
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}
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gen_restore_rmode(tcg_rmode, tcg_fpstatus);
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}
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|
||||
static bool do_fcvt_g(DisasContext *s, arg_fcvt *a,
|
||||
ARMFPRounding rmode, bool is_signed)
|
||||
{
|
||||
TCGv_i64 tcg_int;
|
||||
int check = fp_access_check_scalar_hsd(s, a->esz);
|
||||
|
||||
if (check <= 0) {
|
||||
return check == 0;
|
||||
}
|
||||
|
||||
tcg_int = cpu_reg(s, a->rd);
|
||||
do_fcvt_scalar(s, (a->sf ? MO_64 : MO_32) | (is_signed ? MO_SIGN : 0),
|
||||
a->esz, tcg_int, a->shift, a->rn, rmode);
|
||||
|
||||
if (!a->sf) {
|
||||
tcg_gen_ext32u_i64(tcg_int, tcg_int);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
TRANS(FCVTNS_g, do_fcvt_g, a, FPROUNDING_TIEEVEN, true)
|
||||
TRANS(FCVTNU_g, do_fcvt_g, a, FPROUNDING_TIEEVEN, false)
|
||||
TRANS(FCVTPS_g, do_fcvt_g, a, FPROUNDING_POSINF, true)
|
||||
TRANS(FCVTPU_g, do_fcvt_g, a, FPROUNDING_POSINF, false)
|
||||
TRANS(FCVTMS_g, do_fcvt_g, a, FPROUNDING_NEGINF, true)
|
||||
TRANS(FCVTMU_g, do_fcvt_g, a, FPROUNDING_NEGINF, false)
|
||||
TRANS(FCVTZS_g, do_fcvt_g, a, FPROUNDING_ZERO, true)
|
||||
TRANS(FCVTZU_g, do_fcvt_g, a, FPROUNDING_ZERO, false)
|
||||
TRANS(FCVTAS_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, true)
|
||||
TRANS(FCVTAU_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, false)
|
||||
|
||||
static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
|
||||
{
|
||||
/* FMOV: gpr to or from float, double, or top half of quad fp reg,
|
||||
@ -8844,33 +8813,11 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
|
||||
switch (opcode) {
|
||||
case 2: /* SCVTF */
|
||||
case 3: /* UCVTF */
|
||||
itof = true;
|
||||
/* fallthru */
|
||||
case 4: /* FCVTAS */
|
||||
case 5: /* FCVTAU */
|
||||
if (rmode != 0) {
|
||||
goto do_unallocated;
|
||||
}
|
||||
/* fallthru */
|
||||
case 0: /* FCVT[NPMZ]S */
|
||||
case 1: /* FCVT[NPMZ]U */
|
||||
switch (type) {
|
||||
case 0: /* float32 */
|
||||
case 1: /* float64 */
|
||||
break;
|
||||
case 3: /* float16 */
|
||||
if (!dc_isar_feature(aa64_fp16, s)) {
|
||||
goto do_unallocated;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
goto do_unallocated;
|
||||
}
|
||||
if (!fp_access_check(s)) {
|
||||
return;
|
||||
}
|
||||
handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
|
||||
break;
|
||||
goto do_unallocated;
|
||||
|
||||
default:
|
||||
switch (sf << 7 | type << 5 | rmode << 3 | opcode) {
|
||||
@ -8924,7 +8871,7 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
|
||||
unallocated_encoding(s); /* in decodetree */
|
||||
} else if (extract32(insn, 21, 1) == 0) {
|
||||
/* Floating point to fixed point conversions */
|
||||
disas_fp_fixed_conv(s, insn);
|
||||
unallocated_encoding(s); /* in decodetree */
|
||||
} else {
|
||||
switch (extract32(insn, 10, 2)) {
|
||||
case 1: /* Floating point conditional compare */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user