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target/riscv/tcg: add sha

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'sha' is the augmented hypervisor extension, defined in RVA22 as a set of
the following extensions:

- RVH
- Ssstateen
- Shcounterenw (always present)
- Shvstvala (always present)
- Shtvala (always present)
- Shvstvecd (always present)
- Shvsatpa (always present)
- Shgatpa (always present)

We can claim support for 'sha' by checking if we have RVH and ssstateen.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241218114026.1652352-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2024-12-18 08:40:26 -03:00 committed by Alistair Francis
parent 2fedb6b183
commit f4df21e07f
3 changed files with 11 additions and 0 deletions
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2
target/riscv/cpu.c
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@ -184,6 +184,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),
ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
@ -1714,6 +1715,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = { const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true), MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
{ }, { },
}; };

1
target/riscv/cpu_cfg.h
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@ -141,6 +141,7 @@ struct RISCVCPUConfig {
bool ext_svade; bool ext_svade;
bool ext_zic64b; bool ext_zic64b;
bool ext_ssstateen; bool ext_ssstateen;
bool ext_sha;
/* /*
* Always 'true' booleans for named features * Always 'true' booleans for named features

8
target/riscv/tcg/tcg-cpu.c
View File

@ -212,6 +212,11 @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset)
cpu->cfg.cbop_blocksize = 64; cpu->cfg.cbop_blocksize = 64;
cpu->cfg.cboz_blocksize = 64; cpu->cfg.cboz_blocksize = 64;
break; break;
case CPU_CFG_OFFSET(ext_sha):
if (!cpu_misa_ext_is_user_set(RVH)) {
riscv_cpu_write_misa_bit(cpu, RVH, true);
}
/* fallthrough */
case CPU_CFG_OFFSET(ext_ssstateen): case CPU_CFG_OFFSET(ext_ssstateen):
cpu->cfg.ext_smstateen = true; cpu->cfg.ext_smstateen = true;
break; break;
@ -352,6 +357,9 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
cpu->cfg.cboz_blocksize == 64; cpu->cfg.cboz_blocksize == 64;
cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen;
cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) &&
cpu->cfg.ext_ssstateen;
} }
static void riscv_cpu_validate_g(RISCVCPU *cpu) static void riscv_cpu_validate_g(RISCVCPU *cpu)