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target/arm: Convert [US]CVTF (vector, integer) scalar to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-60-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:30:26 -06:00 committed by Peter Maydell
parent 6697b35e98
commit f469ca170d
2 changed files with 31 additions and 10 deletions
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6
target/arm/tcg/a64.decode
View File

@ -1657,6 +1657,12 @@ FCVTXN_s 0111 1110 011 00001 01101 0 ..... ..... @rr_s
@icvt_sd . ....... .. ...... ...... rn:5 rd:5 \
&fcvt sf=0 esz=%esz_sd shift=0
SCVTF_f 0101 1110 011 11001 11011 0 ..... ..... @icvt_h
SCVTF_f 0101 1110 0.1 00001 11011 0 ..... ..... @icvt_sd
UCVTF_f 0111 1110 011 11001 11011 0 ..... ..... @icvt_h
UCVTF_f 0111 1110 0.1 00001 11011 0 ..... ..... @icvt_sd
FCVTNS_f 0101 1110 011 11001 10101 0 ..... ..... @icvt_h
FCVTNS_f 0101 1110 0.1 00001 10101 0 ..... ..... @icvt_sd
FCVTNU_f 0111 1110 011 11001 10101 0 ..... ..... @icvt_h

35
target/arm/tcg/translate-a64.c
View File

@ -8599,6 +8599,29 @@ static bool do_cvtf_g(DisasContext *s, arg_fcvt *a, bool is_signed)
TRANS(SCVTF_g, do_cvtf_g, a, true)
TRANS(UCVTF_g, do_cvtf_g, a, false)
/*
* [US]CVTF (vector), scalar version.
* Which sounds weird, but really just means input from fp register
* instead of input from general register. Input and output element
* size are always equal.
*/
static bool do_cvtf_f(DisasContext *s, arg_fcvt *a, bool is_signed)
{
TCGv_i64 tcg_int;
int check = fp_access_check_scalar_hsd(s, a->esz);
if (check <= 0) {
return check == 0;
}
tcg_int = tcg_temp_new_i64();
read_vec_element(s, tcg_int, a->rn, 0, a->esz | (is_signed ? MO_SIGN : 0));
return do_cvtf_scalar(s, a->esz, a->rd, a->shift, tcg_int, is_signed);
}
TRANS(SCVTF_f, do_cvtf_f, a, true)
TRANS(UCVTF_f, do_cvtf_f, a, false)
static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
TCGv_i64 tcg_out, int shift, int rn,
ARMFPRounding rmode)
@ -9838,16 +9861,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x6d: /* FCMLE (zero) */
handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd);
return;
case 0x1d: /* SCVTF */
case 0x5d: /* UCVTF */
{
bool is_signed = (opcode == 0x1d);
if (!fp_access_check(s)) {
return;
}
handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size);
return;
}
case 0x3d: /* FRECPE */
case 0x3f: /* FRECPX */
case 0x7d: /* FRSQRTE */
@ -9867,6 +9880,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x1c: /* FCVTAS */
case 0x5c: /* FCVTAU */
case 0x56: /* FCVTXN, FCVTXN2 */
case 0x1d: /* SCVTF */
case 0x5d: /* UCVTF */
default:
unallocated_encoding(s);
return;