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tcg/riscv: Use 'z' constraint

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Replace target-specific 'Z' with generic 'z'.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-02-09 17:26:28 -08:00
parent 065c8f6416
commit f466db1e27
3 changed files with 17 additions and 22 deletions
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10
tcg/riscv/tcg-target-con-set.h
View File

@ -10,17 +10,17 @@
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I1(r)
C_O0_I2(rZ, r)
C_O0_I2(rZ, rZ)
C_O0_I2(rz, r)
C_O0_I2(rz, rz)
C_O1_I1(r, r)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rJ)
C_O1_I2(r, rZ, rN)
C_O1_I2(r, rZ, rZ)
C_O1_I2(r, rz, rN)
C_O1_I2(r, rz, rz)
C_N1_I2(r, r, rM)
C_O1_I4(r, r, rI, rM, rM)
C_O2_I4(r, r, rZ, rZ, rM, rM)
C_O2_I4(r, r, rz, rz, rM, rM)
C_O0_I2(v, r)
C_O1_I1(v, r)
C_O1_I1(v, v)

1
tcg/riscv/tcg-target-con-str.h
View File

@ -21,4 +21,3 @@ CONST('K', TCG_CT_CONST_S5)
CONST('L', TCG_CT_CONST_CMP_VI)
CONST('N', TCG_CT_CONST_N12)
CONST('M', TCG_CT_CONST_M12)
CONST('Z', TCG_CT_CONST_ZERO)

28
tcg/riscv/tcg-target.c.inc
View File

@ -112,13 +112,12 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
return TCG_REG_A0 + slot;
}
#define TCG_CT_CONST_ZERO 0x100
#define TCG_CT_CONST_S12 0x200
#define TCG_CT_CONST_N12 0x400
#define TCG_CT_CONST_M12 0x800
#define TCG_CT_CONST_J12 0x1000
#define TCG_CT_CONST_S5 0x2000
#define TCG_CT_CONST_CMP_VI 0x4000
#define TCG_CT_CONST_S12 0x100
#define TCG_CT_CONST_N12 0x200
#define TCG_CT_CONST_M12 0x400
#define TCG_CT_CONST_J12 0x800
#define TCG_CT_CONST_S5 0x1000
#define TCG_CT_CONST_CMP_VI 0x2000
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
@ -391,9 +390,6 @@ static bool tcg_target_const_match(int64_t val, int ct,
if (ct & TCG_CT_CONST) {
return 1;
}
if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return 1;
}
if (type >= TCG_TYPE_V64) {
/* Val is replicated by VECE; extract the highest element. */
val >>= (-8 << vece) & 63;
@ -2681,7 +2677,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
return C_O0_I2(rZ, r);
return C_O0_I2(rz, r);
case INDEX_op_add_i32:
case INDEX_op_and_i32:
@ -2707,7 +2703,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
return C_O1_I2(r, rZ, rN);
return C_O1_I2(r, rz, rN);
case INDEX_op_mul_i32:
case INDEX_op_mulsh_i32:
@ -2723,7 +2719,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_divu_i64:
case INDEX_op_rem_i64:
case INDEX_op_remu_i64:
return C_O1_I2(r, rZ, rZ);
return C_O1_I2(r, rz, rz);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
@ -2745,7 +2741,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
return C_O0_I2(rZ, rZ);
return C_O0_I2(rz, rz);
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
@ -2755,14 +2751,14 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
case INDEX_op_sub2_i64:
return C_O2_I4(r, r, rZ, rZ, rM, rM);
return C_O2_I4(r, r, rz, rz, rM, rM);
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
return C_O1_I1(r, r);
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
return C_O0_I2(rZ, r);
return C_O0_I2(rz, r);
case INDEX_op_st_vec:
return C_O0_I2(v, r);