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target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2

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Use the single ISA_MIPS32R2 definition to check if the Release 2
ISA is supported, whether the CPU support 32/64-bit.

For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R2 in few commits.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-8-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-12-16 12:06:51 +01:00
parent 08e2262fad
commit f395cef765
3 changed files with 3 additions and 5 deletions
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1
linux-user/mips/cpu_loop.c
View File

@ -385,7 +385,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
prog_req.fre &= interp_req.fre; prog_req.fre &= interp_req.fre;
bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
env->insn_flags & ISA_MIPS64R2 ||
env->insn_flags & ISA_MIPS32R6 || env->insn_flags & ISA_MIPS32R6 ||
env->insn_flags & ISA_MIPS64R6; env->insn_flags & ISA_MIPS64R6;

3
target/mips/mips-defs.h
View File

@ -18,7 +18,6 @@
#define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R2 0x0000000000000040ULL
#define ISA_MIPS64R2 0x0000000000000100ULL
#define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS64R3 0x0000000000000400ULL
#define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R5 0x0000000000000800ULL
@ -78,7 +77,7 @@
/* MIPS Technologies "Release 2" */ /* MIPS Technologies "Release 2" */
#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2) #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
/* MIPS Technologies "Release 3" */ /* MIPS Technologies "Release 3" */
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)

4
target/mips/translate.c
View File

@ -28621,7 +28621,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_DINSM: case OPC_DINSM:
case OPC_DINSU: case OPC_DINSU:
case OPC_DINS: case OPC_DINS:
check_insn(ctx, ISA_MIPS64R2); check_insn(ctx, ISA_MIPS32R2);
check_mips_64(ctx); check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd); gen_bitops(ctx, op1, rt, rs, sa, rd);
break; break;
@ -28641,7 +28641,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special3_r6(env, ctx); decode_opc_special3_r6(env, ctx);
break; break;
default: default:
check_insn(ctx, ISA_MIPS64R2); check_insn(ctx, ISA_MIPS32R2);
check_mips_64(ctx); check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode); op2 = MASK_DBSHFL(ctx->opcode);
gen_bshfl(ctx, op2, rt, rd); gen_bshfl(ctx, op2, rt, rd);