SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

tcg: Include 'tcg-target-has.h' once in 'tcg-has.h'

Browse Source 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-14-philmd@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-08 22:51:54 +01:00
parent 8ae72b38b5
commit f15d00a4c1
11 changed files with 2 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tcg/aarch64/tcg-target.h
View File

@ -47,8 +47,6 @@ typedef enum {
#define TCG_TARGET_NB_REGS 64 #define TCG_TARGET_NB_REGS 64
#include "tcg-target-has.h"
#define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_DEFAULT_MO (0)
#endif /* AARCH64_TCG_TARGET_H */ #endif /* AARCH64_TCG_TARGET_H */

2
tcg/arm/tcg-target.h
View File

@ -70,8 +70,6 @@ typedef enum {
#define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_NB_REGS 32
#include "tcg-target-has.h"
#define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_DEFAULT_MO (0)
#endif #endif

2
tcg/i386/tcg-target.h
View File

@ -88,8 +88,6 @@ typedef enum {
TCG_REG_CALL_STACK = TCG_REG_ESP TCG_REG_CALL_STACK = TCG_REG_ESP
} TCGReg; } TCGReg;
#include "tcg-target-has.h"
/* This defines the natural memory order supported by this /* This defines the natural memory order supported by this
* architecture before guarantees made by various barrier * architecture before guarantees made by various barrier
* instructions. * instructions.

2
tcg/loongarch64/tcg-target.h
View File

@ -85,8 +85,6 @@ typedef enum {
TCG_VEC_TMP0 = TCG_REG_V23, TCG_VEC_TMP0 = TCG_REG_V23,
} TCGReg; } TCGReg;
#include "tcg-target-has.h"
#define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_DEFAULT_MO (0)
#endif /* LOONGARCH_TCG_TARGET_H */ #endif /* LOONGARCH_TCG_TARGET_H */

2
tcg/mips/tcg-target.h
View File

@ -70,8 +70,6 @@ typedef enum {
TCG_AREG0 = TCG_REG_S8, TCG_AREG0 = TCG_REG_S8,
} TCGReg; } TCGReg;
#include "tcg-target-has.h"
#define TCG_TARGET_DEFAULT_MO 0 #define TCG_TARGET_DEFAULT_MO 0
#endif #endif

2
tcg/ppc/tcg-target.h
View File

@ -53,8 +53,6 @@ typedef enum {
TCG_AREG0 = TCG_REG_R27 TCG_AREG0 = TCG_REG_R27
} TCGReg; } TCGReg;
#include "tcg-target-has.h"
#define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_DEFAULT_MO (0)
#endif #endif

2
tcg/riscv/tcg-target.h
View File

@ -57,8 +57,6 @@ typedef enum {
TCG_REG_TMP2 = TCG_REG_T4, TCG_REG_TMP2 = TCG_REG_T4,
} TCGReg; } TCGReg;
#include "tcg-target-has.h"
#define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_DEFAULT_MO (0)
#endif #endif

2
tcg/s390x/tcg-target.h
View File

@ -51,8 +51,6 @@ typedef enum TCGReg {
#define TCG_TARGET_NB_REGS 64 #define TCG_TARGET_NB_REGS 64
#include "tcg-target-has.h"
#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
#endif #endif

2
tcg/sparc64/tcg-target.h
View File

@ -66,8 +66,6 @@ typedef enum {
#define TCG_AREG0 TCG_REG_I0 #define TCG_AREG0 TCG_REG_I0
#include "tcg-target-has.h"
#define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_DEFAULT_MO (0)
#endif #endif

2
tcg/tcg-has.h
View File

@ -7,6 +7,8 @@
#ifndef TCG_HAS_H #ifndef TCG_HAS_H
#define TCG_HAS_H #define TCG_HAS_H
#include "tcg-target-has.h"
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
/* Turn some undef macros into false macros. */ /* Turn some undef macros into false macros. */
#define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0

2
tcg/tci/tcg-target.h
View File

@ -44,8 +44,6 @@
#define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_INSN_UNIT_SIZE 4
#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
#include "tcg-target-has.h"
/* Number of registers available. */ /* Number of registers available. */
#define TCG_TARGET_NB_REGS 16 #define TCG_TARGET_NB_REGS 16