target/openrisc: Reorg tlb lookup
While openrisc has a split i/d tlb, qemu does not. Perform a lookup on both i & d tlbs in parallel and put the composite rights into qemu's tlb. This avoids ping-ponging the qemu tlb between EXEC and READ. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Richard Henderson
Stafford Horne
parent
1cc9e5d896
commit
f0655423ca
@ -237,14 +237,6 @@ enum {
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UXE = (1 << 7),
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};
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/* check if tlb available */
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enum {
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TLBRET_INVALID = -3,
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TLBRET_NOMATCH = -2,
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TLBRET_BADADDR = -1,
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TLBRET_MATCH = 0
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};
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typedef struct OpenRISCTLBEntry {
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uint32_t mr;
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uint32_t tr;
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@ -29,148 +29,78 @@
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#endif
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#ifndef CONFIG_USER_ONLY
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static inline int get_phys_nommu(hwaddr *physical, int *prot,
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static inline void get_phys_nommu(hwaddr *phys_addr, int *prot,
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target_ulong address)
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{
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*physical = address;
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*phys_addr = address;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TLBRET_MATCH;
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}
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static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
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target_ulong address, int rw, bool supervisor)
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static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot,
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target_ulong addr, int need, bool super)
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{
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int vpn = address >> TARGET_PAGE_BITS;
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int idx = vpn & TLB_MASK;
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int right = 0;
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uint32_t mr = cpu->env.tlb.itlb[idx].mr;
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uint32_t tr = cpu->env.tlb.itlb[idx].tr;
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int idx = (addr >> TARGET_PAGE_BITS) & TLB_MASK;
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uint32_t imr = cpu->env.tlb.itlb[idx].mr;
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uint32_t itr = cpu->env.tlb.itlb[idx].tr;
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uint32_t dmr = cpu->env.tlb.dtlb[idx].mr;
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uint32_t dtr = cpu->env.tlb.dtlb[idx].tr;
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int right, match, valid;
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if ((mr >> TARGET_PAGE_BITS) != vpn) {
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return TLBRET_NOMATCH;
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}
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if (!(mr & 1)) {
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return TLBRET_INVALID;
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}
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if (supervisor) {
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if (tr & SXE) {
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right |= PAGE_EXEC;
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}
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/* If the ITLB and DTLB indexes map to the same page, we want to
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load all permissions all at once. If the destination pages do
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not match, zap the one we don't need. */
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if (unlikely((itr ^ dtr) & TARGET_PAGE_MASK)) {
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if (need & PAGE_EXEC) {
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dmr = dtr = 0;
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} else {
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if (tr & UXE) {
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right |= PAGE_EXEC;
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imr = itr = 0;
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}
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}
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if ((rw & 2) && ((right & PAGE_EXEC) == 0)) {
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return TLBRET_BADADDR;
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}
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*physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK);
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/* Check if either of the entries matches the source address. */
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match = (imr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_EXEC;
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match |= (dmr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_READ | PAGE_WRITE;
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/* Check if either of the entries is valid. */
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valid = imr & 1 ? PAGE_EXEC : 0;
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valid |= dmr & 1 ? PAGE_READ | PAGE_WRITE : 0;
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valid &= match;
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/* Collect the permissions from the entries. */
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right = itr & (super ? SXE : UXE) ? PAGE_EXEC : 0;
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right |= dtr & (super ? SRE : URE) ? PAGE_READ : 0;
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right |= dtr & (super ? SWE : UWE) ? PAGE_WRITE : 0;
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right &= valid;
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/* Note that above we validated that itr and dtr match on page.
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So oring them together changes nothing without having to
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check which one we needed. We also want to store to these
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variables even on failure, as it avoids compiler warnings. */
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*phys_addr = ((itr | dtr) & TARGET_PAGE_MASK) | (addr & ~TARGET_PAGE_MASK);
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*prot = right;
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return TLBRET_MATCH;
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qemu_log_mask(CPU_LOG_MMU,
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"MMU lookup: need %d match %d valid %d right %d -> %s\n",
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need, match, valid, right, (need & right) ? "OK" : "FAIL");
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/* Check the collective permissions are present. */
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if (likely(need & right)) {
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return 0; /* success! */
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}
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static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
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target_ulong address, int rw, bool supervisor)
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{
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int vpn = address >> TARGET_PAGE_BITS;
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int idx = vpn & TLB_MASK;
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int right = 0;
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uint32_t mr = cpu->env.tlb.dtlb[idx].mr;
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uint32_t tr = cpu->env.tlb.dtlb[idx].tr;
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if ((mr >> TARGET_PAGE_BITS) != vpn) {
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return TLBRET_NOMATCH;
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}
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if (!(mr & 1)) {
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return TLBRET_INVALID;
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}
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if (supervisor) {
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if (tr & SRE) {
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right |= PAGE_READ;
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}
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if (tr & SWE) {
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right |= PAGE_WRITE;
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}
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/* Determine what kind of failure we have. */
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if (need & valid) {
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return need & PAGE_EXEC ? EXCP_IPF : EXCP_DPF;
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} else {
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if (tr & URE) {
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right |= PAGE_READ;
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return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS;
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}
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if (tr & UWE) {
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right |= PAGE_WRITE;
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}
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}
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if (!(rw & 1) && ((right & PAGE_READ) == 0)) {
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return TLBRET_BADADDR;
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}
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if ((rw & 1) && ((right & PAGE_WRITE) == 0)) {
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return TLBRET_BADADDR;
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}
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*physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK);
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*prot = right;
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return TLBRET_MATCH;
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}
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static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical,
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int *prot, target_ulong address, int rw)
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{
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bool supervisor = (cpu->env.sr & SR_SM) != 0;
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int ret;
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/* Assume nommu results for a moment. */
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ret = get_phys_nommu(physical, prot, address);
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/* Overwrite with TLB lookup if enabled. */
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if (rw == MMU_INST_FETCH) {
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if (cpu->env.sr & SR_IME) {
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ret = get_phys_code(cpu, physical, prot, address, rw, supervisor);
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}
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} else {
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if (cpu->env.sr & SR_DME) {
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ret = get_phys_data(cpu, physical, prot, address, rw, supervisor);
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}
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}
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return ret;
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}
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#endif
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static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
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target_ulong address,
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int rw, int tlb_error)
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static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address,
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int exception)
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{
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CPUState *cs = CPU(cpu);
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int exception = 0;
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switch (tlb_error) {
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default:
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if (rw == 2) {
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exception = EXCP_IPF;
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} else {
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exception = EXCP_DPF;
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}
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break;
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#ifndef CONFIG_USER_ONLY
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case TLBRET_BADADDR:
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if (rw == 2) {
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exception = EXCP_IPF;
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} else {
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exception = EXCP_DPF;
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}
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break;
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case TLBRET_INVALID:
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case TLBRET_NOMATCH:
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/* No TLB match for a mapped address */
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if (rw == 2) {
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exception = EXCP_ITLBMISS;
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} else {
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exception = EXCP_DTLBMISS;
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}
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break;
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#endif
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}
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cs->exception_index = exception;
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cpu->env.eear = address;
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@ -182,7 +112,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
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{
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#ifdef CONFIG_USER_ONLY
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0);
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raise_mmu_exception(cpu, address, EXCP_DPF);
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return 1;
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#else
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g_assert_not_reached();
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@ -193,27 +123,32 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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int prot, excp, sr = cpu->env.sr;
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hwaddr phys_addr;
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int prot;
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int miss;
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/* Check memory for any kind of address, since during debug the
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gdb can ask for anything, check data tlb for address */
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miss = get_phys_addr(cpu, &phys_addr, &prot, addr, 0);
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switch (sr & (SR_DME | SR_IME)) {
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case SR_DME | SR_IME:
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/* The mmu is definitely enabled. */
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excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
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PAGE_EXEC | PAGE_READ | PAGE_WRITE,
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(sr & SR_SM) != 0);
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return excp ? -1 : phys_addr;
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/* Check instruction tlb */
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if (miss) {
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miss = get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH);
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default:
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/* The mmu is partially enabled, and we don't really have
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a "real" access type. Begin by trying the mmu, but if
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that fails try again without. */
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excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
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PAGE_EXEC | PAGE_READ | PAGE_WRITE,
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(sr & SR_SM) != 0);
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if (!excp) {
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return phys_addr;
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}
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/* fallthru */
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/* Last, fall back to a plain address */
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if (miss) {
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miss = get_phys_nommu(&phys_addr, &prot, addr);
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}
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if (miss) {
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return -1;
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} else {
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case 0:
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/* The mmu is definitely disabled; lookups never fail. */
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get_phys_nommu(&phys_addr, &prot, addr);
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return phys_addr;
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}
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}
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@ -222,37 +157,28 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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int ret, prot = 0;
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hwaddr physical = 0;
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int prot, excp;
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hwaddr phys_addr;
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if (mmu_idx == MMU_NOMMU_IDX) {
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ret = get_phys_nommu(&physical, &prot, addr);
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/* The mmu is disabled; lookups never fail. */
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get_phys_nommu(&phys_addr, &prot, addr);
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excp = 0;
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} else {
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bool super = mmu_idx == MMU_SUPERVISOR_IDX;
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if (access_type == MMU_INST_FETCH) {
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ret = get_phys_code(cpu, &physical, &prot, addr, 2, super);
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} else {
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ret = get_phys_data(cpu, &physical, &prot, addr,
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access_type == MMU_DATA_STORE, super);
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}
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int need = (access_type == MMU_INST_FETCH ? PAGE_EXEC
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: access_type == MMU_DATA_STORE ? PAGE_WRITE
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: PAGE_READ);
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excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super);
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}
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if (ret == TLBRET_MATCH) {
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tlb_set_page(cs, addr & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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} else if (ret < 0) {
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int rw;
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if (access_type == MMU_INST_FETCH) {
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rw = 2;
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} else if (access_type == MMU_DATA_STORE) {
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rw = 1;
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} else {
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rw = 0;
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}
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cpu_openrisc_raise_mmu_exception(cpu, addr, rw, ret);
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/* Raise Exception. */
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if (unlikely(excp)) {
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raise_mmu_exception(cpu, addr, excp);
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cpu_loop_exit_restore(cs, retaddr);
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}
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tlb_set_page(cs, addr & TARGET_PAGE_MASK,
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phys_addr & TARGET_PAGE_MASK, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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}
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#endif
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