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target/arm: Convert disas_adc_sbc to decodetree

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This includes ADC, SBC, ADCS, SBCS.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:29:42 -06:00 committed by Peter Maydell
parent 4d1c86efb3
commit eeb4a51962
2 changed files with 22 additions and 27 deletions
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6
target/arm/tcg/a64.decode
View File

@ -746,6 +746,12 @@ ADDS_ext . 01 01011001 ..... ... ... ..... ..... @addsub_ext
SUBS_ext . 11 01011001 ..... ... ... ..... ..... @addsub_ext SUBS_ext . 11 01011001 ..... ... ... ..... ..... @addsub_ext
# Add/subtract (carry) # Add/subtract (carry)
ADC . 00 11010000 ..... 000000 ..... ..... @rrr_sf
ADCS . 01 11010000 ..... 000000 ..... ..... @rrr_sf
SBC . 10 11010000 ..... 000000 ..... ..... @rrr_sf
SBCS . 11 11010000 ..... 000000 ..... ..... @rrr_sf
# Rotate right into flags # Rotate right into flags
# Evaluate into flags # Evaluate into flags
# Conditional compare (regster) # Conditional compare (regster)

43
target/arm/tcg/translate-a64.c
View File

@ -8017,42 +8017,34 @@ TRANS(SMSUBL, do_muladd, a, true, true, MO_SL)
TRANS(UMADDL, do_muladd, a, true, false, MO_UL) TRANS(UMADDL, do_muladd, a, true, false, MO_UL)
TRANS(UMSUBL, do_muladd, a, true, true, MO_UL) TRANS(UMSUBL, do_muladd, a, true, true, MO_UL)
/* Add/subtract (with carry) static bool do_adc_sbc(DisasContext *s, arg_rrr_sf *a,
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 bool is_sub, bool setflags)
* +--+--+--+------------------------+------+-------------+------+-----+
* |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
* +--+--+--+------------------------+------+-------------+------+-----+
*/
static void disas_adc_sbc(DisasContext *s, uint32_t insn)
{ {
unsigned int sf, op, setflags, rm, rn, rd;
TCGv_i64 tcg_y, tcg_rn, tcg_rd; TCGv_i64 tcg_y, tcg_rn, tcg_rd;
sf = extract32(insn, 31, 1); tcg_rd = cpu_reg(s, a->rd);
op = extract32(insn, 30, 1); tcg_rn = cpu_reg(s, a->rn);
setflags = extract32(insn, 29, 1);
rm = extract32(insn, 16, 5);
rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5);
tcg_rd = cpu_reg(s, rd); if (is_sub) {
tcg_rn = cpu_reg(s, rn);
if (op) {
tcg_y = tcg_temp_new_i64(); tcg_y = tcg_temp_new_i64();
tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); tcg_gen_not_i64(tcg_y, cpu_reg(s, a->rm));
} else { } else {
tcg_y = cpu_reg(s, rm); tcg_y = cpu_reg(s, a->rm);
} }
if (setflags) { if (setflags) {
gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y); gen_adc_CC(a->sf, tcg_rd, tcg_rn, tcg_y);
} else { } else {
gen_adc(sf, tcg_rd, tcg_rn, tcg_y); gen_adc(a->sf, tcg_rd, tcg_rn, tcg_y);
} }
return true;
} }
TRANS(ADC, do_adc_sbc, a, false, false)
TRANS(SBC, do_adc_sbc, a, true, false)
TRANS(ADCS, do_adc_sbc, a, false, true)
TRANS(SBCS, do_adc_sbc, a, true, true)
/* /*
* Rotate right into flags * Rotate right into flags
* 31 30 29 21 15 10 5 4 0 * 31 30 29 21 15 10 5 4 0
@ -8305,10 +8297,6 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
switch (op2) { switch (op2) {
case 0x0: case 0x0:
switch (op3) { switch (op3) {
case 0x00: /* Add/subtract (with carry) */
disas_adc_sbc(s, insn);
break;
case 0x01: /* Rotate right into flags */ case 0x01: /* Rotate right into flags */
case 0x21: case 0x21:
disas_rotate_right_into_flags(s, insn); disas_rotate_right_into_flags(s, insn);
@ -8322,6 +8310,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
break; break;
default: default:
case 0x00: /* Add/subtract (with carry) */
goto do_unallocated; goto do_unallocated;
} }
break; break;