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target/riscv: Add counter delegation definitions

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This adds definitions for counter delegation, including the new
scountinhibit register and the mstateen.CD bit.

Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-6-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Kaiwen Xue 2025-01-10 00:21:34 -08:00 committed by Alistair Francis
parent f2548886b3
commit e84af93560
3 changed files with 9 additions and 1 deletions
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1
target/riscv/cpu.h
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@ -392,6 +392,7 @@ struct CPUArchState {
uint32_t scounteren; uint32_t scounteren;
uint32_t mcounteren; uint32_t mcounteren;
uint32_t scountinhibit;
uint32_t mcountinhibit; uint32_t mcountinhibit;
/* PMU cycle & instret privilege mode filtering */ /* PMU cycle & instret privilege mode filtering */

8
target/riscv/cpu_bits.h
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@ -210,6 +210,9 @@
#define CSR_SSTATEEN2 0x10E #define CSR_SSTATEEN2 0x10E
#define CSR_SSTATEEN3 0x10F #define CSR_SSTATEEN3 0x10F
/* Supervisor Counter Delegation */
#define CSR_SCOUNTINHIBIT 0x120
/* Supervisor Trap Handling */ /* Supervisor Trap Handling */
#define CSR_SSCRATCH 0x140 #define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141 #define CSR_SEPC 0x141
@ -779,6 +782,7 @@ typedef enum RISCVException {
#define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7) #define MENVCFG_CBZE BIT(7)
#define MENVCFG_PMM (3ULL << 32) #define MENVCFG_PMM (3ULL << 32)
#define MENVCFG_CDE (1ULL << 60)
#define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_ADUE (1ULL << 61)
#define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_PBMTE (1ULL << 62)
#define MENVCFG_STCE (1ULL << 63) #define MENVCFG_STCE (1ULL << 63)
@ -826,7 +830,9 @@ typedef enum RISCVException {
#define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63
#define ISELECT_MASK_AIA 0x1ff #define ISELECT_MASK_AIA 0x1ff
/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ /* [M|S|VS]SELCT value for Indirect CSR Access Extension */
#define ISELECT_CD_FIRST 0x40
#define ISELECT_CD_LAST 0x5f
#define ISELECT_MASK_SXCSRIND 0xfff #define ISELECT_MASK_SXCSRIND 0xfff
/* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */

1
target/riscv/machine.c
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@ -423,6 +423,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.siselect, RISCVCPU), VMSTATE_UINTTL(env.siselect, RISCVCPU),
VMSTATE_UINT32(env.scounteren, RISCVCPU), VMSTATE_UINT32(env.scounteren, RISCVCPU),
VMSTATE_UINT32(env.mcounteren, RISCVCPU), VMSTATE_UINT32(env.mcounteren, RISCVCPU),
VMSTATE_UINT32(env.scountinhibit, RISCVCPU),
VMSTATE_UINT32(env.mcountinhibit, RISCVCPU), VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0, VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
vmstate_pmu_ctr_state, PMUCTRState), vmstate_pmu_ctr_state, PMUCTRState),