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target/i386: adapt gen_shift_count for SHLD/SHRD

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SHLD/SHRD can have 3 register operands - s->T0, s->T1 and either
1 or CL - and therefore decode->op[2] is taken by the low part
of the register being shifted.  Pass X86_OP_* to gen_shift_count
from its current callers and hardcode cpu_regs[R_ECX] as the
shift count.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2024-05-09 10:15:05 +02:00
parent 87b2037b65
commit e4e5981daf
1 changed files with 10 additions and 10 deletions
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20
target/i386/tcg/emit.c.inc
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@ -2878,16 +2878,16 @@ static void gen_PUSHF(DisasContext *s, X86DecodedInsn *decode)
} }
static MemOp gen_shift_count(DisasContext *s, X86DecodedInsn *decode, static MemOp gen_shift_count(DisasContext *s, X86DecodedInsn *decode,
bool *can_be_zero, TCGv *count) bool *can_be_zero, TCGv *count, int unit)
{ {
MemOp ot = decode->op[0].ot; MemOp ot = decode->op[0].ot;
int mask = (ot <= MO_32 ? 0x1f : 0x3f); int mask = (ot <= MO_32 ? 0x1f : 0x3f);
*can_be_zero = false; *can_be_zero = false;
switch (decode->op[2].unit) { switch (unit) {
case X86_OP_INT: case X86_OP_INT:
*count = tcg_temp_new(); *count = tcg_temp_new();
tcg_gen_andi_tl(*count, s->T1, mask); tcg_gen_andi_tl(*count, cpu_regs[R_ECX], mask);
*can_be_zero = true; *can_be_zero = true;
break; break;
@ -3072,7 +3072,7 @@ static void gen_RCL(DisasContext *s, X86DecodedInsn *decode)
bool have_1bit_cin, can_be_zero; bool have_1bit_cin, can_be_zero;
TCGv count; TCGv count;
TCGLabel *zero_label = NULL; TCGLabel *zero_label = NULL;
MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit);
TCGv low, high, low_count; TCGv low, high, low_count;
if (!count) { if (!count) {
@ -3124,7 +3124,7 @@ static void gen_RCR(DisasContext *s, X86DecodedInsn *decode)
bool have_1bit_cin, can_be_zero; bool have_1bit_cin, can_be_zero;
TCGv count; TCGv count;
TCGLabel *zero_label = NULL; TCGLabel *zero_label = NULL;
MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit);
TCGv low, high, high_count; TCGv low, high, high_count;
if (!count) { if (!count) {
@ -3302,7 +3302,7 @@ static void gen_ROL(DisasContext *s, X86DecodedInsn *decode)
{ {
bool can_be_zero; bool can_be_zero;
TCGv count; TCGv count;
MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit);
TCGv_i32 temp32, count32; TCGv_i32 temp32, count32;
TCGv old = tcg_temp_new(); TCGv old = tcg_temp_new();
@ -3330,7 +3330,7 @@ static void gen_ROR(DisasContext *s, X86DecodedInsn *decode)
{ {
bool can_be_zero; bool can_be_zero;
TCGv count; TCGv count;
MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit);
TCGv_i32 temp32, count32; TCGv_i32 temp32, count32;
TCGv old = tcg_temp_new(); TCGv old = tcg_temp_new();
@ -3442,7 +3442,7 @@ static void gen_SAR(DisasContext *s, X86DecodedInsn *decode)
{ {
bool can_be_zero; bool can_be_zero;
TCGv count; TCGv count;
MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit);
if (!count) { if (!count) {
return; return;
@ -3570,7 +3570,7 @@ static void gen_SHL(DisasContext *s, X86DecodedInsn *decode)
{ {
bool can_be_zero; bool can_be_zero;
TCGv count; TCGv count;
MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit);
if (!count) { if (!count) {
return; return;
@ -3602,7 +3602,7 @@ static void gen_SHR(DisasContext *s, X86DecodedInsn *decode)
{ {
bool can_be_zero; bool can_be_zero;
TCGv count; TCGv count;
MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit);
if (!count) { if (!count) {
return; return;