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Implement size bit in PowerPC 64 comparisons.

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Allow 'weight' field in sync instruction.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3250 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-09-27 04:47:25 +00:00
parent 4118a97030
commit e3878283de
1 changed files with 4 additions and 4 deletions
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8
target-ppc/translate.c
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@ -969,7 +969,7 @@ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
{ \ { \
gen_op_load_gpr_T0(rA(ctx->opcode)); \ gen_op_load_gpr_T0(rA(ctx->opcode)); \
gen_op_load_gpr_T1(rB(ctx->opcode)); \ gen_op_load_gpr_T1(rB(ctx->opcode)); \
if (ctx->sf_mode) \ if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
gen_op_##name##_64(); \ gen_op_##name##_64(); \
else \ else \
gen_op_##name(); \ gen_op_##name(); \
@ -993,7 +993,7 @@ GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
{ {
gen_op_load_gpr_T0(rA(ctx->opcode)); gen_op_load_gpr_T0(rA(ctx->opcode));
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
if (ctx->sf_mode) if (ctx->sf_mode && (ctx->opcode & 0x00200000))
gen_op_cmpi_64(SIMM(ctx->opcode)); gen_op_cmpi_64(SIMM(ctx->opcode));
else else
#endif #endif
@ -1007,7 +1007,7 @@ GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
{ {
gen_op_load_gpr_T0(rA(ctx->opcode)); gen_op_load_gpr_T0(rA(ctx->opcode));
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
if (ctx->sf_mode) if (ctx->sf_mode && (ctx->opcode & 0x00200000))
gen_op_cmpli_64(UIMM(ctx->opcode)); gen_op_cmpli_64(UIMM(ctx->opcode));
else else
#endif #endif
@ -2565,7 +2565,7 @@ GEN_HANDLER(stdcx_, 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
#endif /* defined(TARGET_PPC64) */ #endif /* defined(TARGET_PPC64) */
/* sync */ /* sync */
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM_SYNC) GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03CF0801, PPC_MEM_SYNC)
{ {
} }