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hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs

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When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit  528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Versatile Express board however expects a fixed set of 64
interrupts (see the fixed IRQ length when this board was added in
commit 2055283bcc8 ("hw/vexpress: Add model of ARM Versatile Express
board"). Add the GIC_EXT_IRQS definition (with a comment) to make
that explicit.

Except explicitly setting a property value to its same implicit
value, there is no logical change intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-02-12 16:43:31 +01:00 committed by Peter Maydell
parent 92fea7f2e7
commit e2e5266c45
1 changed files with 5 additions and 2 deletions
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7
hw/arm/vexpress.c
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@ -51,6 +51,8 @@
#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
#define GIC_EXT_IRQS 64 /* Versatile Express A9 development board */
/* Number of virtio transports to create (0..8; limited by /* Number of virtio transports to create (0..8; limited by
* number of available IRQ lines). * number of available IRQ lines).
*/ */
@ -241,6 +243,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type,
*/ */
dev = qdev_new(privdev); dev = qdev_new(privdev);
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL);
busdev = SYS_BUS_DEVICE(dev); busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal); sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, periphbase); sysbus_mmio_map(busdev, 0, periphbase);
@ -251,7 +254,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type,
* external interrupts starting from 32 (because there * external interrupts starting from 32 (because there
* are internal interrupts 0..31). * are internal interrupts 0..31).
*/ */
for (n = 0; n < 64; n++) { for (n = 0; n < GIC_EXT_IRQS; n++) {
pic[n] = qdev_get_gpio_in(dev, n); pic[n] = qdev_get_gpio_in(dev, n);
} }
@ -543,7 +546,7 @@ static void vexpress_common_init(MachineState *machine)
VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
VEDBoardInfo *daughterboard = vmc->daughterboard; VEDBoardInfo *daughterboard = vmc->daughterboard;
DeviceState *dev, *sysctl, *pl041; DeviceState *dev, *sysctl, *pl041;
qemu_irq pic[64]; qemu_irq pic[GIC_EXT_IRQS];
uint32_t sys_id; uint32_t sys_id;
DriveInfo *dinfo; DriveInfo *dinfo;
PFlashCFI01 *pflash0; PFlashCFI01 *pflash0;