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accel: Prefer cached CpuClass over CPU_GET_CLASS() macro

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CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250122093028.52416-6-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-01-21 12:11:09 +01:00
parent 30e76638eb
commit e27fa95fb9
4 changed files with 11 additions and 15 deletions
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12
accel/accel-target.c
View File

@ -113,22 +113,20 @@ void accel_init_interfaces(AccelClass *ac)
void accel_cpu_instance_init(CPUState *cpu) void accel_cpu_instance_init(CPUState *cpu)
{ {
CPUClass *cc = CPU_GET_CLASS(cpu); if (cpu->cc->accel_cpu && cpu->cc->accel_cpu->cpu_instance_init) {
cpu->cc->accel_cpu->cpu_instance_init(cpu);
if (cc->accel_cpu && cc->accel_cpu->cpu_instance_init) {
cc->accel_cpu->cpu_instance_init(cpu);
} }
} }
bool accel_cpu_common_realize(CPUState *cpu, Error **errp) bool accel_cpu_common_realize(CPUState *cpu, Error **errp)
{ {
CPUClass *cc = CPU_GET_CLASS(cpu);
AccelState *accel = current_accel(); AccelState *accel = current_accel();
AccelClass *acc = ACCEL_GET_CLASS(accel); AccelClass *acc = ACCEL_GET_CLASS(accel);
/* target specific realization */ /* target specific realization */
if (cc->accel_cpu && cc->accel_cpu->cpu_target_realize if (cpu->cc->accel_cpu
&& !cc->accel_cpu->cpu_target_realize(cpu, errp)) { && cpu->cc->accel_cpu->cpu_target_realize
&& !cpu->cc->accel_cpu->cpu_target_realize(cpu, errp)) {
return false; return false;
} }

3
accel/tcg/tcg-accel-ops.c
View File

@ -121,10 +121,9 @@ static inline int xlat_gdb_type(CPUState *cpu, int gdbtype)
[GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS, [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
}; };
CPUClass *cc = CPU_GET_CLASS(cpu);
int cputype = xlat[gdbtype]; int cputype = xlat[gdbtype];
if (cc->gdb_stop_before_watchpoint) { if (cpu->cc->gdb_stop_before_watchpoint) {
cputype |= BP_STOP_BEFORE_ACCESS; cputype |= BP_STOP_BEFORE_ACCESS;
} }
return cputype; return cputype;

2
accel/tcg/translate-all.c
View File

@ -630,7 +630,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
* to account for the re-execution of the branch. * to account for the re-execution of the branch.
*/ */
n = 1; n = 1;
cc = CPU_GET_CLASS(cpu); cc = cpu->cc;
if (cc->tcg_ops->io_recompile_replay_branch && if (cc->tcg_ops->io_recompile_replay_branch &&
cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) { cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) {
cpu->neg.icount_decr.u16.low++; cpu->neg.icount_decr.u16.low++;

9
accel/tcg/watchpoint.c
View File

@ -68,7 +68,6 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
MemTxAttrs attrs, int flags, uintptr_t ra) MemTxAttrs attrs, int flags, uintptr_t ra)
{ {
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUWatchpoint *wp; CPUWatchpoint *wp;
assert(tcg_enabled()); assert(tcg_enabled());
@ -84,9 +83,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
return; return;
} }
if (cc->tcg_ops->adjust_watchpoint_address) { if (cpu->cc->tcg_ops->adjust_watchpoint_address) {
/* this is currently used only by ARM BE32 */ /* this is currently used only by ARM BE32 */
addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); addr = cpu->cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
} }
assert((flags & ~BP_MEM_ACCESS) == 0); assert((flags & ~BP_MEM_ACCESS) == 0);
@ -118,8 +117,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
wp->hitattrs = attrs; wp->hitattrs = attrs;
if (wp->flags & BP_CPU if (wp->flags & BP_CPU
&& cc->tcg_ops->debug_check_watchpoint && cpu->cc->tcg_ops->debug_check_watchpoint
&& !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { && !cpu->cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
wp->flags &= ~BP_WATCHPOINT_HIT; wp->flags &= ~BP_WATCHPOINT_HIT;
continue; continue;
} }