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hw/arm/bcm2836: Introduce the BCM2835 SoC

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Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201024170127.3592182-7-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-10-24 19:01:24 +02:00 committed by Peter Maydell
parent f5600924ad
commit df6cf08dea
3 changed files with 37 additions and 0 deletions
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34
hw/arm/bcm2836.c
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@ -89,6 +89,25 @@ static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
return true; return true;
} }
static void bcm2835_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
if (!bcm283x_common_realize(dev, errp)) {
return;
}
if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
return;
}
/* Connect irq/fiq outputs from the interrupt controller. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
}
static void bcm2836_realize(DeviceState *dev, Error **errp) static void bcm2836_realize(DeviceState *dev, Error **errp)
{ {
BCM283XState *s = BCM283X(dev); BCM283XState *s = BCM283X(dev);
@ -159,6 +178,17 @@ static void bcm283x_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false; dc->user_creatable = false;
} }
static void bcm2835_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
bc->core_count = 1;
bc->peri_base = 0x20000000;
dc->realize = bcm2835_realize;
};
static void bcm2836_class_init(ObjectClass *oc, void *data) static void bcm2836_class_init(ObjectClass *oc, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
@ -189,6 +219,10 @@ static void bcm2837_class_init(ObjectClass *oc, void *data)
static const TypeInfo bcm283x_types[] = { static const TypeInfo bcm283x_types[] = {
{ {
.name = TYPE_BCM2835,
.parent = TYPE_BCM283X,
.class_init = bcm2835_class_init,
}, {
.name = TYPE_BCM2836, .name = TYPE_BCM2836,
.parent = TYPE_BCM283X, .parent = TYPE_BCM283X,
.class_init = bcm2836_class_init, .class_init = bcm2836_class_init,

2
hw/arm/raspi.c
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@ -70,6 +70,7 @@ FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
FIELD(REV_CODE, STYLE, 23, 1); FIELD(REV_CODE, STYLE, 23, 1);
typedef enum RaspiProcessorId { typedef enum RaspiProcessorId {
PROCESSOR_ID_BCM2835 = 0,
PROCESSOR_ID_BCM2836 = 1, PROCESSOR_ID_BCM2836 = 1,
PROCESSOR_ID_BCM2837 = 2, PROCESSOR_ID_BCM2837 = 2,
} RaspiProcessorId; } RaspiProcessorId;
@ -78,6 +79,7 @@ static const struct {
const char *type; const char *type;
int cores_count; int cores_count;
} soc_property[] = { } soc_property[] = {
[PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1},
[PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS}, [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
[PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS}, [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
}; };

1
include/hw/arm/bcm2836.h
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@ -26,6 +26,7 @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
* them, code using these devices should always handle them via the * them, code using these devices should always handle them via the
* BCM283x base class, so they have no BCM2836(obj) etc macros. * BCM283x base class, so they have no BCM2836(obj) etc macros.
*/ */
#define TYPE_BCM2835 "bcm2835"
#define TYPE_BCM2836 "bcm2836" #define TYPE_BCM2836 "bcm2836"
#define TYPE_BCM2837 "bcm2837" #define TYPE_BCM2837 "bcm2837"