SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

target/ppc: Wire up BookE ATB registers for e500 family

Browse Source 
From the Freescale PowerPC Architecture Primer:

  Alternate time base APU. This APU, implemented on the e500v2, defines
  a 64-bit time base counter that differs from the PowerPC defined time
  base in that it is not writable and counts at a different, and
  typically much higher, frequency. The alternate time base always
  counts up, wrapping when the 64-bit count overflows.

This implementation of ATB uses the same frequency as the TB. The
existing spr_read_atbu/l functions are unused without this patch
to wire them into the SPR.

RTEMS uses this SPR on the e6500, though this hasn't been tested.

Message-ID: <20241219034035.1826173-6-npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-12-19 13:40:35 +10:00
parent e8291ec16d
commit d8a624515a
1 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
target/ppc/cpu_init.c
View File

@ -922,6 +922,18 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
#endif
}
static void register_atb_sprs(CPUPPCState *env)
{
spr_register(env, SPR_ATBL, "ATBL",
&spr_read_atbl, SPR_NOACCESS,
&spr_read_atbl, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_ATBU, "ATBU",
&spr_read_atbu, SPR_NOACCESS,
&spr_read_atbu, SPR_NOACCESS,
0x00000000);
}
/* SPR specific to PowerPC 440 implementation */
static void register_440_sprs(CPUPPCState *env)
{
@ -2911,6 +2923,11 @@ static void init_proc_e500(CPUPPCState *env, int version)
register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
register_usprgh_sprs(env);
if (version != fsl_e500v1) {
/* e500v1 has no support for alternate timebase */
register_atb_sprs(env);
}
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,