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target/arm: Use tcg_constant in handle_sys

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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-26 09:30:02 -07:00 committed by Peter Maydell
parent 181115d906
commit d7eeaa0956
1 changed files with 9 additions and 22 deletions
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31
target/arm/translate-a64.c
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@ -1818,19 +1818,14 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
/* Emit code to perform further access permissions checks at /* Emit code to perform further access permissions checks at
* runtime; this may result in an exception. * runtime; this may result in an exception.
*/ */
TCGv_ptr tmpptr;
TCGv_i32 tcg_syn, tcg_isread;
uint32_t syndrome; uint32_t syndrome;
gen_a64_set_pc_im(s->pc_curr);
tmpptr = tcg_const_ptr(ri);
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
tcg_syn = tcg_const_i32(syndrome); gen_a64_set_pc_im(s->pc_curr);
tcg_isread = tcg_const_i32(isread); gen_helper_access_check_cp_reg(cpu_env,
gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread); tcg_constant_ptr(ri),
tcg_temp_free_ptr(tmpptr); tcg_constant_i32(syndrome),
tcg_temp_free_i32(tcg_syn); tcg_constant_i32(isread));
tcg_temp_free_i32(tcg_isread);
} else if (ri->type & ARM_CP_RAISES_EXC) { } else if (ri->type & ARM_CP_RAISES_EXC) {
/* /*
* The readfn or writefn might raise an exception; * The readfn or writefn might raise an exception;
@ -1861,17 +1856,15 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
case ARM_CP_DC_ZVA: case ARM_CP_DC_ZVA:
/* Writes clear the aligned block of memory which rt points into. */ /* Writes clear the aligned block of memory which rt points into. */
if (s->mte_active[0]) { if (s->mte_active[0]) {
TCGv_i32 t_desc;
int desc = 0; int desc = 0;
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
t_desc = tcg_const_i32(desc);
tcg_rt = new_tmp_a64(s); tcg_rt = new_tmp_a64(s);
gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, rt)); gen_helper_mte_check_zva(tcg_rt, cpu_env,
tcg_temp_free_i32(t_desc); tcg_constant_i32(desc), cpu_reg(s, rt));
} else { } else {
tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); tcg_rt = clean_data_tbi(s, cpu_reg(s, rt));
} }
@ -1935,10 +1928,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
if (ri->type & ARM_CP_CONST) { if (ri->type & ARM_CP_CONST) {
tcg_gen_movi_i64(tcg_rt, ri->resetvalue); tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
} else if (ri->readfn) { } else if (ri->readfn) {
TCGv_ptr tmpptr; gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_constant_ptr(ri));
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
tcg_temp_free_ptr(tmpptr);
} else { } else {
tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
} }
@ -1947,10 +1937,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
/* If not forbidden by access permissions, treat as WI */ /* If not forbidden by access permissions, treat as WI */
return; return;
} else if (ri->writefn) { } else if (ri->writefn) {
TCGv_ptr tmpptr; gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tcg_rt);
tmpptr = tcg_const_ptr(ri);
gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
tcg_temp_free_ptr(tmpptr);
} else { } else {
tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
} }