SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

target/hppa: Fix extrw and depw with sar for hppa64

Browse Source 
These are 32-bit operations regardless of processor.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-19 16:07:14 +02:00
parent 1e9ab9fbe0
commit d781cb7798
1 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
target/hppa/translate.c
View File

@ -3230,7 +3230,9 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a)
tmp = tcg_temp_new(); tmp = tcg_temp_new();
/* Recall that SAR is using big-endian bit numbering. */ /* Recall that SAR is using big-endian bit numbering. */
tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); tcg_gen_andi_reg(tmp, cpu_sar, 31);
tcg_gen_xori_reg(tmp, tmp, 31);
if (a->se) { if (a->se) {
tcg_gen_sar_reg(dest, src, tmp); tcg_gen_sar_reg(dest, src, tmp);
tcg_gen_sextract_reg(dest, dest, 0, len); tcg_gen_sextract_reg(dest, dest, 0, len);
@ -3355,7 +3357,8 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
tmp = tcg_temp_new(); tmp = tcg_temp_new();
/* Convert big-endian bit numbering in SAR to left-shift. */ /* Convert big-endian bit numbering in SAR to left-shift. */
tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1); tcg_gen_andi_reg(shift, cpu_sar, 31);
tcg_gen_xori_reg(shift, shift, 31);
mask = tcg_temp_new(); mask = tcg_temp_new();
tcg_gen_movi_reg(mask, msb + (msb - 1)); tcg_gen_movi_reg(mask, msb + (msb - 1));