target/riscv: fixes a bug against ssamoswap
behavior in M-mode
Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds `ssamoswap` instruction. `ssamoswap` takes the code-point from existing reserved encoding (and not a zimop like other shadow stack instructions). If shadow stack is not enabled (via xenvcfg.SSE) and effective priv is less than M then `ssamoswap` must result in an illegal instruction exception. However if effective priv is M, then `ssamoswap` results in store/AMO access fault. See Section "22.2.3. Shadow Stack Memory Protection" of priv spec. Fixes: f06bfe3dc38c ("target/riscv: implement zicfiss instructions") Reported-by: Ved Shanbhogue <ved@rivosinc.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250306064636.452396-2-debug@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -15,6 +15,13 @@
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_ZICFISS(ctx) do { \
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if (!ctx->cfg_ptr->ext_zicfiss) { \
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return false; \
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} \
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} while (0)
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static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)
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{
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if (!ctx->bcfi_enabled) {
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@ -77,6 +84,11 @@ static bool trans_ssrdp(DisasContext *ctx, arg_ssrdp *a)
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static bool trans_ssamoswap_w(DisasContext *ctx, arg_amoswap_w *a)
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{
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REQUIRE_A_OR_ZAAMO(ctx);
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REQUIRE_ZICFISS(ctx);
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if (ctx->priv == PRV_M) {
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generate_exception(ctx, RISCV_EXCP_STORE_AMO_ACCESS_FAULT);
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}
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if (!ctx->bcfi_enabled) {
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return false;
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}
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@ -97,6 +109,11 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_amoswap_w *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_A_OR_ZAAMO(ctx);
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REQUIRE_ZICFISS(ctx);
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if (ctx->priv == PRV_M) {
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generate_exception(ctx, RISCV_EXCP_STORE_AMO_ACCESS_FAULT);
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}
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if (!ctx->bcfi_enabled) {
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return false;
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}
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