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target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return

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Using ~0 as the mask on the aarch64->aarch32 exception return
was not even as correct as the CPSR_ERET_MASK that we had used
on the aarch32->aarch32 exception return.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200208125816.14954-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-08 12:58:04 +00:00 committed by Peter Maydell
parent 437864216d
commit d203cabd1b
1 changed files with 3 additions and 2 deletions
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5
target/arm/helper-a64.c
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@ -959,7 +959,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
{ {
int cur_el = arm_current_el(env); int cur_el = arm_current_el(env);
unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
uint32_t spsr = env->banked_spsr[spsr_idx]; uint32_t mask, spsr = env->banked_spsr[spsr_idx];
int new_el; int new_el;
bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; bool return_to_aa64 = (spsr & PSTATE_nRW) == 0;
@ -1014,7 +1014,8 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
* will sort the register banks out for us, and we've already * will sort the register banks out for us, and we've already
* caught all the bad-mode cases in el_from_spsr(). * caught all the bad-mode cases in el_from_spsr().
*/ */
cpsr_write(env, spsr, ~0, CPSRWriteRaw); mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
cpsr_write(env, spsr, mask, CPSRWriteRaw);
if (!arm_singlestep_active(env)) { if (!arm_singlestep_active(env)) {
env->uncached_cpsr &= ~PSTATE_SS; env->uncached_cpsr &= ~PSTATE_SS;
} }