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target/arm: Convert VCMLA, VCADD size field to MO_* in decode

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The VCMLA and VCADD insns have a size field which is 0 for fp16
and 1 for fp32 (note that this is the reverse of the Neon 3-same
encoding!). Convert it to MO_* values in decode for consistency.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-4-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-09-03 14:32:09 +01:00
parent 0ae715c658
commit d186a4854c
2 changed files with 24 additions and 16 deletions
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18
target/arm/neon-shared.decode
View File

@ -34,11 +34,17 @@
%vd_dp 22:1 12:4 %vd_dp 22:1 12:4
%vd_sp 12:4 22:1 %vd_sp 12:4 22:1
VCMLA 1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \ # For VCMLA/VCADD insns, convert the single-bit size field
vm=%vm_dp vn=%vn_dp vd=%vd_dp # which is 0 for fp16 and 1 for fp32 into a MO_* constant.
# (Note that this is the reverse of the sense of the 1-bit size
# field in the 3same_fp Neon insns.)
%vcadd_size 20:1 !function=plus1
VCADD 1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \ VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size
VCADD 1111 110 rot:1 1 . 0 . .... .... 1000 . q:1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size
# VUDOT and VSDOT # VUDOT and VSDOT
VDOT 1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \ VDOT 1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
@ -51,9 +57,9 @@ VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1 vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \ VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
vn=%vn_dp vd=%vd_dp size=0 vn=%vn_dp vd=%vd_dp size=1
VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \ VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0 vm=%vm_dp vn=%vn_dp vd=%vd_dp size=2 index=0
VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \ VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
vm=%vm_dp vn=%vn_dp vd=%vd_dp vm=%vm_dp vn=%vn_dp vd=%vd_dp

22
target/arm/translate-neon.c.inc
View File

@ -168,7 +168,7 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
gen_helper_gvec_3_ptr *fn_gvec_ptr; gen_helper_gvec_3_ptr *fn_gvec_ptr;
if (!dc_isar_feature(aa32_vcma, s) if (!dc_isar_feature(aa32_vcma, s)
|| (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { || (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s))) {
return false; return false;
} }
@ -187,8 +187,9 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
} }
opr_sz = (1 + a->q) * 8; opr_sz = (1 + a->q) * 8;
fpst = fpstatus_ptr(a->size == 0 ? FPST_STD_F16 : FPST_STD); fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; fn_gvec_ptr = (a->size == MO_16) ?
gen_helper_gvec_fcmlah : gen_helper_gvec_fcmlas;
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vn),
vfp_reg_offset(1, a->vm), vfp_reg_offset(1, a->vm),
@ -205,7 +206,7 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
gen_helper_gvec_3_ptr *fn_gvec_ptr; gen_helper_gvec_3_ptr *fn_gvec_ptr;
if (!dc_isar_feature(aa32_vcma, s) if (!dc_isar_feature(aa32_vcma, s)
|| (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { || (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s))) {
return false; return false;
} }
@ -224,8 +225,9 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
} }
opr_sz = (1 + a->q) * 8; opr_sz = (1 + a->q) * 8;
fpst = fpstatus_ptr(a->size == 0 ? FPST_STD_F16 : FPST_STD); fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; fn_gvec_ptr = (a->size == MO_16) ?
gen_helper_gvec_fcaddh : gen_helper_gvec_fcadds;
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vn),
vfp_reg_offset(1, a->vm), vfp_reg_offset(1, a->vm),
@ -307,7 +309,7 @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
if (!dc_isar_feature(aa32_vcma, s)) { if (!dc_isar_feature(aa32_vcma, s)) {
return false; return false;
} }
if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) { if (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s)) {
return false; return false;
} }
@ -325,10 +327,10 @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
return true; return true;
} }
fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx fn_gvec_ptr = (a->size == MO_16) ?
: gen_helper_gvec_fcmlah_idx); gen_helper_gvec_fcmlah_idx : gen_helper_gvec_fcmlas_idx;
opr_sz = (1 + a->q) * 8; opr_sz = (1 + a->q) * 8;
fpst = fpstatus_ptr(a->size == 0 ? FPST_STD_F16 : FPST_STD); fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vn),
vfp_reg_offset(1, a->vm), vfp_reg_offset(1, a->vm),