hw/fsi: Introduce IBM's FSI master
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI master. CFAM is hanging out of FSI master which is a bus controller.
The FSI master: A controller in the platform service processor (e.g.
BMC) driving CFAM engine accesses into the POWER chip. At the
hardware level FSI is a bit-based protocol supporting synchronous and
DMA-driven accesses of engines in a CFAM.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - move FSICFAMState object under FSIMasterState
- introduced fsi_master_init()
- reworked fsi_master_realize()
- dropped FSIBus definition ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Ninad Palsule
Cédric Le Goater
parent
f32f8e4d20
commit
ca03310737
170
hw/fsi/fsi-master.c
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170
hw/fsi/fsi-master.c
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@ -0,0 +1,170 @@
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/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Copyright (C) 2024 IBM Corp.
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*
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* IBM Flexible Service Interface master
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/fsi/fsi-master.h"
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#define TYPE_OP_BUS "opb"
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#define TO_REG(x) ((x) >> 2)
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#define FSI_MENP0 TO_REG(0x010)
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#define FSI_MENP32 TO_REG(0x014)
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#define FSI_MSENP0 TO_REG(0x018)
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#define FSI_MLEVP0 TO_REG(0x018)
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#define FSI_MSENP32 TO_REG(0x01c)
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#define FSI_MLEVP32 TO_REG(0x01c)
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#define FSI_MCENP0 TO_REG(0x020)
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#define FSI_MREFP0 TO_REG(0x020)
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#define FSI_MCENP32 TO_REG(0x024)
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#define FSI_MREFP32 TO_REG(0x024)
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#define FSI_MVER TO_REG(0x074)
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#define FSI_MRESP0 TO_REG(0x0d0)
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#define FSI_MRESB0 TO_REG(0x1d0)
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#define FSI_MRESB0_RESET_GENERAL BIT(31)
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#define FSI_MRESB0_RESET_ERROR BIT(30)
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static uint64_t fsi_master_read(void *opaque, hwaddr addr, unsigned size)
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{
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FSIMasterState *s = FSI_MASTER(opaque);
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int reg = TO_REG(addr);
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trace_fsi_master_read(addr, size);
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if (reg >= FSI_MASTER_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n",
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__func__, addr, size);
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return 0;
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}
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return s->regs[reg];
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}
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static void fsi_master_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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FSIMasterState *s = FSI_MASTER(opaque);
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int reg = TO_REG(addr);
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trace_fsi_master_write(addr, size, data);
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if (reg >= FSI_MASTER_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out of bounds write: %"HWADDR_PRIx" for %u\n",
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__func__, addr, size);
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return;
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}
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switch (reg) {
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case FSI_MENP0:
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s->regs[FSI_MENP0] = data;
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break;
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case FSI_MENP32:
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s->regs[FSI_MENP32] = data;
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break;
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case FSI_MSENP0:
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s->regs[FSI_MENP0] |= data;
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break;
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case FSI_MSENP32:
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s->regs[FSI_MENP32] |= data;
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break;
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case FSI_MCENP0:
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s->regs[FSI_MENP0] &= ~data;
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break;
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case FSI_MCENP32:
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s->regs[FSI_MENP32] &= ~data;
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break;
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case FSI_MRESP0:
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/* Perform necessary resets leave register 0 to indicate no errors */
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break;
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case FSI_MRESB0:
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if (data & FSI_MRESB0_RESET_GENERAL) {
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device_cold_reset(DEVICE(opaque));
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}
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if (data & FSI_MRESB0_RESET_ERROR) {
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/* FIXME: this seems dubious */
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device_cold_reset(DEVICE(opaque));
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}
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break;
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default:
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s->regs[reg] = data;
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}
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}
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static const struct MemoryRegionOps fsi_master_ops = {
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.read = fsi_master_read,
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.write = fsi_master_write,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void fsi_master_init(Object *o)
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{
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FSIMasterState *s = FSI_MASTER(o);
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object_initialize_child(o, "cfam", &s->cfam, TYPE_FSI_CFAM);
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qbus_init(&s->bus, sizeof(s->bus), TYPE_FSI_BUS, DEVICE(s), NULL);
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memory_region_init_io(&s->iomem, OBJECT(s), &fsi_master_ops, s,
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TYPE_FSI_MASTER, 0x10000000);
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memory_region_init(&s->opb2fsi, OBJECT(s), "fsi.opb2fsi", 0x10000000);
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}
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static void fsi_master_realize(DeviceState *dev, Error **errp)
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{
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FSIMasterState *s = FSI_MASTER(dev);
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if (!qdev_realize(DEVICE(&s->cfam), BUS(&s->bus), errp)) {
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return;
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}
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/* address ? */
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memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.mr);
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}
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static void fsi_master_reset(DeviceState *dev)
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{
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FSIMasterState *s = FSI_MASTER(dev);
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/* Initialize registers */
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memset(s->regs, 0, sizeof(s->regs));
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/* ASPEED default */
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s->regs[FSI_MVER] = 0xe0050101;
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}
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static void fsi_master_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->bus_type = TYPE_OP_BUS;
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dc->desc = "FSI Master";
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dc->realize = fsi_master_realize;
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dc->reset = fsi_master_reset;
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}
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static const TypeInfo fsi_master_info = {
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.name = TYPE_FSI_MASTER,
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.parent = TYPE_DEVICE,
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.instance_init = fsi_master_init,
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.instance_size = sizeof(FSIMasterState),
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.class_init = fsi_master_class_init,
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};
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static void fsi_register_types(void)
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{
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type_register_static(&fsi_master_info);
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}
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type_init(fsi_register_types);
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@ -1 +1 @@
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system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c'))
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system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c','fsi-master.c'))
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@ -7,3 +7,5 @@ fsi_cfam_config_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64
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fsi_cfam_unimplemented_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
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fsi_cfam_unimplemented_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
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fsi_cfam_config_write_noaddr(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
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fsi_master_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=%d"
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fsi_master_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size=%d value=0x%"PRIx64
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32
include/hw/fsi/fsi-master.h
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32
include/hw/fsi/fsi-master.h
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@ -0,0 +1,32 @@
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/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Copyright (C) 2024 IBM Corp.
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*
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* IBM Flexible Service Interface Master
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*/
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#ifndef FSI_FSI_MASTER_H
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#define FSI_FSI_MASTER_H
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#include "exec/memory.h"
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#include "hw/qdev-core.h"
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#include "hw/fsi/fsi.h"
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#include "hw/fsi/cfam.h"
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#define TYPE_FSI_MASTER "fsi.master"
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OBJECT_DECLARE_SIMPLE_TYPE(FSIMasterState, FSI_MASTER)
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#define FSI_MASTER_NR_REGS ((0x2e0 >> 2) + 1)
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typedef struct FSIMasterState {
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DeviceState parent;
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MemoryRegion iomem;
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MemoryRegion opb2fsi;
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FSIBus bus;
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uint32_t regs[FSI_MASTER_NR_REGS];
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FSICFAMState cfam;
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} FSIMasterState;
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#endif /* FSI_FSI_H */
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