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target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-05 10:53:30 -07:00
parent baf3dbf258
commit c6d83e4ff5
2 changed files with 56 additions and 42 deletions
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7
target/sparc/insns.decode
View File

@ -239,8 +239,11 @@ DONE 10 00000 111110 00000 0 0000000000000
RETRY 10 00001 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000
FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2 FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2
FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2
FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2
FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2
FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2
FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2
{ {
[ [
@ -266,9 +269,13 @@ FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2
BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r
FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d
FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s
FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d
FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s
FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @r_r1 # FNOT1d
FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s
FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d
FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s
] ]
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1

91
target/sparc/translate.c
View File

@ -44,7 +44,9 @@
#else #else
# define gen_helper_clear_softint(E, S) qemu_build_not_reached() # define gen_helper_clear_softint(E, S) qemu_build_not_reached()
# define gen_helper_done(E) qemu_build_not_reached() # define gen_helper_done(E) qemu_build_not_reached()
# define gen_helper_fabsd(D, S) qemu_build_not_reached()
# define gen_helper_flushw(E) qemu_build_not_reached() # define gen_helper_flushw(E) qemu_build_not_reached()
# define gen_helper_fnegd(D, S) qemu_build_not_reached()
# define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached()
# define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached()
# define gen_helper_restored(E) qemu_build_not_reached() # define gen_helper_restored(E) qemu_build_not_reached()
@ -1420,6 +1422,24 @@ static void gen_op_fabss(TCGv_i32 dst, TCGv_i32 src)
gen_helper_fabss(dst, src); gen_helper_fabss(dst, src);
} }
static void gen_op_fmovd(TCGv_i64 dst, TCGv_i64 src)
{
gen_op_clear_ieee_excp_and_FTT();
tcg_gen_mov_i64(dst, src);
}
static void gen_op_fnegd(TCGv_i64 dst, TCGv_i64 src)
{
gen_op_clear_ieee_excp_and_FTT();
gen_helper_fnegd(dst, src);
}
static void gen_op_fabsd(TCGv_i64 dst, TCGv_i64 src)
{
gen_op_clear_ieee_excp_and_FTT();
gen_helper_fabsd(dst, src);
}
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
{ {
@ -1639,21 +1659,6 @@ static void gen_fop_DD(DisasContext *dc, int rd, int rs,
gen_store_fpr_D(dc, rd, dst); gen_store_fpr_D(dc, rd, dst);
} }
#ifdef TARGET_SPARC64
static void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
void (*gen)(TCGv_i64, TCGv_i64))
{
TCGv_i64 dst, src;
src = gen_load_fpr_D(dc, rs);
dst = gen_dest_fpr_D(dc, rd);
gen(dst, src);
gen_store_fpr_D(dc, rd, dst);
}
#endif
static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64)) void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
{ {
@ -4829,6 +4834,28 @@ TRANS(FABSs, ALL, do_ff, a, gen_op_fabss)
TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32)
TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32)
static bool do_dd(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_i64, TCGv_i64))
{
TCGv_i64 dst, src;
if (gen_trap_ifnofpu(dc)) {
return true;
}
dst = gen_dest_fpr_D(dc, a->rd);
src = gen_load_fpr_D(dc, a->rs);
func(dst, src);
gen_store_fpr_D(dc, a->rd, dst);
return advance_pc(dc);
}
TRANS(FMOVd, 64, do_dd, a, gen_op_fmovd)
TRANS(FNEGd, 64, do_dd, a, gen_op_fnegd)
TRANS(FABSd, 64, do_dd, a, gen_op_fabsd)
TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64)
TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64)
#define CHECK_IU_FEATURE(dc, FEATURE) \ #define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn; goto illegal_insn;
@ -4872,6 +4899,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x1: /* fmovs */ case 0x1: /* fmovs */
case 0x5: /* fnegs */ case 0x5: /* fnegs */
case 0x9: /* fabss */ case 0x9: /* fabss */
case 0x2: /* V9 fmovd */
case 0x6: /* V9 fnegd */
case 0xa: /* V9 fabsd */
g_assert_not_reached(); /* in decodetree */ g_assert_not_reached(); /* in decodetree */
case 0x29: /* fsqrts */ case 0x29: /* fsqrts */
gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
@ -4974,24 +5004,14 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi); gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
break; break;
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
case 0x2: /* V9 fmovd */
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
gen_store_fpr_D(dc, rd, cpu_src1_64);
break;
case 0x3: /* V9 fmovq */ case 0x3: /* V9 fmovq */
CHECK_FPU_FEATURE(dc, FLOAT128); CHECK_FPU_FEATURE(dc, FLOAT128);
gen_move_Q(dc, rd, rs2); gen_move_Q(dc, rd, rs2);
break; break;
case 0x6: /* V9 fnegd */
gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
break;
case 0x7: /* V9 fnegq */ case 0x7: /* V9 fnegq */
CHECK_FPU_FEATURE(dc, FLOAT128); CHECK_FPU_FEATURE(dc, FLOAT128);
gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
break; break;
case 0xa: /* V9 fabsd */
gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
break;
case 0xb: /* V9 fabsq */ case 0xb: /* V9 fabsq */
CHECK_FPU_FEATURE(dc, FLOAT128); CHECK_FPU_FEATURE(dc, FLOAT128);
gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
@ -5204,6 +5224,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x06b: /* VIS I fnot1s */ case 0x06b: /* VIS I fnot1s */
case 0x075: /* VIS I fsrc1s */ case 0x075: /* VIS I fsrc1s */
case 0x079: /* VIS I fsrc2s */ case 0x079: /* VIS I fsrc2s */
case 0x066: /* VIS I fnot2 */
case 0x06a: /* VIS I fnot1 */
case 0x074: /* VIS I fsrc1 */
case 0x078: /* VIS I fsrc2 */
g_assert_not_reached(); /* in decodetree */ g_assert_not_reached(); /* in decodetree */
case 0x020: /* VIS I fcmple16 */ case 0x020: /* VIS I fcmple16 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
@ -5387,10 +5411,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32); gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
break; break;
case 0x066: /* VIS I fnot2 */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
break;
case 0x068: /* VIS I fandnot1 */ case 0x068: /* VIS I fandnot1 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
@ -5399,10 +5419,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32); gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
break; break;
case 0x06a: /* VIS I fnot1 */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
break;
case 0x06c: /* VIS I fxor */ case 0x06c: /* VIS I fxor */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
@ -5435,10 +5451,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32); gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
break; break;
case 0x074: /* VIS I fsrc1 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
gen_store_fpr_D(dc, rd, cpu_src1_64);
break; break;
case 0x076: /* VIS I fornot2 */ case 0x076: /* VIS I fornot2 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
@ -5448,11 +5460,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32); gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
break; break;
case 0x078: /* VIS I fsrc2 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
gen_store_fpr_D(dc, rd, cpu_src1_64);
break;
case 0x07a: /* VIS I fornot1 */ case 0x07a: /* VIS I fornot1 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);