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target/riscv: Fix format for indentation

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Fix identation problems, and try to use the same indentation strategy
in the same file.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-04-05 16:58:11 +08:00 committed by Alistair Francis
parent 38256529f3
commit c45eff30cb
12 changed files with 238 additions and 232 deletions
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4
target/riscv/arch_dump.c
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@ -180,8 +180,8 @@ int cpu_get_dump_info(ArchDumpInfo *info,
info->d_class = ELFCLASS32; info->d_class = ELFCLASS32;
#endif #endif
info->d_endian = (env->mstatus & MSTATUS_UBE) != 0 info->d_endian = (env->mstatus & MSTATUS_UBE) != 0 ?
? ELFDATA2MSB : ELFDATA2LSB; ELFDATA2MSB : ELFDATA2LSB;
return 0; return 0;
} }

2
target/riscv/cpu.c
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@ -54,7 +54,7 @@ struct isa_ext_data {
}; };
#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
/** /**
* Here are the ordering rules of extension naming defined by RISC-V * Here are the ordering rules of extension naming defined by RISC-V

7
target/riscv/cpu_helper.c
View File

@ -1001,8 +1001,8 @@ restart:
*/ */
MemoryRegion *mr; MemoryRegion *mr;
hwaddr l = sizeof(target_ulong), addr1; hwaddr l = sizeof(target_ulong), addr1;
mr = address_space_translate(cs->as, pte_addr, mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
&addr1, &l, false, MEMTXATTRS_UNSPECIFIED); false, MEMTXATTRS_UNSPECIFIED);
if (memory_region_is_ram(mr)) { if (memory_region_is_ram(mr)) {
target_ulong *pte_pa = target_ulong *pte_pa =
qemu_map_ram_ptr(mr->ram_block, addr1); qemu_map_ram_ptr(mr->ram_block, addr1);
@ -1281,7 +1281,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
false); false);
qemu_log_mask(CPU_LOG_MMU, qemu_log_mask(CPU_LOG_MMU,
"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " "%s 2nd-stage address=%" VADDR_PRIx
" ret %d physical "
HWADDR_FMT_plx " prot %d\n", HWADDR_FMT_plx " prot %d\n",
__func__, im_address, ret, pa, prot2); __func__, im_address, ret, pa, prot2);

4
target/riscv/op_helper.c
View File

@ -367,8 +367,8 @@ void helper_wfi(CPURISCVState *env)
if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) || if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) ||
(rvs && prv_u && !env->virt_enabled)) { (rvs && prv_u && !env->virt_enabled)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else if (env->virt_enabled && (prv_u || } else if (env->virt_enabled &&
(prv_s && get_field(env->hstatus, HSTATUS_VTW)))) { (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else { } else {
cs->halted = 1; cs->halted = 1;

11
target/riscv/pmp.c
View File

@ -220,8 +220,8 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
{ {
int result = 0; int result = 0;
if ((addr >= env->pmp_state.addr[pmp_index].sa) if ((addr >= env->pmp_state.addr[pmp_index].sa) &&
&& (addr <= env->pmp_state.addr[pmp_index].ea)) { (addr <= env->pmp_state.addr[pmp_index].ea)) {
result = 1; result = 1;
} else { } else {
result = 0; result = 0;
@ -234,7 +234,8 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
* Check if the address has required RWX privs when no PMP entry is matched. * Check if the address has required RWX privs when no PMP entry is matched.
*/ */
static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, target_ulong size, pmp_priv_t privs,
pmp_priv_t *allowed_privs,
target_ulong mode) target_ulong mode)
{ {
bool ret; bool ret;
@ -297,8 +298,8 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
* Return negtive value if no match * Return negtive value if no match
*/ */
int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, target_ulong size, pmp_priv_t privs,
target_ulong mode) pmp_priv_t *allowed_privs, target_ulong mode)
{ {
int i = 0; int i = 0;
int ret = -1; int ret = -1;

3
target/riscv/pmp.h
View File

@ -73,7 +73,8 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val); target_ulong val);
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, target_ulong size, pmp_priv_t privs,
pmp_priv_t *allowed_privs,
target_ulong mode); target_ulong mode);
target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index, target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
target_ulong tlb_sa, target_ulong tlb_ea); target_ulong tlb_sa, target_ulong tlb_ea);

61
target/riscv/vector_helper.c
View File

@ -50,10 +50,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
} }
} }
if ((sew > cpu->cfg.elen) if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
|| vill
|| (ediv != 0)
|| (reserved != 0)) {
/* only set vill bit. */ /* only set vill bit. */
env->vill = 1; env->vill = 1;
env->vtype = 0; env->vtype = 0;
@ -1308,7 +1305,8 @@ GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f)
/* generate the helpers for shift instructions with one vector and one scalar */ /* generate the helpers for shift instructions with one vector and one scalar */
#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \ #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \ void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \ { \
uint32_t vm = vext_vm(desc); \ uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \ uint32_t vl = env->vl; \
@ -1735,9 +1733,9 @@ GEN_VEXT_VX(vmulhsu_vx_d, 8)
/* Vector Integer Divide Instructions */ /* Vector Integer Divide Instructions */
#define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M) #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
#define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M) #define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M)
#define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\ #define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : \
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M) unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
#define DO_REM(N, M) (unlikely(M == 0) ? N :\ #define DO_REM(N, M) (unlikely(M == 0) ? N : \
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M) unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU) RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU)
@ -2277,7 +2275,8 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
/* generate helpers for fixed point instructions with OPIVX format */ /* generate helpers for fixed point instructions with OPIVX format */
#define GEN_VEXT_VX_RM(NAME, ESZ) \ #define GEN_VEXT_VX_RM(NAME, ESZ) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \ void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \ { \
vext_vx_rm_2(vd, v0, s1, vs2, env, desc, \ vext_vx_rm_2(vd, v0, s1, vs2, env, desc, \
do_##NAME, ESZ); \ do_##NAME, ESZ); \
@ -3319,20 +3318,20 @@ GEN_VEXT_VF(vfmacc_vf_d, 8)
static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s) static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{ {
return float16_muladd(a, b, d, return float16_muladd(a, b, d, float_muladd_negate_c |
float_muladd_negate_c | float_muladd_negate_product, s); float_muladd_negate_product, s);
} }
static uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s) static uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{ {
return float32_muladd(a, b, d, return float32_muladd(a, b, d, float_muladd_negate_c |
float_muladd_negate_c | float_muladd_negate_product, s); float_muladd_negate_product, s);
} }
static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s) static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{ {
return float64_muladd(a, b, d, return float64_muladd(a, b, d, float_muladd_negate_c |
float_muladd_negate_c | float_muladd_negate_product, s); float_muladd_negate_product, s);
} }
RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16) RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
@ -3434,20 +3433,20 @@ GEN_VEXT_VF(vfmadd_vf_d, 8)
static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s) static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{ {
return float16_muladd(d, b, a, return float16_muladd(d, b, a, float_muladd_negate_c |
float_muladd_negate_c | float_muladd_negate_product, s); float_muladd_negate_product, s);
} }
static uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s) static uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{ {
return float32_muladd(d, b, a, return float32_muladd(d, b, a, float_muladd_negate_c |
float_muladd_negate_c | float_muladd_negate_product, s); float_muladd_negate_product, s);
} }
static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s) static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{ {
return float64_muladd(d, b, a, return float64_muladd(d, b, a, float_muladd_negate_c |
float_muladd_negate_c | float_muladd_negate_product, s); float_muladd_negate_product, s);
} }
RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16) RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
@ -3545,14 +3544,15 @@ static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{ {
return float32_muladd(float16_to_float32(a, true, s), return float32_muladd(float16_to_float32(a, true, s),
float16_to_float32(b, true, s), d, float16_to_float32(b, true, s), d,
float_muladd_negate_c | float_muladd_negate_product, s); float_muladd_negate_c | float_muladd_negate_product,
s);
} }
static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s) static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{ {
return float64_muladd(float32_to_float64(a, s), return float64_muladd(float32_to_float64(a, s), float32_to_float64(b, s),
float32_to_float64(b, s), d, d, float_muladd_negate_c |
float_muladd_negate_c | float_muladd_negate_product, s); float_muladd_negate_product, s);
} }
RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16) RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
@ -4422,8 +4422,8 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
\ \
for (i = env->vstart; i < vl; i++) { \ for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
*((ETYPE *)vd + H(i)) \ *((ETYPE *)vd + H(i)) = \
= (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
} \ } \
env->vstart = 0; \ env->vstart = 0; \
/* set tail elements to 1s */ \ /* set tail elements to 1s */ \
@ -4564,7 +4564,8 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
/* Vector Single-Width Integer Reduction Instructions */ /* Vector Single-Width Integer Reduction Instructions */
#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \ #define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \ void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \ { \
uint32_t vm = vext_vm(desc); \ uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \ uint32_t vl = env->vl; \
@ -5013,7 +5014,8 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
#define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \ #define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \
static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \ static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \ void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \ { \
typedef uint##BITWIDTH##_t ETYPE; \ typedef uint##BITWIDTH##_t ETYPE; \
uint32_t vm = vext_vm(desc); \ uint32_t vm = vext_vm(desc); \
@ -5061,7 +5063,8 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
#define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \ #define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \
static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \ static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \ void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \ { \
typedef uint##BITWIDTH##_t ETYPE; \ typedef uint##BITWIDTH##_t ETYPE; \
uint32_t vm = vext_vm(desc); \ uint32_t vm = vext_vm(desc); \