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include/exec: Use uintptr_t in CPUTLBEntry

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Since we no longer support 64-bit guests on 32-bit hosts,
we can use a 32-bit type on a 32-bit host.  This shrinks
the size of the structure to 16 bytes on a 32-bit host.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-02-04 19:34:51 -08:00
parent a70af12add
commit bf455ec50b
5 changed files with 19 additions and 46 deletions
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21
accel/tcg/cputlb.c
View File

@ -104,22 +104,15 @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
{ {
/* Do not rearrange the CPUTLBEntry structure members. */ /* Do not rearrange the CPUTLBEntry structure members. */
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) != QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=
MMU_DATA_LOAD * sizeof(uint64_t)); MMU_DATA_LOAD * sizeof(uintptr_t));
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) != QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=
MMU_DATA_STORE * sizeof(uint64_t)); MMU_DATA_STORE * sizeof(uintptr_t));
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) != QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
MMU_INST_FETCH * sizeof(uint64_t)); MMU_INST_FETCH * sizeof(uintptr_t));
#if TARGET_LONG_BITS == 32 const uintptr_t *ptr = &entry->addr_idx[access_type];
/* Use qatomic_read, in case of addr_write; only care about low bits. */
const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
ptr += HOST_BIG_ENDIAN;
return qatomic_read(ptr);
#else
const uint64_t *ptr = &entry->addr_idx[access_type];
/* ofs might correspond to .addr_write, so use qatomic_read */ /* ofs might correspond to .addr_write, so use qatomic_read */
return qatomic_read(ptr); return qatomic_read(ptr);
#endif
} }
static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry) static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry)
@ -899,14 +892,8 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
addr &= TARGET_PAGE_MASK; addr &= TARGET_PAGE_MASK;
addr += tlb_entry->addend; addr += tlb_entry->addend;
if ((addr - start) < length) { if ((addr - start) < length) {
#if TARGET_LONG_BITS == 32
uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
ptr_write += HOST_BIG_ENDIAN;
qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
#else
qatomic_set(&tlb_entry->addr_write, qatomic_set(&tlb_entry->addr_write,
tlb_entry->addr_write | TLB_NOTDIRTY); tlb_entry->addr_write | TLB_NOTDIRTY);
#endif
} }
} }
} }

10
include/exec/tlb-common.h
View File

@ -19,14 +19,14 @@
#ifndef EXEC_TLB_COMMON_H #ifndef EXEC_TLB_COMMON_H
#define EXEC_TLB_COMMON_H 1 #define EXEC_TLB_COMMON_H 1
#define CPU_TLB_ENTRY_BITS 5 #define CPU_TLB_ENTRY_BITS (HOST_LONG_BITS == 32 ? 4 : 5)
/* Minimalized TLB entry for use by TCG fast path. */ /* Minimalized TLB entry for use by TCG fast path. */
typedef union CPUTLBEntry { typedef union CPUTLBEntry {
struct { struct {
uint64_t addr_read; uintptr_t addr_read;
uint64_t addr_write; uintptr_t addr_write;
uint64_t addr_code; uintptr_t addr_code;
/* /*
* Addend to virtual address to get host address. IO accesses * Addend to virtual address to get host address. IO accesses
* use the corresponding iotlb value. * use the corresponding iotlb value.
@ -37,7 +37,7 @@ typedef union CPUTLBEntry {
* Padding to get a power of two size, as well as index * Padding to get a power of two size, as well as index
* access to addr_{read,write,code}. * access to addr_{read,write,code}.
*/ */
uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)]; uintptr_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uintptr_t)];
} CPUTLBEntry; } CPUTLBEntry;
QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));

1
tcg/arm/tcg-target.c.inc
View File

@ -1500,7 +1500,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
* Add the tlb_table pointer, creating the CPUTLBEntry address in R1. * Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
* Load the tlb comparator into R2 and the fast path addend into R1. * Load the tlb comparator into R2 and the fast path addend into R1.
*/ */
QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
if (cmp_off == 0) { if (cmp_off == 0) {
tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
} else { } else {

12
tcg/mips/tcg-target.c.inc
View File

@ -1262,18 +1262,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
/* Add the tlb_table pointer, creating the CPUTLBEntry address. */ /* Add the tlb_table pointer, creating the CPUTLBEntry address. */
tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { /* Load the tlb comparator. */
/* Load the (low half) tlb comparator. */ if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3,
cmp_off + HOST_BIG_ENDIAN * 4); cmp_off + HOST_BIG_ENDIAN * 4);
} else { } else {
tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off); tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off);
} }
if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) { /* Load the tlb addend for the fast path. */
/* Load the tlb addend for the fast path. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
}
/* /*
* Mask the page bits, keeping the alignment bits to compare against. * Mask the page bits, keeping the alignment bits to compare against.

21
tcg/ppc/tcg-target.c.inc
View File

@ -2490,27 +2490,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
/* /*
* Load the (low part) TLB comparator into TMP2. * Load the TLB comparator into TMP2.
* For 64-bit host, always load the entire 64-bit slot for simplicity. * For 64-bit host, always load the entire 64-bit slot for simplicity.
* We will ignore the high bits with tcg_out_cmp(..., addr_type). * We will ignore the high bits with tcg_out_cmp(..., addr_type).
*/ */
if (TCG_TARGET_REG_BITS == 64) { if (cmp_off == 0) {
if (cmp_off == 0) { tcg_out32(s, (TCG_TARGET_REG_BITS == 64 ? LDUX : LWZUX)
tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2));
TCG_REG_TMP1, TCG_REG_TMP2));
} else {
tcg_out32(s, ADD | TAB(TCG_REG_TMP1,
TCG_REG_TMP1, TCG_REG_TMP2));
tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2,
TCG_REG_TMP1, cmp_off);
}
} else if (cmp_off == 0 && !HOST_BIG_ENDIAN) {
tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2,
TCG_REG_TMP1, TCG_REG_TMP2));
} else { } else {
tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off);
cmp_off + 4 * HOST_BIG_ENDIAN);
} }
/* /*