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target/riscv/csr.c: fix deadcode in rmw_xireg()

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Coverity found a DEADCODE issue in rmw_xireg() claiming that we can't
reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label:

done:
    if (ret) {
        return (env->virt_enabled && virt) ?
               RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
    }
    return RISCV_EXCP_NONE;

This happens because the 'virt' flag, which is only used by 'done', is
set to 'false' and it will always remain 'false' in any condition where
we'll jump to 'done':

    switch (csrno) {
    (...)
    case CSR_VSIREG:
        isel = env->vsiselect;
        virt = true;
        break;
    default:
        goto done;
    };

'virt = true' will never reach 'done' because we have a if/else-if/else
block right before the label that will always return:

    if (xiselect_aia_range(isel)) {
        return ...
    } else if (...) {
        return ...
    } else {
        return RISCV_EXCP_ILLEGAL_INST;
    }

All this means that we can preserve the current logic by reducing the
'done' label to:

done:
    if (ret) {
        return RISCV_EXCP_ILLEGAL_INST;
    }
    return RISCV_EXCP_NONE;

The flag 'virt' is now unused. Remove it.

Fix the 'goto done' identation while we're at it.

Resolves: Coverity CID 1590359
Fixes: dc0280723d ("target/riscv: Decouple AIA processing from xiselect and xireg")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250121184847.2109128-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2025-01-21 15:48:43 -03:00 committed by Alistair Francis
parent 661c2e1ab2
commit bf031e257d
1 changed files with 2 additions and 5 deletions
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5
target/riscv/csr.c
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@ -2658,7 +2658,6 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
target_ulong *val, target_ulong new_val, target_ulong *val, target_ulong new_val,
target_ulong wr_mask) target_ulong wr_mask)
{ {
bool virt = false;
int ret = -EINVAL; int ret = -EINVAL;
target_ulong isel; target_ulong isel;
@ -2680,7 +2679,6 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
break; break;
case CSR_VSIREG: case CSR_VSIREG:
isel = env->vsiselect; isel = env->vsiselect;
virt = true;
break; break;
default: default:
goto done; goto done;
@ -2705,8 +2703,7 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
done: done:
if (ret) { if (ret) {
return (env->virt_enabled && virt) ? return RISCV_EXCP_ILLEGAL_INST;
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
} }
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }