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target/riscv: machine: Add Control Transfer Record state description

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Add a subsection to machine.c to migrate CTR CSR state

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250205-b4-ctr_upstream_v6-v6-6-439d8e06c8ef@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Rajnesh Kanwal 2025-02-05 11:18:50 +00:00 committed by Alistair Francis
parent 9e69e760fd
commit bda6522e3f
1 changed files with 25 additions and 0 deletions
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25
target/riscv/machine.c
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@ -300,6 +300,30 @@ static const VMStateDescription vmstate_envcfg = {
} }
}; };
static bool ctr_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
return cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr;
}
static const VMStateDescription vmstate_ctr = {
.name = "cpu/ctr",
.version_id = 1,
.minimum_version_id = 1,
.needed = ctr_needed,
.fields = (const VMStateField[]) {
VMSTATE_UINT64(env.mctrctl, RISCVCPU),
VMSTATE_UINT32(env.sctrdepth, RISCVCPU),
VMSTATE_UINT32(env.sctrstatus, RISCVCPU),
VMSTATE_UINT64(env.vsctrctl, RISCVCPU),
VMSTATE_UINT64_ARRAY(env.ctr_src, RISCVCPU, 16 << SCTRDEPTH_MAX),
VMSTATE_UINT64_ARRAY(env.ctr_dst, RISCVCPU, 16 << SCTRDEPTH_MAX),
VMSTATE_UINT64_ARRAY(env.ctr_data, RISCVCPU, 16 << SCTRDEPTH_MAX),
VMSTATE_END_OF_LIST()
}
};
static bool pmu_needed(void *opaque) static bool pmu_needed(void *opaque)
{ {
RISCVCPU *cpu = opaque; RISCVCPU *cpu = opaque;
@ -450,6 +474,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_jvt, &vmstate_jvt,
&vmstate_elp, &vmstate_elp,
&vmstate_ssp, &vmstate_ssp,
&vmstate_ctr,
NULL NULL
} }
}; };