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hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS

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According to ACPI spec 6.5 5.2.28.4 System Locality Latency and Bandwidth
Information Structure, if the "Entry Base Unit" is 1024 for BW and the
matrix entry has the value of 100, the BW is 100 GB/s. So the
entry_base_unit should be changed from 1000 to 1024 given the comment notes
it's 16GB/s for .latency_bandwidth.

Fixes: 882877fc359d ("hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE")
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Dave Jiang 2023-09-04 14:28:04 +01:00 committed by Michael Tokarev
parent 7b165fa164
commit bc63c99ef8
1 changed files with 1 additions and 1 deletions
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hw/pci-bridge/cxl_upstream.c
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@ -262,7 +262,7 @@ static int build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
.length = sslbis_size, .length = sslbis_size,
}, },
.data_type = HMATLB_DATA_TYPE_ACCESS_BANDWIDTH, .data_type = HMATLB_DATA_TYPE_ACCESS_BANDWIDTH,
.entry_base_unit = 1000, .entry_base_unit = 1024,
}, },
}; };