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target/ppc: powerpc_excp: Move lpes code to where it is used

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Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20210601214649.785647-2-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Fabiano Rosas 2021-06-01 18:46:45 -03:00 committed by David Gibson
parent fe43ba9721
commit bbc443cf65
1 changed files with 25 additions and 22 deletions
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47
target/ppc/excp_helper.c
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@ -333,7 +333,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
CPUPPCState *env = &cpu->env; CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector; target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1, lev = -1; int srr0, srr1, asrr0, asrr1, lev = -1;
bool lpes0;
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
" => %08x (%02x)\n", env->nip, excp, env->error_code); " => %08x (%02x)\n", env->nip, excp, env->error_code);
@ -365,27 +364,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
excp = powerpc_reset_wakeup(cs, env, excp, &msr); excp = powerpc_reset_wakeup(cs, env, excp, &msr);
} }
/*
* Exception targeting modifiers
*
* LPES0 is supported on POWER7/8/9
* LPES1 is not supported (old iSeries mode)
*
* On anything else, we behave as if LPES0 is 1
* (externals don't alter MSR:HV)
*/
#if defined(TARGET_PPC64)
if (excp_model == POWERPC_EXCP_POWER7 ||
excp_model == POWERPC_EXCP_POWER8 ||
excp_model == POWERPC_EXCP_POWER9 ||
excp_model == POWERPC_EXCP_POWER10) {
lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
} else
#endif /* defined(TARGET_PPC64) */
{
lpes0 = true;
}
/* /*
* Hypervisor emulation assistance interrupt only exists on server * Hypervisor emulation assistance interrupt only exists on server
* arch 2.05 server or later. We also don't want to generate it if * arch 2.05 server or later. We also don't want to generate it if
@ -473,8 +451,32 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
msr |= env->error_code; msr |= env->error_code;
break; break;
case POWERPC_EXCP_EXTERNAL: /* External input */ case POWERPC_EXCP_EXTERNAL: /* External input */
{
bool lpes0;
cs = CPU(cpu); cs = CPU(cpu);
/*
* Exception targeting modifiers
*
* LPES0 is supported on POWER7/8/9
* LPES1 is not supported (old iSeries mode)
*
* On anything else, we behave as if LPES0 is 1
* (externals don't alter MSR:HV)
*/
#if defined(TARGET_PPC64)
if (excp_model == POWERPC_EXCP_POWER7 ||
excp_model == POWERPC_EXCP_POWER8 ||
excp_model == POWERPC_EXCP_POWER9 ||
excp_model == POWERPC_EXCP_POWER10) {
lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
} else
#endif /* defined(TARGET_PPC64) */
{
lpes0 = true;
}
if (!lpes0) { if (!lpes0) {
new_msr |= (target_ulong)MSR_HVB; new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI); new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
@ -486,6 +488,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
} }
break; break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */ case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */ /* Get rS/rD and rA from faulting opcode */
/* /*