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target/arm: Implement FPCR.AH semantics for FMAXV and FMINV

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Implement the FPCR.AH semantics for FMAXV and FMINV.  These are the
"recursively reduce all lanes of a vector to a scalar result" insns;
we just need to use the _ah_ helper for the reduction step when
FPCR.AH == 1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell 2025-02-01 16:39:29 +00:00
parent d613e44010
commit bb9330b662
1 changed files with 18 additions and 10 deletions
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28
target/arm/tcg/translate-a64.c
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@ -7018,27 +7018,35 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int rn, MemOp esz,
} }
static bool do_fp_reduction(DisasContext *s, arg_qrr_e *a, static bool do_fp_reduction(DisasContext *s, arg_qrr_e *a,
NeonGenTwoSingleOpFn *fn) NeonGenTwoSingleOpFn *fnormal,
NeonGenTwoSingleOpFn *fah)
{ {
if (fp_access_check(s)) { if (fp_access_check(s)) {
MemOp esz = a->esz; MemOp esz = a->esz;
int elts = (a->q ? 16 : 8) >> esz; int elts = (a->q ? 16 : 8) >> esz;
TCGv_ptr fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64); TCGv_ptr fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);
TCGv_i32 res = do_reduction_op(s, a->rn, esz, 0, elts, fpst, fn); TCGv_i32 res = do_reduction_op(s, a->rn, esz, 0, elts, fpst,
s->fpcr_ah ? fah : fnormal);
write_fp_sreg(s, a->rd, res); write_fp_sreg(s, a->rd, res);
} }
return true; return true;
} }
TRANS_FEAT(FMAXNMV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_maxnumh) TRANS_FEAT(FMAXNMV_h, aa64_fp16, do_fp_reduction, a,
TRANS_FEAT(FMINNMV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_minnumh) gen_helper_vfp_maxnumh, gen_helper_vfp_maxnumh)
TRANS_FEAT(FMAXV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_maxh) TRANS_FEAT(FMINNMV_h, aa64_fp16, do_fp_reduction, a,
TRANS_FEAT(FMINV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_minh) gen_helper_vfp_minnumh, gen_helper_vfp_minnumh)
TRANS_FEAT(FMAXV_h, aa64_fp16, do_fp_reduction, a,
gen_helper_vfp_maxh, gen_helper_vfp_ah_maxh)
TRANS_FEAT(FMINV_h, aa64_fp16, do_fp_reduction, a,
gen_helper_vfp_minh, gen_helper_vfp_ah_minh)
TRANS(FMAXNMV_s, do_fp_reduction, a, gen_helper_vfp_maxnums) TRANS(FMAXNMV_s, do_fp_reduction, a,
TRANS(FMINNMV_s, do_fp_reduction, a, gen_helper_vfp_minnums) gen_helper_vfp_maxnums, gen_helper_vfp_maxnums)
TRANS(FMAXV_s, do_fp_reduction, a, gen_helper_vfp_maxs) TRANS(FMINNMV_s, do_fp_reduction, a,
TRANS(FMINV_s, do_fp_reduction, a, gen_helper_vfp_mins) gen_helper_vfp_minnums, gen_helper_vfp_minnums)
TRANS(FMAXV_s, do_fp_reduction, a, gen_helper_vfp_maxs, gen_helper_vfp_ah_maxs)
TRANS(FMINV_s, do_fp_reduction, a, gen_helper_vfp_mins, gen_helper_vfp_ah_mins)
/* /*
* Floating-point Immediate * Floating-point Immediate