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tcg/tci: Split out tci_args_ri and tci_args_rI

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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-01-29 21:49:24 -10:00
parent 5a0adf3490
commit b95aa12ed2
1 changed files with 22 additions and 16 deletions
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38
tcg/tci.c
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@ -121,16 +121,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr)
return value; return value;
} }
#if TCG_TARGET_REG_BITS == 64
/* Read constant (64 bit) from bytecode. */
static uint64_t tci_read_i64(const uint8_t **tb_ptr)
{
uint64_t value = *(const uint64_t *)(*tb_ptr);
*tb_ptr += sizeof(value);
return value;
}
#endif
/* Read indexed register (native size) from bytecode. */ /* Read indexed register (native size) from bytecode. */
static tcg_target_ulong static tcg_target_ulong
tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
@ -181,6 +171,8 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* where arguments is a sequence of * where arguments is a sequence of
* *
* c = condition (TCGCond) * c = condition (TCGCond)
* i = immediate (uint32_t)
* I = immediate (tcg_target_ulong)
* l = label or pointer * l = label or pointer
* r = register * r = register
* s = signed ldst offset * s = signed ldst offset
@ -198,6 +190,22 @@ static void tci_args_rr(const uint8_t **tb_ptr,
*r1 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr);
} }
static void tci_args_ri(const uint8_t **tb_ptr,
TCGReg *r0, tcg_target_ulong *i1)
{
*r0 = tci_read_r(tb_ptr);
*i1 = tci_read_i32(tb_ptr);
}
#if TCG_TARGET_REG_BITS == 64
static void tci_args_rI(const uint8_t **tb_ptr,
TCGReg *r0, tcg_target_ulong *i1)
{
*r0 = tci_read_r(tb_ptr);
*i1 = tci_read_i(tb_ptr);
}
#endif
static void tci_args_rrr(const uint8_t **tb_ptr, static void tci_args_rrr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2) TCGReg *r0, TCGReg *r1, TCGReg *r2)
{ {
@ -483,9 +491,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
regs[r0] = regs[r1]; regs[r0] = regs[r1];
break; break;
case INDEX_op_tci_movi_i32: case INDEX_op_tci_movi_i32:
t0 = *tb_ptr++; tci_args_ri(&tb_ptr, &r0, &t1);
t1 = tci_read_i32(&tb_ptr); regs[r0] = t1;
tci_write_reg(regs, t0, t1);
break; break;
/* Load/store operations (32 bit). */ /* Load/store operations (32 bit). */
@ -705,9 +712,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif #endif
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
case INDEX_op_tci_movi_i64: case INDEX_op_tci_movi_i64:
t0 = *tb_ptr++; tci_args_rI(&tb_ptr, &r0, &t1);
t1 = tci_read_i64(&tb_ptr); regs[r0] = t1;
tci_write_reg(regs, t0, t1);
break; break;
/* Load/store operations (64 bit). */ /* Load/store operations (64 bit). */