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target/riscv: Add select value range check for counter delegation

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This adds checks in ops performed on xireg and xireg2-xireg6 so that the
counter delegation function will receive a valid xiselect value with the
proper extensions enabled.

Co-developed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-7-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Kaiwen Xue 2025-01-10 00:21:35 -08:00 committed by Alistair Francis
parent e84af93560
commit b6504cd0d1
1 changed files with 35 additions and 1 deletions
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36
target/riscv/csr.c
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@ -2159,6 +2159,11 @@ static bool xiselect_aia_range(target_ulong isel)
(ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST); (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST);
} }
static bool xiselect_cd_range(target_ulong isel)
{
return (ISELECT_CD_FIRST <= isel && isel <= ISELECT_CD_LAST);
}
static int rmw_iprio(target_ulong xlen, static int rmw_iprio(target_ulong xlen,
target_ulong iselect, uint8_t *iprio, target_ulong iselect, uint8_t *iprio,
target_ulong *val, target_ulong new_val, target_ulong *val, target_ulong new_val,
@ -2284,6 +2289,17 @@ done:
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
static int rmw_xireg_cd(CPURISCVState *env, int csrno,
target_ulong isel, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
if (!riscv_cpu_cfg(env)->ext_smcdeleg) {
return RISCV_EXCP_ILLEGAL_INST;
}
/* TODO: Implement the functionality later */
return RISCV_EXCP_NONE;
}
/* /*
* rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6 * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6
* *
@ -2295,7 +2311,25 @@ static int rmw_xireg_csrind(CPURISCVState *env, int csrno,
target_ulong isel, target_ulong *val, target_ulong isel, target_ulong *val,
target_ulong new_val, target_ulong wr_mask) target_ulong new_val, target_ulong wr_mask)
{ {
return -EINVAL; int ret = -EINVAL;
bool virt = csrno == CSR_VSIREG ? true : false;
if (xiselect_cd_range(isel)) {
ret = rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask);
} else {
/*
* As per the specification, access to unimplented region is undefined
* but recommendation is to raise illegal instruction exception.
*/
return RISCV_EXCP_ILLEGAL_INST;
}
if (ret) {
return (env->virt_enabled && virt) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_NONE;
} }
static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val, static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val,