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target/arm: Remove gen_exception_internal_insn pc argument

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In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Since we always pass dc->pc_curr, fold the arithmetic to zero displacement.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-10-20 13:06:37 +10:00 committed by Peter Maydell
parent 55086e628f
commit b4f8d987f6
2 changed files with 8 additions and 8 deletions
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6
target/arm/translate-a64.c
View File

@ -332,9 +332,9 @@ static void gen_exception_internal(int excp)
gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
} }
static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) static void gen_exception_internal_insn(DisasContext *s, int excp)
{ {
gen_a64_update_pc(s, pc - s->pc_curr); gen_a64_update_pc(s, 0);
gen_exception_internal(excp); gen_exception_internal(excp);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
@ -2211,7 +2211,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
* Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
*/ */
if (semihosting_enabled(s->current_el == 0) && imm16 == 0xf000) { if (semihosting_enabled(s->current_el == 0) && imm16 == 0xf000) {
gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); gen_exception_internal_insn(s, EXCP_SEMIHOST);
} else { } else {
unallocated_encoding(s); unallocated_encoding(s);
} }

10
target/arm/translate.c
View File

@ -1074,10 +1074,10 @@ static inline void gen_smc(DisasContext *s)
s->base.is_jmp = DISAS_SMC; s->base.is_jmp = DISAS_SMC;
} }
static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) static void gen_exception_internal_insn(DisasContext *s, int excp)
{ {
gen_set_condexec(s); gen_set_condexec(s);
gen_update_pc(s, pc - s->pc_curr); gen_update_pc(s, 0);
gen_exception_internal(excp); gen_exception_internal(excp);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
@ -1169,7 +1169,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
*/ */
if (semihosting_enabled(s->current_el != 0) && if (semihosting_enabled(s->current_el != 0) &&
(imm == (s->thumb ? 0x3c : 0xf000))) { (imm == (s->thumb ? 0x3c : 0xf000))) {
gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); gen_exception_internal_insn(s, EXCP_SEMIHOST);
return; return;
} }
@ -6556,7 +6556,7 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a)
if (arm_dc_feature(s, ARM_FEATURE_M) && if (arm_dc_feature(s, ARM_FEATURE_M) &&
semihosting_enabled(s->current_el == 0) && semihosting_enabled(s->current_el == 0) &&
(a->imm == 0xab)) { (a->imm == 0xab)) {
gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); gen_exception_internal_insn(s, EXCP_SEMIHOST);
} else { } else {
gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
} }
@ -8762,7 +8762,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
if (!arm_dc_feature(s, ARM_FEATURE_M) && if (!arm_dc_feature(s, ARM_FEATURE_M) &&
semihosting_enabled(s->current_el == 0) && semihosting_enabled(s->current_el == 0) &&
(a->imm == semihost_imm)) { (a->imm == semihost_imm)) {
gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); gen_exception_internal_insn(s, EXCP_SEMIHOST);
} else { } else {
gen_update_pc(s, curr_insn_len(s)); gen_update_pc(s, curr_insn_len(s));
s->svc_imm = a->imm; s->svc_imm = a->imm;