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target/arm: Convert PACGA to decodetree

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Remove disas_data_proc_2src, as this was the last insn
decoded by that function.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:29:33 -06:00 committed by Peter Maydell
parent 9be60681c2
commit b466ea8f21
2 changed files with 13 additions and 54 deletions
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2
target/arm/tcg/a64.decode
View File

@ -682,6 +682,8 @@ SUBPS 1 01 11010110 ..... 000000 ..... ..... @rrr
IRG 1 00 11010110 ..... 000100 ..... ..... @rrr IRG 1 00 11010110 ..... 000100 ..... ..... @rrr
GMI 1 00 11010110 ..... 000101 ..... ..... @rrr GMI 1 00 11010110 ..... 000101 ..... ..... @rrr
PACGA 1 00 11010110 ..... 001100 ..... ..... @rrr
# Data Processing (1-source) # Data Processing (1-source)
# Logical (shifted reg) # Logical (shifted reg)
# Add/subtract (shifted reg) # Add/subtract (shifted reg)

65
target/arm/tcg/translate-a64.c
View File

@ -7674,6 +7674,16 @@ static bool trans_GMI(DisasContext *s, arg_rrr *a)
return false; return false;
} }
static bool trans_PACGA(DisasContext *s, arg_rrr *a)
{
if (dc_isar_feature(aa64_pauth, s)) {
gen_helper_pacga(cpu_reg(s, a->rd), tcg_env,
cpu_reg(s, a->rn), cpu_reg_sp(s, a->rm));
return true;
}
return false;
}
/* Logical (shifted register) /* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+ * +----+-----+-----------+-------+---+------+--------+------+------+
@ -8555,59 +8565,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
} }
/* Data-processing (2 source)
* 31 30 29 28 21 20 16 15 10 9 5 4 0
* +----+---+---+-----------------+------+--------+------+------+
* | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
* +----+---+---+-----------------+------+--------+------+------+
*/
static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
{
unsigned int sf, rm, opcode, rn, rd, setflag;
sf = extract32(insn, 31, 1);
setflag = extract32(insn, 29, 1);
rm = extract32(insn, 16, 5);
opcode = extract32(insn, 10, 6);
rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5);
if (setflag && opcode != 0) {
unallocated_encoding(s);
return;
}
switch (opcode) {
case 12: /* PACGA */
if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
}
gen_helper_pacga(cpu_reg(s, rd), tcg_env,
cpu_reg(s, rn), cpu_reg_sp(s, rm));
break;
default:
do_unallocated:
case 0: /* SUBP(S) */
case 2: /* UDIV */
case 3: /* SDIV */
case 4: /* IRG */
case 5: /* GMI */
case 8: /* LSLV */
case 9: /* LSRV */
case 10: /* ASRV */
case 11: /* RORV */
case 16:
case 17:
case 18:
case 19:
case 20:
case 21:
case 22:
case 23: /* CRC32 */
unallocated_encoding(s);
break;
}
}
/* /*
* Data processing - register * Data processing - register
* 31 30 29 28 25 21 20 16 10 0 * 31 30 29 28 25 21 20 16 10 0
@ -8674,7 +8631,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
if (op0) { /* (1 source) */ if (op0) { /* (1 source) */
disas_data_proc_1src(s, insn); disas_data_proc_1src(s, insn);
} else { /* (2 source) */ } else { /* (2 source) */
disas_data_proc_2src(s, insn); goto do_unallocated;
} }
break; break;
case 0x8 ... 0xf: /* (3 source) */ case 0x8 ... 0xf: /* (3 source) */