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tcg/riscv: Fix StoreStore barrier generation

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On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`

Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Roman Artemev 2024-12-11 07:40:04 +00:00 committed by Richard Henderson
parent 04e006ab36
commit b438362a14
1 changed files with 1 additions and 1 deletions
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2
tcg/riscv/tcg-target.c.inc
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@ -1624,7 +1624,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
insn |= 0x02100000;
}
if (a0 & TCG_MO_ST_ST) {
insn |= 0x02200000;
insn |= 0x01100000;
}
tcg_out32(s, insn);
}