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target/ppc: Add ISA v3.1 variants of sync instruction

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POWER10 adds a new field to sync for store-store syncs, and some
new variants of the existing syncs that include persistent memory.

Implement the store-store syncs and plwsync/phwsync.

Reviewed-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-05-01 23:04:34 +10:00
parent ab4f174bae
commit b3cfa2dd2b
2 changed files with 32 additions and 15 deletions
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6
target/ppc/insn32.decode
View File

@ -1001,7 +1001,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 -
# Memory Barrier Instructions # Memory Barrier Instructions
&X_sync l &X_sync l sc
@X_sync ...... ... l:2 ..... ..... .......... . &X_sync @X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync
SYNC 011111 --- .. ----- ----- 1001010110 - @X_sync SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync
EIEIO 011111 ----- ----- ----- 1101010110 - EIEIO 011111 ----- ----- ----- 1101010110 -

41
target/ppc/translate/misc-impl.c.inc
View File

@ -25,6 +25,7 @@ static bool trans_SYNC(DisasContext *ctx, arg_X_sync *a)
{ {
TCGBar bar = TCG_MO_ALL; TCGBar bar = TCG_MO_ALL;
uint32_t l = a->l; uint32_t l = a->l;
uint32_t sc = a->sc;
/* /*
* BookE uses the msync mnemonic. This means hwsync, except in the * BookE uses the msync mnemonic. This means hwsync, except in the
@ -41,20 +42,36 @@ static bool trans_SYNC(DisasContext *ctx, arg_X_sync *a)
return false; return false;
} }
if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { /*
bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; * In ISA v3.1, the L field grew one bit. Mask that out to ignore it in
* older processors. It also added the SC field, zero this to ignore
* it too.
*/
if (!(ctx->insns_flags2 & PPC2_ISA310)) {
l &= 0x3;
sc = 0;
} }
/* if (sc) {
* We may need to check for a pending TLB flush. /* Store syncs [stsync, stcisync, stncisync]. These ignore L. */
* bar = TCG_MO_ST_ST;
* We do this on ptesync (l == 2) on ppc64 and any sync on ppc32. } else {
* if (((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) || (l == 5)) {
* Additionally, this can only happen in kernel mode however so /* lwsync, or plwsync on POWER10 and later */
* check MSR_PR as well. bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
*/ }
if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
gen_check_tlb_flush(ctx, true); /*
* We may need to check for a pending TLB flush.
*
* We do this on ptesync (l == 2) on ppc64 and any sync on ppc32.
*
* Additionally, this can only happen in kernel mode however so
* check MSR_PR as well.
*/
if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
gen_check_tlb_flush(ctx, true);
}
} }
tcg_gen_mb(bar | TCG_BAR_SC); tcg_gen_mb(bar | TCG_BAR_SC);