target-arm: A64: add support for add, addi, sub, subi
Implement the non-carry forms of addition and subtraction (immediate, extended register and shifted register). This includes the code to calculate NZCV if the instruction calls for setting the flags. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Alex Bennée
Peter Maydell
parent
a5e94a9d76
commit
b0ff21b4f9
@ -297,6 +297,102 @@ static inline void gen_logic_CC(int sf, TCGv_i64 result)
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tcg_gen_movi_i32(cpu_VF, 0);
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}
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/* dest = T0 + T1; compute C, N, V and Z flags */
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static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
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{
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if (sf) {
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TCGv_i64 result, flag, tmp;
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result = tcg_temp_new_i64();
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flag = tcg_temp_new_i64();
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tmp = tcg_temp_new_i64();
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tcg_gen_movi_i64(tmp, 0);
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tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp);
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tcg_gen_trunc_i64_i32(cpu_CF, flag);
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gen_set_NZ64(result);
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tcg_gen_xor_i64(flag, result, t0);
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tcg_gen_xor_i64(tmp, t0, t1);
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tcg_gen_andc_i64(flag, flag, tmp);
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tcg_temp_free_i64(tmp);
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tcg_gen_shri_i64(flag, flag, 32);
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tcg_gen_trunc_i64_i32(cpu_VF, flag);
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tcg_gen_mov_i64(dest, result);
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tcg_temp_free_i64(result);
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tcg_temp_free_i64(flag);
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} else {
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/* 32 bit arithmetic */
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TCGv_i32 t0_32 = tcg_temp_new_i32();
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TCGv_i32 t1_32 = tcg_temp_new_i32();
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_movi_i32(tmp, 0);
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tcg_gen_trunc_i64_i32(t0_32, t0);
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tcg_gen_trunc_i64_i32(t1_32, t1);
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tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp);
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tcg_gen_mov_i32(cpu_ZF, cpu_NF);
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tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
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tcg_gen_xor_i32(tmp, t0_32, t1_32);
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tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
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tcg_gen_extu_i32_i64(dest, cpu_NF);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(t0_32);
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tcg_temp_free_i32(t1_32);
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}
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}
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/* dest = T0 - T1; compute C, N, V and Z flags */
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static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
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{
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if (sf) {
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/* 64 bit arithmetic */
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TCGv_i64 result, flag, tmp;
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result = tcg_temp_new_i64();
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flag = tcg_temp_new_i64();
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tcg_gen_sub_i64(result, t0, t1);
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gen_set_NZ64(result);
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tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1);
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tcg_gen_trunc_i64_i32(cpu_CF, flag);
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tcg_gen_xor_i64(flag, result, t0);
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tmp = tcg_temp_new_i64();
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tcg_gen_xor_i64(tmp, t0, t1);
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tcg_gen_and_i64(flag, flag, tmp);
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tcg_temp_free_i64(tmp);
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tcg_gen_shri_i64(flag, flag, 32);
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tcg_gen_trunc_i64_i32(cpu_VF, flag);
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tcg_gen_mov_i64(dest, result);
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tcg_temp_free_i64(flag);
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tcg_temp_free_i64(result);
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} else {
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/* 32 bit arithmetic */
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TCGv_i32 t0_32 = tcg_temp_new_i32();
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TCGv_i32 t1_32 = tcg_temp_new_i32();
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TCGv_i32 tmp;
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tcg_gen_trunc_i64_i32(t0_32, t0);
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tcg_gen_trunc_i64_i32(t1_32, t1);
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tcg_gen_sub_i32(cpu_NF, t0_32, t1_32);
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tcg_gen_mov_i32(cpu_ZF, cpu_NF);
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tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32);
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tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
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tmp = tcg_temp_new_i32();
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tcg_gen_xor_i32(tmp, t0_32, t1_32);
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tcg_temp_free_i32(t0_32);
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tcg_temp_free_i32(t1_32);
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tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
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tcg_temp_free_i32(tmp);
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tcg_gen_extu_i32_i64(dest, cpu_NF);
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}
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}
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/*
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* Load/Store generators
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*/
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@ -1328,10 +1424,68 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
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tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
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}
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/* Add/subtract (immediate) */
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/*
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* C3.4.1 Add/subtract (immediate)
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*
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* 31 30 29 28 24 23 22 21 10 9 5 4 0
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* +--+--+--+-----------+-----+-------------+-----+-----+
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* |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
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* +--+--+--+-----------+-----+-------------+-----+-----+
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*
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* sf: 0 -> 32bit, 1 -> 64bit
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* op: 0 -> add , 1 -> sub
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* S: 1 -> set flags
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* shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
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*/
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static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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uint64_t imm = extract32(insn, 10, 12);
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int shift = extract32(insn, 22, 2);
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bool setflags = extract32(insn, 29, 1);
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bool sub_op = extract32(insn, 30, 1);
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bool is_64bit = extract32(insn, 31, 1);
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TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
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TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
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TCGv_i64 tcg_result;
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switch (shift) {
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case 0x0:
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break;
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case 0x1:
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imm <<= 12;
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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tcg_result = tcg_temp_new_i64();
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if (!setflags) {
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if (sub_op) {
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tcg_gen_subi_i64(tcg_result, tcg_rn, imm);
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} else {
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tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
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}
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} else {
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TCGv_i64 tcg_imm = tcg_const_i64(imm);
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if (sub_op) {
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gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
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} else {
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gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
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}
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tcg_temp_free_i64(tcg_imm);
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}
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if (is_64bit) {
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tcg_gen_mov_i64(tcg_rd, tcg_result);
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} else {
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tcg_gen_ext32u_i64(tcg_rd, tcg_result);
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}
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tcg_temp_free_i64(tcg_result);
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}
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/* The input should be a value in the bottom e bits (with higher
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@ -1789,16 +1943,142 @@ static void disas_logic_reg(DisasContext *s, uint32_t insn)
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}
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}
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/* Add/subtract (extended register) */
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/*
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* C3.5.1 Add/subtract (extended register)
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*
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* 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
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* +--+--+--+-----------+-----+--+-------+------+------+----+----+
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* |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
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* +--+--+--+-----------+-----+--+-------+------+------+----+----+
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*
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* sf: 0 -> 32bit, 1 -> 64bit
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* op: 0 -> add , 1 -> sub
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* S: 1 -> set flags
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* opt: 00
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* option: extension type (see DecodeRegExtend)
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* imm3: optional shift to Rm
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*
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* Rd = Rn + LSL(extend(Rm), amount)
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*/
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static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int imm3 = extract32(insn, 10, 3);
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int option = extract32(insn, 13, 3);
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int rm = extract32(insn, 16, 5);
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bool setflags = extract32(insn, 29, 1);
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bool sub_op = extract32(insn, 30, 1);
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bool sf = extract32(insn, 31, 1);
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TCGv_i64 tcg_rm, tcg_rn; /* temps */
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TCGv_i64 tcg_rd;
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TCGv_i64 tcg_result;
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if (imm3 > 4) {
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unallocated_encoding(s);
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return;
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}
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/* non-flag setting ops may use SP */
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if (!setflags) {
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tcg_rn = read_cpu_reg_sp(s, rn, sf);
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tcg_rd = cpu_reg_sp(s, rd);
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} else {
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tcg_rn = read_cpu_reg(s, rn, sf);
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tcg_rd = cpu_reg(s, rd);
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}
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tcg_rm = read_cpu_reg(s, rm, sf);
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ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
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tcg_result = tcg_temp_new_i64();
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if (!setflags) {
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if (sub_op) {
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tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
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} else {
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tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
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}
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} else {
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if (sub_op) {
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gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
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} else {
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gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
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}
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}
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if (sf) {
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tcg_gen_mov_i64(tcg_rd, tcg_result);
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} else {
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tcg_gen_ext32u_i64(tcg_rd, tcg_result);
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}
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tcg_temp_free_i64(tcg_result);
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}
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/* Add/subtract (shifted register) */
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/*
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* C3.5.2 Add/subtract (shifted register)
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*
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* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
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* +--+--+--+-----------+-----+--+-------+---------+------+------+
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* |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
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* +--+--+--+-----------+-----+--+-------+---------+------+------+
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*
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* sf: 0 -> 32bit, 1 -> 64bit
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* op: 0 -> add , 1 -> sub
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* S: 1 -> set flags
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* shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
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* imm6: Shift amount to apply to Rm before the add/sub
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*/
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static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int imm6 = extract32(insn, 10, 6);
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int rm = extract32(insn, 16, 5);
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int shift_type = extract32(insn, 22, 2);
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bool setflags = extract32(insn, 29, 1);
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bool sub_op = extract32(insn, 30, 1);
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bool sf = extract32(insn, 31, 1);
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TCGv_i64 tcg_rd = cpu_reg(s, rd);
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TCGv_i64 tcg_rn, tcg_rm;
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TCGv_i64 tcg_result;
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if ((shift_type == 3) || (!sf && (imm6 > 31))) {
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unallocated_encoding(s);
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return;
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}
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tcg_rn = read_cpu_reg(s, rn, sf);
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tcg_rm = read_cpu_reg(s, rm, sf);
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shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6);
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tcg_result = tcg_temp_new_i64();
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if (!setflags) {
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if (sub_op) {
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tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
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} else {
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tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
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}
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} else {
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if (sub_op) {
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gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
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} else {
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gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
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}
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}
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if (sf) {
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tcg_gen_mov_i64(tcg_rd, tcg_result);
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} else {
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tcg_gen_ext32u_i64(tcg_rd, tcg_result);
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}
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tcg_temp_free_i64(tcg_result);
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}
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/* Data-processing (3 source) */
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