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target/riscv/cpu.c: add riscv_bare_cpu_init()

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Next patch will add more bare CPUs. Their cpu_init() functions would be
glorified copy/pastes of rv64i_bare_cpu_init(), differing only by a
riscv_cpu_set_misa() call.

Add a new .instance_init for the TYPE_RISCV_BARE_CPU typ to avoid this
code repetition. While we're at it, add a better explanation on why
we're disabling the timing extensions for bare CPUs.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122123348.973288-2-dbarboza@ventanamicro.com>
[ Changes by AF:
 - Rebase on latest changes
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2024-01-22 09:33:47 -03:00 committed by Alistair Francis
parent a65d51707d
commit b077aec9c9
1 changed files with 29 additions and 16 deletions
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45
target/riscv/cpu.c
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@ -605,22 +605,6 @@ static void rv64i_bare_cpu_init(Object *obj)
{ {
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
riscv_cpu_set_misa_ext(env, RVI); riscv_cpu_set_misa_ext(env, RVI);
/* Remove the defaults from the parent class */
RISCV_CPU(obj)->cfg.ext_zicntr = false;
RISCV_CPU(obj)->cfg.ext_zihpm = false;
/* Set to QEMU's first supported priv version */
env->priv_ver = PRIV_VERSION_1_10_0;
/*
* Support all available satp_mode settings. The default
* value will be set to MBARE if the user doesn't set
* satp_mode manually (see set_satp_mode_default()).
*/
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64);
#endif
} }
#else #else
static void rv32_base_cpu_init(Object *obj) static void rv32_base_cpu_init(Object *obj)
@ -1329,6 +1313,34 @@ static void riscv_cpu_init(Object *obj)
cpu->env.vext_ver = VEXT_VERSION_1_00_0; cpu->env.vext_ver = VEXT_VERSION_1_00_0;
} }
static void riscv_bare_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
/*
* Bare CPUs do not inherit the timer and performance
* counters from the parent class (see riscv_cpu_init()
* for info on why the parent enables them).
*
* Users have to explicitly enable these counters for
* bare CPUs.
*/
cpu->cfg.ext_zicntr = false;
cpu->cfg.ext_zihpm = false;
/* Set to QEMU's first supported priv version */
cpu->env.priv_ver = PRIV_VERSION_1_10_0;
/*
* Support all available satp_mode settings. The default
* value will be set to MBARE if the user doesn't set
* satp_mode manually (see set_satp_mode_default()).
*/
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_SV64);
#endif
}
typedef struct misa_ext_info { typedef struct misa_ext_info {
const char *name; const char *name;
const char *description; const char *description;
@ -2505,6 +2517,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
{ {
.name = TYPE_RISCV_BARE_CPU, .name = TYPE_RISCV_BARE_CPU,
.parent = TYPE_RISCV_CPU, .parent = TYPE_RISCV_CPU,
.instance_init = riscv_bare_cpu_init,
.abstract = true, .abstract = true,
}, },
#if defined(TARGET_RISCV32) #if defined(TARGET_RISCV32)