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tcg: Rename cpu_env to tcg_env

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Allow the name 'cpu_env' to be used for something else.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-13 16:37:36 -07:00
parent a953b5fa15
commit ad75a51e84
91 changed files with 3818 additions and 3819 deletions
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8
accel/tcg/plugin-gen.c
View File

@ -104,7 +104,7 @@ static void gen_empty_udata_cb(void)
TCGv_ptr udata = tcg_temp_ebb_new_ptr(); TCGv_ptr udata = tcg_temp_ebb_new_ptr();
tcg_gen_movi_ptr(udata, 0); tcg_gen_movi_ptr(udata, 0);
tcg_gen_ld_i32(cpu_index, cpu_env, tcg_gen_ld_i32(cpu_index, tcg_env,
-offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)); -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
gen_helper_plugin_vcpu_udata_cb(cpu_index, udata); gen_helper_plugin_vcpu_udata_cb(cpu_index, udata);
@ -138,7 +138,7 @@ static void gen_empty_mem_cb(TCGv_i64 addr, uint32_t info)
tcg_gen_movi_i32(meminfo, info); tcg_gen_movi_i32(meminfo, info);
tcg_gen_movi_ptr(udata, 0); tcg_gen_movi_ptr(udata, 0);
tcg_gen_ld_i32(cpu_index, cpu_env, tcg_gen_ld_i32(cpu_index, tcg_env,
-offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)); -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr, udata); gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr, udata);
@ -157,7 +157,7 @@ static void gen_empty_mem_helper(void)
TCGv_ptr ptr = tcg_temp_ebb_new_ptr(); TCGv_ptr ptr = tcg_temp_ebb_new_ptr();
tcg_gen_movi_ptr(ptr, 0); tcg_gen_movi_ptr(ptr, 0);
tcg_gen_st_ptr(ptr, cpu_env, offsetof(CPUState, plugin_mem_cbs) - tcg_gen_st_ptr(ptr, tcg_env, offsetof(CPUState, plugin_mem_cbs) -
offsetof(ArchCPU, env)); offsetof(ArchCPU, env));
tcg_temp_free_ptr(ptr); tcg_temp_free_ptr(ptr);
} }
@ -581,7 +581,7 @@ void plugin_gen_disable_mem_helpers(void)
if (!tcg_ctx->plugin_tb->mem_helper) { if (!tcg_ctx->plugin_tb->mem_helper) {
return; return;
} }
tcg_gen_st_ptr(tcg_constant_ptr(NULL), cpu_env, tcg_gen_st_ptr(tcg_constant_ptr(NULL), tcg_env,
offsetof(CPUState, plugin_mem_cbs) - offsetof(ArchCPU, env)); offsetof(CPUState, plugin_mem_cbs) - offsetof(ArchCPU, env));
} }

6
accel/tcg/translator.c
View File

@ -22,7 +22,7 @@ static void set_can_do_io(DisasContextBase *db, bool val)
db->saved_can_do_io = val; db->saved_can_do_io = val;
QEMU_BUILD_BUG_ON(sizeof_field(CPUState, neg.can_do_io) != 1); QEMU_BUILD_BUG_ON(sizeof_field(CPUState, neg.can_do_io) != 1);
tcg_gen_st8_i32(tcg_constant_i32(val), cpu_env, tcg_gen_st8_i32(tcg_constant_i32(val), tcg_env,
offsetof(ArchCPU, parent_obj.neg.can_do_io) - offsetof(ArchCPU, parent_obj.neg.can_do_io) -
offsetof(ArchCPU, env)); offsetof(ArchCPU, env));
} }
@ -49,7 +49,7 @@ static TCGOp *gen_tb_start(DisasContextBase *db, uint32_t cflags)
if ((cflags & CF_USE_ICOUNT) || !(cflags & CF_NOIRQ)) { if ((cflags & CF_USE_ICOUNT) || !(cflags & CF_NOIRQ)) {
count = tcg_temp_new_i32(); count = tcg_temp_new_i32();
tcg_gen_ld_i32(count, cpu_env, tcg_gen_ld_i32(count, tcg_env,
offsetof(ArchCPU, parent_obj.neg.icount_decr.u32) offsetof(ArchCPU, parent_obj.neg.icount_decr.u32)
- offsetof(ArchCPU, env)); - offsetof(ArchCPU, env));
} }
@ -79,7 +79,7 @@ static TCGOp *gen_tb_start(DisasContextBase *db, uint32_t cflags)
} }
if (cflags & CF_USE_ICOUNT) { if (cflags & CF_USE_ICOUNT) {
tcg_gen_st16_i32(count, cpu_env, tcg_gen_st16_i32(count, tcg_env,
offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.low) offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.low)
- offsetof(ArchCPU, env)); - offsetof(ArchCPU, env));
} }

2
include/tcg/tcg.h
View File

@ -577,7 +577,7 @@ static inline bool temp_readonly(TCGTemp *ts)
extern __thread TCGContext *tcg_ctx; extern __thread TCGContext *tcg_ctx;
extern const void *tcg_code_gen_epilogue; extern const void *tcg_code_gen_epilogue;
extern uintptr_t tcg_splitwx_diff; extern uintptr_t tcg_splitwx_diff;
extern TCGv_env cpu_env; extern TCGv_env tcg_env;
bool in_code_gen_buffer(const void *p); bool in_code_gen_buffer(const void *p);

142
target/alpha/translate.c
View File

@ -131,13 +131,13 @@ void alpha_translate_init(void)
int i; int i;
for (i = 0; i < 31; i++) { for (i = 0; i < 31; i++) {
cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env, cpu_std_ir[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUAlphaState, ir[i]), offsetof(CPUAlphaState, ir[i]),
greg_names[i]); greg_names[i]);
} }
for (i = 0; i < 31; i++) { for (i = 0; i < 31; i++) {
cpu_fir[i] = tcg_global_mem_new_i64(cpu_env, cpu_fir[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUAlphaState, fir[i]), offsetof(CPUAlphaState, fir[i]),
freg_names[i]); freg_names[i]);
} }
@ -146,7 +146,7 @@ void alpha_translate_init(void)
memcpy(cpu_pal_ir, cpu_std_ir, sizeof(cpu_pal_ir)); memcpy(cpu_pal_ir, cpu_std_ir, sizeof(cpu_pal_ir));
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
int r = (i == 7 ? 25 : i + 8); int r = (i == 7 ? 25 : i + 8);
cpu_pal_ir[r] = tcg_global_mem_new_i64(cpu_env, cpu_pal_ir[r] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUAlphaState, offsetof(CPUAlphaState,
shadow[i]), shadow[i]),
shadow_names[i]); shadow_names[i]);
@ -155,7 +155,7 @@ void alpha_translate_init(void)
for (i = 0; i < ARRAY_SIZE(vars); ++i) { for (i = 0; i < ARRAY_SIZE(vars); ++i) {
const GlobalVar *v = &vars[i]; const GlobalVar *v = &vars[i];
*v->var = tcg_global_mem_new_i64(cpu_env, v->ofs, v->name); *v->var = tcg_global_mem_new_i64(tcg_env, v->ofs, v->name);
} }
} }
@ -244,12 +244,12 @@ static int get_flag_ofs(unsigned shift)
static void ld_flag_byte(TCGv val, unsigned shift) static void ld_flag_byte(TCGv val, unsigned shift)
{ {
tcg_gen_ld8u_i64(val, cpu_env, get_flag_ofs(shift)); tcg_gen_ld8u_i64(val, tcg_env, get_flag_ofs(shift));
} }
static void st_flag_byte(TCGv val, unsigned shift) static void st_flag_byte(TCGv val, unsigned shift)
{ {
tcg_gen_st8_i64(val, cpu_env, get_flag_ofs(shift)); tcg_gen_st8_i64(val, tcg_env, get_flag_ofs(shift));
} }
static void gen_excp_1(int exception, int error_code) static void gen_excp_1(int exception, int error_code)
@ -258,7 +258,7 @@ static void gen_excp_1(int exception, int error_code)
tmp1 = tcg_constant_i32(exception); tmp1 = tcg_constant_i32(exception);
tmp2 = tcg_constant_i32(error_code); tmp2 = tcg_constant_i32(error_code);
gen_helper_excp(cpu_env, tmp1, tmp2); gen_helper_excp(tcg_env, tmp1, tmp2);
} }
static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code) static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code)
@ -582,7 +582,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int fn11)
tcg_gen_movi_i32(tmp, float_round_down); tcg_gen_movi_i32(tmp, float_round_down);
break; break;
case QUAL_RM_D: case QUAL_RM_D:
tcg_gen_ld8u_i32(tmp, cpu_env, tcg_gen_ld8u_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fpcr_dyn_round)); offsetof(CPUAlphaState, fpcr_dyn_round));
break; break;
} }
@ -591,7 +591,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int fn11)
/* ??? The "fpu/softfloat.h" interface is to call set_float_rounding_mode. /* ??? The "fpu/softfloat.h" interface is to call set_float_rounding_mode.
With CONFIG_SOFTFLOAT that expands to an out-of-line call that just With CONFIG_SOFTFLOAT that expands to an out-of-line call that just
sets the one field. */ sets the one field. */
tcg_gen_st8_i32(tmp, cpu_env, tcg_gen_st8_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fp_status.float_rounding_mode)); offsetof(CPUAlphaState, fp_status.float_rounding_mode));
#else #else
gen_helper_setroundmode(tmp); gen_helper_setroundmode(tmp);
@ -611,7 +611,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int fn11)
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
if (fn11) { if (fn11) {
/* Underflow is enabled, use the FPCR setting. */ /* Underflow is enabled, use the FPCR setting. */
tcg_gen_ld8u_i32(tmp, cpu_env, tcg_gen_ld8u_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fpcr_flush_to_zero)); offsetof(CPUAlphaState, fpcr_flush_to_zero));
} else { } else {
/* Underflow is disabled, force flush-to-zero. */ /* Underflow is disabled, force flush-to-zero. */
@ -619,7 +619,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int fn11)
} }
#if defined(CONFIG_SOFTFLOAT_INLINE) #if defined(CONFIG_SOFTFLOAT_INLINE)
tcg_gen_st8_i32(tmp, cpu_env, tcg_gen_st8_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fp_status.flush_to_zero)); offsetof(CPUAlphaState, fp_status.flush_to_zero));
#else #else
gen_helper_setflushzero(tmp); gen_helper_setflushzero(tmp);
@ -636,16 +636,16 @@ static TCGv gen_ieee_input(DisasContext *ctx, int reg, int fn11, int is_cmp)
val = cpu_fir[reg]; val = cpu_fir[reg];
if ((fn11 & QUAL_S) == 0) { if ((fn11 & QUAL_S) == 0) {
if (is_cmp) { if (is_cmp) {
gen_helper_ieee_input_cmp(cpu_env, val); gen_helper_ieee_input_cmp(tcg_env, val);
} else { } else {
gen_helper_ieee_input(cpu_env, val); gen_helper_ieee_input(tcg_env, val);
} }
} else { } else {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
/* In system mode, raise exceptions for denormals like real /* In system mode, raise exceptions for denormals like real
hardware. In user mode, proceed as if the OS completion hardware. In user mode, proceed as if the OS completion
handler is handling the denormal as per spec. */ handler is handling the denormal as per spec. */
gen_helper_ieee_input_s(cpu_env, val); gen_helper_ieee_input_s(tcg_env, val);
#endif #endif
} }
} }
@ -678,9 +678,9 @@ static void gen_fp_exc_raise(int rc, int fn11)
or if we were to do something clever with imprecise exceptions. */ or if we were to do something clever with imprecise exceptions. */
reg = tcg_constant_i32(rc + 32); reg = tcg_constant_i32(rc + 32);
if (fn11 & QUAL_S) { if (fn11 & QUAL_S) {
gen_helper_fp_exc_raise_s(cpu_env, ign, reg); gen_helper_fp_exc_raise_s(tcg_env, ign, reg);
} else { } else {
gen_helper_fp_exc_raise(cpu_env, ign, reg); gen_helper_fp_exc_raise(tcg_env, ign, reg);
} }
} }
@ -705,7 +705,7 @@ static void gen_ieee_arith2(DisasContext *ctx,
gen_qual_flushzero(ctx, fn11); gen_qual_flushzero(ctx, fn11);
vb = gen_ieee_input(ctx, rb, fn11, 0); vb = gen_ieee_input(ctx, rb, fn11, 0);
helper(dest_fpr(ctx, rc), cpu_env, vb); helper(dest_fpr(ctx, rc), tcg_env, vb);
gen_fp_exc_raise(rc, fn11); gen_fp_exc_raise(rc, fn11);
} }
@ -732,10 +732,10 @@ static void gen_cvttq(DisasContext *ctx, int rb, int rc, int fn11)
/* Almost all integer conversions use cropped rounding; /* Almost all integer conversions use cropped rounding;
special case that. */ special case that. */
if ((fn11 & QUAL_RM_MASK) == QUAL_RM_C) { if ((fn11 & QUAL_RM_MASK) == QUAL_RM_C) {
gen_helper_cvttq_c(vc, cpu_env, vb); gen_helper_cvttq_c(vc, tcg_env, vb);
} else { } else {
gen_qual_roundmode(ctx, fn11); gen_qual_roundmode(ctx, fn11);
gen_helper_cvttq(vc, cpu_env, vb); gen_helper_cvttq(vc, tcg_env, vb);
} }
gen_fp_exc_raise(rc, fn11); gen_fp_exc_raise(rc, fn11);
} }
@ -754,10 +754,10 @@ static void gen_ieee_intcvt(DisasContext *ctx,
is inexact. Thus we only need to worry about exceptions when is inexact. Thus we only need to worry about exceptions when
inexact handling is requested. */ inexact handling is requested. */
if (fn11 & QUAL_I) { if (fn11 & QUAL_I) {
helper(vc, cpu_env, vb); helper(vc, tcg_env, vb);
gen_fp_exc_raise(rc, fn11); gen_fp_exc_raise(rc, fn11);
} else { } else {
helper(vc, cpu_env, vb); helper(vc, tcg_env, vb);
} }
} }
@ -797,7 +797,7 @@ static void gen_ieee_arith3(DisasContext *ctx,
va = gen_ieee_input(ctx, ra, fn11, 0); va = gen_ieee_input(ctx, ra, fn11, 0);
vb = gen_ieee_input(ctx, rb, fn11, 0); vb = gen_ieee_input(ctx, rb, fn11, 0);
vc = dest_fpr(ctx, rc); vc = dest_fpr(ctx, rc);
helper(vc, cpu_env, va, vb); helper(vc, tcg_env, va, vb);
gen_fp_exc_raise(rc, fn11); gen_fp_exc_raise(rc, fn11);
} }
@ -826,7 +826,7 @@ static void gen_ieee_compare(DisasContext *ctx,
va = gen_ieee_input(ctx, ra, fn11, 1); va = gen_ieee_input(ctx, ra, fn11, 1);
vb = gen_ieee_input(ctx, rb, fn11, 1); vb = gen_ieee_input(ctx, rb, fn11, 1);
vc = dest_fpr(ctx, rc); vc = dest_fpr(ctx, rc);
helper(vc, cpu_env, va, vb); helper(vc, tcg_env, va, vb);
gen_fp_exc_raise(rc, fn11); gen_fp_exc_raise(rc, fn11);
} }
@ -1059,12 +1059,12 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
break; break;
case 0x9E: case 0x9E:
/* RDUNIQUE */ /* RDUNIQUE */
tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env, tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,
offsetof(CPUAlphaState, unique)); offsetof(CPUAlphaState, unique));
break; break;
case 0x9F: case 0x9F:
/* WRUNIQUE */ /* WRUNIQUE */
tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env, tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, unique)); offsetof(CPUAlphaState, unique));
break; break;
default: default:
@ -1088,17 +1088,17 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
break; break;
case 0x2D: case 0x2D:
/* WRVPTPTR */ /* WRVPTPTR */
tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env, tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, vptptr)); offsetof(CPUAlphaState, vptptr));
break; break;
case 0x31: case 0x31:
/* WRVAL */ /* WRVAL */
tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env, tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, sysval)); offsetof(CPUAlphaState, sysval));
break; break;
case 0x32: case 0x32:
/* RDVAL */ /* RDVAL */
tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env, tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,
offsetof(CPUAlphaState, sysval)); offsetof(CPUAlphaState, sysval));
break; break;
@ -1126,23 +1126,23 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
case 0x38: case 0x38:
/* WRUSP */ /* WRUSP */
tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env, tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, usp)); offsetof(CPUAlphaState, usp));
break; break;
case 0x3A: case 0x3A:
/* RDUSP */ /* RDUSP */
tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env, tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,
offsetof(CPUAlphaState, usp)); offsetof(CPUAlphaState, usp));
break; break;
case 0x3C: case 0x3C:
/* WHAMI */ /* WHAMI */
tcg_gen_ld32s_i64(ctx->ir[IR_V0], cpu_env, tcg_gen_ld32s_i64(ctx->ir[IR_V0], tcg_env,
-offsetof(AlphaCPU, env) + offsetof(CPUState, cpu_index)); -offsetof(AlphaCPU, env) + offsetof(CPUState, cpu_index));
break; break;
case 0x3E: case 0x3E:
/* WTINT */ /* WTINT */
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(AlphaCPU, env) + -offsetof(AlphaCPU, env) +
offsetof(CPUState, halted)); offsetof(CPUState, halted));
tcg_gen_movi_i64(ctx->ir[IR_V0], 0); tcg_gen_movi_i64(ctx->ir[IR_V0], 0);
@ -1174,7 +1174,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
} }
tcg_gen_movi_i64(tmp, exc_addr); tcg_gen_movi_i64(tmp, exc_addr);
tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr)); tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr));
entry += (palcode & 0x80 entry += (palcode & 0x80
? 0x2000 + (palcode - 0x80) * 64 ? 0x2000 + (palcode - 0x80) * 64
@ -1254,9 +1254,9 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno)
if (data == 0) { if (data == 0) {
tcg_gen_movi_i64(va, 0); tcg_gen_movi_i64(va, 0);
} else if (data & PR_LONG) { } else if (data & PR_LONG) {
tcg_gen_ld32s_i64(va, cpu_env, data & ~PR_LONG); tcg_gen_ld32s_i64(va, tcg_env, data & ~PR_LONG);
} else { } else {
tcg_gen_ld_i64(va, cpu_env, data); tcg_gen_ld_i64(va, tcg_env, data);
} }
break; break;
} }
@ -1272,17 +1272,17 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
switch (regno) { switch (regno) {
case 255: case 255:
/* TBIA */ /* TBIA */
gen_helper_tbia(cpu_env); gen_helper_tbia(tcg_env);
break; break;
case 254: case 254:
/* TBIS */ /* TBIS */
gen_helper_tbis(cpu_env, vb); gen_helper_tbis(tcg_env, vb);
break; break;
case 253: case 253:
/* WAIT */ /* WAIT */
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(AlphaCPU, env) + offsetof(CPUState, halted)); -offsetof(AlphaCPU, env) + offsetof(CPUState, halted));
return gen_excp(ctx, EXCP_HALTED, 0); return gen_excp(ctx, EXCP_HALTED, 0);
@ -1296,16 +1296,16 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
if (translator_io_start(&ctx->base)) { if (translator_io_start(&ctx->base)) {
ret = DISAS_PC_STALE; ret = DISAS_PC_STALE;
} }
gen_helper_set_alarm(cpu_env, vb); gen_helper_set_alarm(tcg_env, vb);
break; break;
case 7: case 7:
/* PALBR */ /* PALBR */
tcg_gen_st_i64(vb, cpu_env, offsetof(CPUAlphaState, palbr)); tcg_gen_st_i64(vb, tcg_env, offsetof(CPUAlphaState, palbr));
/* Changing the PAL base register implies un-chaining all of the TBs /* Changing the PAL base register implies un-chaining all of the TBs
that ended with a CALL_PAL. Since the base register usually only that ended with a CALL_PAL. Since the base register usually only
changes during boot, flushing everything works well. */ changes during boot, flushing everything works well. */
gen_helper_tb_flush(cpu_env); gen_helper_tb_flush(tcg_env);
return DISAS_PC_STALE; return DISAS_PC_STALE;
case 32 ... 39: case 32 ... 39:
@ -1327,9 +1327,9 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
data = cpu_pr_data(regno); data = cpu_pr_data(regno);
if (data != 0) { if (data != 0) {
if (data & PR_LONG) { if (data & PR_LONG) {
tcg_gen_st32_i64(vb, cpu_env, data & ~PR_LONG); tcg_gen_st32_i64(vb, tcg_env, data & ~PR_LONG);
} else { } else {
tcg_gen_st_i64(vb, cpu_env, data); tcg_gen_st_i64(vb, tcg_env, data);
} }
} }
break; break;
@ -1594,7 +1594,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tcg_gen_ext32s_i64(vc, vb); tcg_gen_ext32s_i64(vc, vb);
tcg_gen_add_i64(tmp, tmp, vc); tcg_gen_add_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp); tcg_gen_ext32s_i64(vc, tmp);
gen_helper_check_overflow(cpu_env, vc, tmp); gen_helper_check_overflow(tcg_env, vc, tmp);
break; break;
case 0x49: case 0x49:
/* SUBL/V */ /* SUBL/V */
@ -1603,7 +1603,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tcg_gen_ext32s_i64(vc, vb); tcg_gen_ext32s_i64(vc, vb);
tcg_gen_sub_i64(tmp, tmp, vc); tcg_gen_sub_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp); tcg_gen_ext32s_i64(vc, tmp);
gen_helper_check_overflow(cpu_env, vc, tmp); gen_helper_check_overflow(tcg_env, vc, tmp);
break; break;
case 0x4D: case 0x4D:
/* CMPLT */ /* CMPLT */
@ -1620,7 +1620,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tcg_gen_and_i64(tmp, tmp, tmp2); tcg_gen_and_i64(tmp, tmp, tmp2);
tcg_gen_shri_i64(tmp, tmp, 63); tcg_gen_shri_i64(tmp, tmp, 63);
tcg_gen_movi_i64(tmp2, 0); tcg_gen_movi_i64(tmp2, 0);
gen_helper_check_overflow(cpu_env, tmp, tmp2); gen_helper_check_overflow(tcg_env, tmp, tmp2);
break; break;
case 0x69: case 0x69:
/* SUBQ/V */ /* SUBQ/V */
@ -1633,7 +1633,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tcg_gen_and_i64(tmp, tmp, tmp2); tcg_gen_and_i64(tmp, tmp, tmp2);
tcg_gen_shri_i64(tmp, tmp, 63); tcg_gen_shri_i64(tmp, tmp, 63);
tcg_gen_movi_i64(tmp2, 0); tcg_gen_movi_i64(tmp2, 0);
gen_helper_check_overflow(cpu_env, tmp, tmp2); gen_helper_check_overflow(tcg_env, tmp, tmp2);
break; break;
case 0x6D: case 0x6D:
/* CMPLE */ /* CMPLE */
@ -1924,7 +1924,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tcg_gen_ext32s_i64(vc, vb); tcg_gen_ext32s_i64(vc, vb);
tcg_gen_mul_i64(tmp, tmp, vc); tcg_gen_mul_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp); tcg_gen_ext32s_i64(vc, tmp);
gen_helper_check_overflow(cpu_env, vc, tmp); gen_helper_check_overflow(tcg_env, vc, tmp);
break; break;
case 0x60: case 0x60:
/* MULQ/V */ /* MULQ/V */
@ -1932,7 +1932,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
tmp2 = tcg_temp_new(); tmp2 = tcg_temp_new();
tcg_gen_muls2_i64(vc, tmp, va, vb); tcg_gen_muls2_i64(vc, tmp, va, vb);
tcg_gen_sari_i64(tmp2, vc, 63); tcg_gen_sari_i64(tmp2, vc, 63);
gen_helper_check_overflow(cpu_env, tmp, tmp2); gen_helper_check_overflow(tcg_env, tmp, tmp2);
break; break;
default: default:
goto invalid_opc; goto invalid_opc;
@ -1957,7 +1957,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN; REQUIRE_FEN;
vb = load_fpr(ctx, rb); vb = load_fpr(ctx, rb);
gen_helper_sqrtf(vc, cpu_env, vb); gen_helper_sqrtf(vc, tcg_env, vb);
break; break;
case 0x0B: case 0x0B:
/* SQRTS */ /* SQRTS */
@ -1986,7 +1986,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN; REQUIRE_FEN;
vb = load_fpr(ctx, rb); vb = load_fpr(ctx, rb);
gen_helper_sqrtg(vc, cpu_env, vb); gen_helper_sqrtg(vc, tcg_env, vb);
break; break;
case 0x02B: case 0x02B:
/* SQRTT */ /* SQRTT */
@ -2009,22 +2009,22 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x00: case 0x00:
/* ADDF */ /* ADDF */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_addf(vc, cpu_env, va, vb); gen_helper_addf(vc, tcg_env, va, vb);
break; break;
case 0x01: case 0x01:
/* SUBF */ /* SUBF */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_subf(vc, cpu_env, va, vb); gen_helper_subf(vc, tcg_env, va, vb);
break; break;
case 0x02: case 0x02:
/* MULF */ /* MULF */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_mulf(vc, cpu_env, va, vb); gen_helper_mulf(vc, tcg_env, va, vb);
break; break;
case 0x03: case 0x03:
/* DIVF */ /* DIVF */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_divf(vc, cpu_env, va, vb); gen_helper_divf(vc, tcg_env, va, vb);
break; break;
case 0x1E: case 0x1E:
/* CVTDG -- TODO */ /* CVTDG -- TODO */
@ -2033,43 +2033,43 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x20: case 0x20:
/* ADDG */ /* ADDG */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_addg(vc, cpu_env, va, vb); gen_helper_addg(vc, tcg_env, va, vb);
break; break;
case 0x21: case 0x21:
/* SUBG */ /* SUBG */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_subg(vc, cpu_env, va, vb); gen_helper_subg(vc, tcg_env, va, vb);
break; break;
case 0x22: case 0x22:
/* MULG */ /* MULG */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_mulg(vc, cpu_env, va, vb); gen_helper_mulg(vc, tcg_env, va, vb);
break; break;
case 0x23: case 0x23:
/* DIVG */ /* DIVG */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_divg(vc, cpu_env, va, vb); gen_helper_divg(vc, tcg_env, va, vb);
break; break;
case 0x25: case 0x25:
/* CMPGEQ */ /* CMPGEQ */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_cmpgeq(vc, cpu_env, va, vb); gen_helper_cmpgeq(vc, tcg_env, va, vb);
break; break;
case 0x26: case 0x26:
/* CMPGLT */ /* CMPGLT */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_cmpglt(vc, cpu_env, va, vb); gen_helper_cmpglt(vc, tcg_env, va, vb);
break; break;
case 0x27: case 0x27:
/* CMPGLE */ /* CMPGLE */
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_cmpgle(vc, cpu_env, va, vb); gen_helper_cmpgle(vc, tcg_env, va, vb);
break; break;
case 0x2C: case 0x2C:
/* CVTGF */ /* CVTGF */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_cvtgf(vc, cpu_env, vb); gen_helper_cvtgf(vc, tcg_env, vb);
break; break;
case 0x2D: case 0x2D:
/* CVTGD -- TODO */ /* CVTGD -- TODO */
@ -2079,19 +2079,19 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
/* CVTGQ */ /* CVTGQ */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_cvtgq(vc, cpu_env, vb); gen_helper_cvtgq(vc, tcg_env, vb);
break; break;
case 0x3C: case 0x3C:
/* CVTQF */ /* CVTQF */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_cvtqf(vc, cpu_env, vb); gen_helper_cvtqf(vc, tcg_env, vb);
break; break;
case 0x3E: case 0x3E:
/* CVTQG */ /* CVTQG */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN; REQUIRE_FEN;
gen_helper_cvtqg(vc, cpu_env, vb); gen_helper_cvtqg(vc, tcg_env, vb);
break; break;
default: default:
goto invalid_opc; goto invalid_opc;
@ -2242,7 +2242,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
/* MT_FPCR */ /* MT_FPCR */
REQUIRE_FEN; REQUIRE_FEN;
va = load_fpr(ctx, ra); va = load_fpr(ctx, ra);
gen_helper_store_fpcr(cpu_env, va); gen_helper_store_fpcr(tcg_env, va);
if (ctx->tb_rm == QUAL_RM_D) { if (ctx->tb_rm == QUAL_RM_D) {
/* Re-do the copy of the rounding mode to fp_status /* Re-do the copy of the rounding mode to fp_status
the next time we use dynamic rounding. */ the next time we use dynamic rounding. */
@ -2253,7 +2253,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
/* MF_FPCR */ /* MF_FPCR */
REQUIRE_FEN; REQUIRE_FEN;
va = dest_fpr(ctx, ra); va = dest_fpr(ctx, ra);
gen_helper_load_fpcr(va, cpu_env); gen_helper_load_fpcr(va, tcg_env);
break; break;
case 0x02A: case 0x02A:
/* FCMOVEQ */ /* FCMOVEQ */
@ -2292,7 +2292,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
REQUIRE_FEN; REQUIRE_FEN;
vc = dest_fpr(ctx, rc); vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb); vb = load_fpr(ctx, rb);
gen_helper_cvtql(vc, cpu_env, vb); gen_helper_cvtql(vc, tcg_env, vb);
gen_fp_exc_raise(rc, fn11); gen_fp_exc_raise(rc, fn11);
break; break;
default: default:
@ -2332,7 +2332,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
if (translator_io_start(&ctx->base)) { if (translator_io_start(&ctx->base)) {
ret = DISAS_PC_STALE; ret = DISAS_PC_STALE;
} }
gen_helper_load_pcc(va, cpu_env); gen_helper_load_pcc(va, tcg_env);
break; break;
case 0xE000: case 0xE000:
/* RC */ /* RC */
@ -2628,7 +2628,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
address from EXC_ADDR. This turns out to be useful for our address from EXC_ADDR. This turns out to be useful for our
emulation PALcode, so continue to accept it. */ emulation PALcode, so continue to accept it. */
vb = dest_sink(ctx); vb = dest_sink(ctx);
tcg_gen_ld_i64(vb, cpu_env, offsetof(CPUAlphaState, exc_addr)); tcg_gen_ld_i64(vb, tcg_env, offsetof(CPUAlphaState, exc_addr));
} else { } else {
vb = load_gpr(ctx, rb); vb = load_gpr(ctx, rb);
} }

2
target/arm/tcg/translate-a32.h
View File

@ -55,7 +55,7 @@ bool mve_skip_vmov(DisasContext *s, int vn, int index, int size);
static inline TCGv_i32 load_cpu_offset(int offset) static inline TCGv_i32 load_cpu_offset(int offset)
{ {
TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_ld_i32(tmp, cpu_env, offset); tcg_gen_ld_i32(tmp, tcg_env, offset);
return tmp; return tmp;
} }

378
target/arm/tcg/translate-a64.c
View File

File diff suppressed because it is too large Load Diff

4
target/arm/tcg/translate-a64.h
View File

@ -115,7 +115,7 @@ static inline int vec_full_reg_offset(DisasContext *s, int regno)
static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
{ {
TCGv_ptr ret = tcg_temp_new_ptr(); TCGv_ptr ret = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno)); tcg_gen_addi_ptr(ret, tcg_env, vec_full_reg_offset(s, regno));
return ret; return ret;
} }
@ -179,7 +179,7 @@ static inline int pred_gvec_reg_size(DisasContext *s)
static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno) static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno)
{ {
TCGv_ptr ret = tcg_temp_new_ptr(); TCGv_ptr ret = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno)); tcg_gen_addi_ptr(ret, tcg_env, pred_full_reg_offset(s, regno));
return ret; return ret;
} }

24
target/arm/tcg/translate-m-nocp.c
View File

@ -85,9 +85,9 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
fptr = load_reg(s, a->rn); fptr = load_reg(s, a->rn);
if (a->l) { if (a->l) {
gen_helper_v7m_vlldm(cpu_env, fptr); gen_helper_v7m_vlldm(tcg_env, fptr);
} else { } else {
gen_helper_v7m_vlstm(cpu_env, fptr); gen_helper_v7m_vlstm(tcg_env, fptr);
} }
clear_eci_state(s); clear_eci_state(s);
@ -322,7 +322,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
switch (regno) { switch (regno) {
case ARM_VFP_FPSCR: case ARM_VFP_FPSCR:
tmp = loadfn(s, opaque, true); tmp = loadfn(s, opaque, true);
gen_helper_vfp_set_fpscr(cpu_env, tmp); gen_helper_vfp_set_fpscr(tcg_env, tmp);
gen_lookup_tb(s); gen_lookup_tb(s);
break; break;
case ARM_VFP_FPSCR_NZCVQC: case ARM_VFP_FPSCR_NZCVQC:
@ -391,7 +391,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
R_V7M_CONTROL_SFPA_SHIFT, 1); R_V7M_CONTROL_SFPA_SHIFT, 1);
store_cpu_field(control, v7m.control[M_REG_S]); store_cpu_field(control, v7m.control[M_REG_S]);
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
gen_helper_vfp_set_fpscr(cpu_env, tmp); gen_helper_vfp_set_fpscr(tcg_env, tmp);
s->base.is_jmp = DISAS_UPDATE_NOCHAIN; s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
break; break;
} }
@ -451,12 +451,12 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
switch (regno) { switch (regno) {
case ARM_VFP_FPSCR: case ARM_VFP_FPSCR:
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env); gen_helper_vfp_get_fpscr(tmp, tcg_env);
storefn(s, opaque, tmp, true); storefn(s, opaque, tmp, true);
break; break;
case ARM_VFP_FPSCR_NZCVQC: case ARM_VFP_FPSCR_NZCVQC:
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env); gen_helper_vfp_get_fpscr(tmp, tcg_env);
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK); tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK);
storefn(s, opaque, tmp, true); storefn(s, opaque, tmp, true);
break; break;
@ -475,7 +475,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
/* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */ /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
sfpa = tcg_temp_new_i32(); sfpa = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env); gen_helper_vfp_get_fpscr(tmp, tcg_env);
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
control = load_cpu_field(v7m.control[M_REG_S]); control = load_cpu_field(v7m.control[M_REG_S]);
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
@ -493,7 +493,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK); tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
store_cpu_field(control, v7m.control[M_REG_S]); store_cpu_field(control, v7m.control[M_REG_S]);
fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
gen_helper_vfp_set_fpscr(cpu_env, fpscr); gen_helper_vfp_set_fpscr(tcg_env, fpscr);
lookup_tb = true; lookup_tb = true;
break; break;
} }
@ -528,7 +528,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
sfpa = tcg_temp_new_i32(); sfpa = tcg_temp_new_i32();
fpscr = tcg_temp_new_i32(); fpscr = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(fpscr, cpu_env); gen_helper_vfp_get_fpscr(fpscr, tcg_env);
tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
control = load_cpu_field(v7m.control[M_REG_S]); control = load_cpu_field(v7m.control[M_REG_S]);
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
@ -540,7 +540,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0), tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0),
fpdscr, fpscr); fpdscr, fpscr);
gen_helper_vfp_set_fpscr(cpu_env, fpscr); gen_helper_vfp_set_fpscr(tcg_env, fpscr);
break; break;
} }
case ARM_VFP_VPR: case ARM_VFP_VPR:
@ -643,7 +643,7 @@ static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value,
} }
if (s->v8m_stackcheck && a->rn == 13 && a->w) { if (s->v8m_stackcheck && a->rn == 13 && a->w) {
gen_helper_v8m_stackcheck(cpu_env, addr); gen_helper_v8m_stackcheck(tcg_env, addr);
} }
if (do_access) { if (do_access) {
@ -682,7 +682,7 @@ static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque,
} }
if (s->v8m_stackcheck && a->rn == 13 && a->w) { if (s->v8m_stackcheck && a->rn == 13 && a->w) {
gen_helper_v8m_stackcheck(cpu_env, addr); gen_helper_v8m_stackcheck(tcg_env, addr);
} }
if (do_access) { if (do_access) {

52
target/arm/tcg/translate-mve.c
View File

@ -56,7 +56,7 @@ static inline long mve_qreg_offset(unsigned reg)
static TCGv_ptr mve_qreg_ptr(unsigned reg) static TCGv_ptr mve_qreg_ptr(unsigned reg)
{ {
TCGv_ptr ret = tcg_temp_new_ptr(); TCGv_ptr ret = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg)); tcg_gen_addi_ptr(ret, tcg_env, mve_qreg_offset(reg));
return ret; return ret;
} }
@ -173,7 +173,7 @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
} }
qreg = mve_qreg_ptr(a->qd); qreg = mve_qreg_ptr(a->qd);
fn(cpu_env, qreg, addr); fn(tcg_env, qreg, addr);
/* /*
* Writeback always happens after the last beat of the insn, * Writeback always happens after the last beat of the insn,
@ -234,7 +234,7 @@ static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a, MVEGenLdStSGFn fn)
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, addr); fn(tcg_env, qd, qm, addr);
mve_update_eci(s); mve_update_eci(s);
return true; return true;
} }
@ -330,7 +330,7 @@ static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_sg_imm *a,
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, tcg_constant_i32(offset)); fn(tcg_env, qd, qm, tcg_constant_i32(offset));
mve_update_eci(s); mve_update_eci(s);
return true; return true;
} }
@ -397,7 +397,7 @@ static bool do_vldst_il(DisasContext *s, arg_vldst_il *a, MVEGenLdStIlFn *fn,
* We pass the index of Qd, not a pointer, because the helper must * We pass the index of Qd, not a pointer, because the helper must
* access multiple Q registers starting at Qd and working up. * access multiple Q registers starting at Qd and working up.
*/ */
fn(cpu_env, tcg_constant_i32(a->qd), rn); fn(tcg_env, tcg_constant_i32(a->qd), rn);
if (a->w) { if (a->w) {
tcg_gen_addi_i32(rn, rn, addrinc); tcg_gen_addi_i32(rn, rn, addrinc);
@ -491,7 +491,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
} else { } else {
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
tcg_gen_dup_i32(a->size, rt, rt); tcg_gen_dup_i32(a->size, rt, rt);
gen_helper_mve_vdup(cpu_env, qd, rt); gen_helper_mve_vdup(tcg_env, qd, rt);
} }
mve_update_eci(s); mve_update_eci(s);
return true; return true;
@ -517,7 +517,7 @@ static bool do_1op_vec(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn,
} else { } else {
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm); fn(tcg_env, qd, qm);
} }
mve_update_eci(s); mve_update_eci(s);
return true; return true;
@ -612,7 +612,7 @@ static bool do_vcvt_rmode(DisasContext *s, arg_1op *a,
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode))); fn(tcg_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode)));
mve_update_eci(s); mve_update_eci(s);
return true; return true;
} }
@ -800,7 +800,7 @@ static bool do_2op_vec(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn,
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
qn = mve_qreg_ptr(a->qn); qn = mve_qreg_ptr(a->qn);
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qn, qm); fn(tcg_env, qd, qn, qm);
} }
mve_update_eci(s); mve_update_eci(s);
return true; return true;
@ -1052,7 +1052,7 @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
qn = mve_qreg_ptr(a->qn); qn = mve_qreg_ptr(a->qn);
rm = load_reg(s, a->rm); rm = load_reg(s, a->rm);
fn(cpu_env, qd, qn, rm); fn(tcg_env, qd, qn, rm);
mve_update_eci(s); mve_update_eci(s);
return true; return true;
} }
@ -1183,7 +1183,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
rda_i = tcg_constant_i64(0); rda_i = tcg_constant_i64(0);
} }
fn(rda_o, cpu_env, qn, qm, rda_i); fn(rda_o, tcg_env, qn, qm, rda_i);
rdalo = tcg_temp_new_i32(); rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32(); rdahi = tcg_temp_new_i32();
@ -1281,7 +1281,7 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
rda_o = tcg_temp_new_i32(); rda_o = tcg_temp_new_i32();
} }
fn(rda_o, cpu_env, qn, qm, rda_i); fn(rda_o, tcg_env, qn, qm, rda_i);
store_reg(s, a->rda, rda_o); store_reg(s, a->rda, rda_o);
mve_update_eci(s); mve_update_eci(s);
@ -1377,7 +1377,7 @@ static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a)
return true; return true;
} }
gen_helper_mve_vpnot(cpu_env); gen_helper_mve_vpnot(tcg_env);
/* This insn updates predication bits */ /* This insn updates predication bits */
s->base.is_jmp = DISAS_UPDATE_NOCHAIN; s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
mve_update_eci(s); mve_update_eci(s);
@ -1419,7 +1419,7 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
} }
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
fns[a->size][a->u](rda_o, cpu_env, qm, rda_i); fns[a->size][a->u](rda_o, tcg_env, qm, rda_i);
store_reg(s, a->rda, rda_o); store_reg(s, a->rda, rda_o);
mve_update_eci(s); mve_update_eci(s);
@ -1471,9 +1471,9 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
if (a->u) { if (a->u) {
gen_helper_mve_vaddlv_u(rda_o, cpu_env, qm, rda_i); gen_helper_mve_vaddlv_u(rda_o, tcg_env, qm, rda_i);
} else { } else {
gen_helper_mve_vaddlv_s(rda_o, cpu_env, qm, rda_i); gen_helper_mve_vaddlv_s(rda_o, tcg_env, qm, rda_i);
} }
rdalo = tcg_temp_new_i32(); rdalo = tcg_temp_new_i32();
@ -1508,7 +1508,7 @@ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn,
imm, 16, 16); imm, 16, 16);
} else { } else {
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
fn(cpu_env, qd, tcg_constant_i64(imm)); fn(tcg_env, qd, tcg_constant_i64(imm));
} }
mve_update_eci(s); mve_update_eci(s);
return true; return true;
@ -1580,7 +1580,7 @@ static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
} else { } else {
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, tcg_constant_i32(shift)); fn(tcg_env, qd, qm, tcg_constant_i32(shift));
} }
mve_update_eci(s); mve_update_eci(s);
return true; return true;
@ -1685,7 +1685,7 @@ static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a,
qda = mve_qreg_ptr(a->qda); qda = mve_qreg_ptr(a->qda);
rm = load_reg(s, a->rm); rm = load_reg(s, a->rm);
fn(cpu_env, qda, qda, rm); fn(tcg_env, qda, qda, rm);
mve_update_eci(s); mve_update_eci(s);
return true; return true;
} }
@ -1827,7 +1827,7 @@ static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
rdm = load_reg(s, a->rdm); rdm = load_reg(s, a->rdm);
gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); gen_helper_mve_vshlc(rdm, tcg_env, qd, rdm, tcg_constant_i32(a->imm));
store_reg(s, a->rdm, rdm); store_reg(s, a->rdm, rdm);
mve_update_eci(s); mve_update_eci(s);
return true; return true;
@ -1856,7 +1856,7 @@ static bool do_vidup(DisasContext *s, arg_vidup *a, MVEGenVIDUPFn *fn)
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
rn = load_reg(s, a->rn); rn = load_reg(s, a->rn);
fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm)); fn(rn, tcg_env, qd, rn, tcg_constant_i32(a->imm));
store_reg(s, a->rn, rn); store_reg(s, a->rn, rn);
mve_update_eci(s); mve_update_eci(s);
return true; return true;
@ -1891,7 +1891,7 @@ static bool do_viwdup(DisasContext *s, arg_viwdup *a, MVEGenVIWDUPFn *fn)
qd = mve_qreg_ptr(a->qd); qd = mve_qreg_ptr(a->qd);
rn = load_reg(s, a->rn); rn = load_reg(s, a->rn);
rm = load_reg(s, a->rm); rm = load_reg(s, a->rm);
fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm)); fn(rn, tcg_env, qd, rn, rm, tcg_constant_i32(a->imm));
store_reg(s, a->rn, rn); store_reg(s, a->rn, rn);
mve_update_eci(s); mve_update_eci(s);
return true; return true;
@ -1957,7 +1957,7 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn)
qn = mve_qreg_ptr(a->qn); qn = mve_qreg_ptr(a->qn);
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qn, qm); fn(tcg_env, qn, qm);
if (a->mask) { if (a->mask) {
/* VPT */ /* VPT */
gen_vpst(s, a->mask); gen_vpst(s, a->mask);
@ -1988,7 +1988,7 @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a,
} else { } else {
rm = load_reg(s, a->rm); rm = load_reg(s, a->rm);
} }
fn(cpu_env, qn, rm); fn(tcg_env, qn, rm);
if (a->mask) { if (a->mask) {
/* VPT */ /* VPT */
gen_vpst(s, a->mask); gen_vpst(s, a->mask);
@ -2089,7 +2089,7 @@ static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn)
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
rda = load_reg(s, a->rda); rda = load_reg(s, a->rda);
fn(rda, cpu_env, qm, rda); fn(rda, tcg_env, qm, rda);
store_reg(s, a->rda, rda); store_reg(s, a->rda, rda);
mve_update_eci(s); mve_update_eci(s);
return true; return true;
@ -2153,7 +2153,7 @@ static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn)
qm = mve_qreg_ptr(a->qm); qm = mve_qreg_ptr(a->qm);
qn = mve_qreg_ptr(a->qn); qn = mve_qreg_ptr(a->qn);
rda = load_reg(s, a->rda); rda = load_reg(s, a->rda);
fn(rda, cpu_env, qn, qm, rda); fn(rda, tcg_env, qn, qm, rda);
store_reg(s, a->rda, rda); store_reg(s, a->rda, rda);
mve_update_eci(s); mve_update_eci(s);
return true; return true;

78
target/arm/tcg/translate-neon.c
View File

@ -32,7 +32,7 @@
static TCGv_ptr vfp_reg_ptr(bool dp, int reg) static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
{ {
TCGv_ptr ret = tcg_temp_new_ptr(); TCGv_ptr ret = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); tcg_gen_addi_ptr(ret, tcg_env, vfp_reg_offset(dp, reg));
return ret; return ret;
} }
@ -42,13 +42,13 @@ static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
switch (mop) { switch (mop) {
case MO_UB: case MO_UB:
tcg_gen_ld8u_i32(var, cpu_env, offset); tcg_gen_ld8u_i32(var, tcg_env, offset);
break; break;
case MO_UW: case MO_UW:
tcg_gen_ld16u_i32(var, cpu_env, offset); tcg_gen_ld16u_i32(var, tcg_env, offset);
break; break;
case MO_UL: case MO_UL:
tcg_gen_ld_i32(var, cpu_env, offset); tcg_gen_ld_i32(var, tcg_env, offset);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -61,16 +61,16 @@ static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
switch (mop) { switch (mop) {
case MO_UB: case MO_UB:
tcg_gen_ld8u_i64(var, cpu_env, offset); tcg_gen_ld8u_i64(var, tcg_env, offset);
break; break;
case MO_UW: case MO_UW:
tcg_gen_ld16u_i64(var, cpu_env, offset); tcg_gen_ld16u_i64(var, tcg_env, offset);
break; break;
case MO_UL: case MO_UL:
tcg_gen_ld32u_i64(var, cpu_env, offset); tcg_gen_ld32u_i64(var, tcg_env, offset);
break; break;
case MO_UQ: case MO_UQ:
tcg_gen_ld_i64(var, cpu_env, offset); tcg_gen_ld_i64(var, tcg_env, offset);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -83,13 +83,13 @@ static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
switch (size) { switch (size) {
case MO_8: case MO_8:
tcg_gen_st8_i32(var, cpu_env, offset); tcg_gen_st8_i32(var, tcg_env, offset);
break; break;
case MO_16: case MO_16:
tcg_gen_st16_i32(var, cpu_env, offset); tcg_gen_st16_i32(var, tcg_env, offset);
break; break;
case MO_32: case MO_32:
tcg_gen_st_i32(var, cpu_env, offset); tcg_gen_st_i32(var, tcg_env, offset);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -102,16 +102,16 @@ static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
switch (size) { switch (size) {
case MO_8: case MO_8:
tcg_gen_st8_i64(var, cpu_env, offset); tcg_gen_st8_i64(var, tcg_env, offset);
break; break;
case MO_16: case MO_16:
tcg_gen_st16_i64(var, cpu_env, offset); tcg_gen_st16_i64(var, tcg_env, offset);
break; break;
case MO_32: case MO_32:
tcg_gen_st32_i64(var, cpu_env, offset); tcg_gen_st32_i64(var, tcg_env, offset);
break; break;
case MO_64: case MO_64:
tcg_gen_st_i64(var, cpu_env, offset); tcg_gen_st_i64(var, tcg_env, offset);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -296,7 +296,7 @@ static bool trans_VFML(DisasContext *s, arg_VFML *a)
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
vfp_reg_offset(a->q, a->vn), vfp_reg_offset(a->q, a->vn),
vfp_reg_offset(a->q, a->vm), vfp_reg_offset(a->q, a->vm),
cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */ tcg_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
gen_helper_gvec_fmlal_a32); gen_helper_gvec_fmlal_a32);
return true; return true;
} }
@ -390,7 +390,7 @@ static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
vfp_reg_offset(a->q, a->vn), vfp_reg_offset(a->q, a->vn),
vfp_reg_offset(a->q, a->rm), vfp_reg_offset(a->q, a->rm),
cpu_env, opr_sz, opr_sz, tcg_env, opr_sz, opr_sz,
(a->index << 2) | a->s, /* is_2 == 0 */ (a->index << 2) | a->s, /* is_2 == 0 */
gen_helper_gvec_fmlal_idx_a32); gen_helper_gvec_fmlal_idx_a32);
return true; return true;
@ -920,7 +920,7 @@ DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1)
#define DO_3SAME_64_ENV(INSN, FUNC) \ #define DO_3SAME_64_ENV(INSN, FUNC) \
static void gen_##INSN##_elt(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \ static void gen_##INSN##_elt(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \
{ \ { \
FUNC(d, cpu_env, n, m); \ FUNC(d, tcg_env, n, m); \
} \ } \
DO_3SAME_64(INSN, gen_##INSN##_elt) DO_3SAME_64(INSN, gen_##INSN##_elt)
@ -953,7 +953,7 @@ DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64)
} }
/* /*
* Some helper functions need to be passed the cpu_env. In order * Some helper functions need to be passed the tcg_env. In order
* to use those with the gvec APIs like tcg_gen_gvec_3() we need * to use those with the gvec APIs like tcg_gen_gvec_3() we need
* to create wrapper functions whose prototype is a NeonGenTwoOpFn() * to create wrapper functions whose prototype is a NeonGenTwoOpFn()
* and which call a NeonGenTwoOpEnvFn(). * and which call a NeonGenTwoOpEnvFn().
@ -961,7 +961,7 @@ DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64)
#define WRAP_ENV_FN(WRAPNAME, FUNC) \ #define WRAP_ENV_FN(WRAPNAME, FUNC) \
static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \ static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \
{ \ { \
FUNC(d, cpu_env, n, m); \ FUNC(d, tcg_env, n, m); \
} }
#define DO_3SAME_32_ENV(INSN, FUNC) \ #define DO_3SAME_32_ENV(INSN, FUNC) \
@ -1305,7 +1305,7 @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
{ {
/* /*
* 2-reg-and-shift operations, size == 3 case, where the * 2-reg-and-shift operations, size == 3 case, where the
* function needs to be passed cpu_env. * function needs to be passed tcg_env.
*/ */
TCGv_i64 constimm; TCGv_i64 constimm;
int pass; int pass;
@ -1338,7 +1338,7 @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
TCGv_i64 tmp = tcg_temp_new_i64(); TCGv_i64 tmp = tcg_temp_new_i64();
read_neon_element64(tmp, a->vm, pass, MO_64); read_neon_element64(tmp, a->vm, pass, MO_64);
fn(tmp, cpu_env, tmp, constimm); fn(tmp, tcg_env, tmp, constimm);
write_neon_element64(tmp, a->vd, pass, MO_64); write_neon_element64(tmp, a->vd, pass, MO_64);
} }
return true; return true;
@ -1349,7 +1349,7 @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
{ {
/* /*
* 2-reg-and-shift operations, size < 3 case, where the * 2-reg-and-shift operations, size < 3 case, where the
* helper needs to be passed cpu_env. * helper needs to be passed tcg_env.
*/ */
TCGv_i32 constimm, tmp; TCGv_i32 constimm, tmp;
int pass; int pass;
@ -1381,7 +1381,7 @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
for (pass = 0; pass < (a->q ? 4 : 2); pass++) { for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
read_neon_element32(tmp, a->vm, pass, MO_32); read_neon_element32(tmp, a->vm, pass, MO_32);
fn(tmp, cpu_env, tmp, constimm); fn(tmp, tcg_env, tmp, constimm);
write_neon_element32(tmp, a->vd, pass, MO_32); write_neon_element32(tmp, a->vd, pass, MO_32);
} }
return true; return true;
@ -1447,11 +1447,11 @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
read_neon_element64(rm2, a->vm, 1, MO_64); read_neon_element64(rm2, a->vm, 1, MO_64);
shiftfn(rm1, rm1, constimm); shiftfn(rm1, rm1, constimm);
narrowfn(rd, cpu_env, rm1); narrowfn(rd, tcg_env, rm1);
write_neon_element32(rd, a->vd, 0, MO_32); write_neon_element32(rd, a->vd, 0, MO_32);
shiftfn(rm2, rm2, constimm); shiftfn(rm2, rm2, constimm);
narrowfn(rd, cpu_env, rm2); narrowfn(rd, tcg_env, rm2);
write_neon_element32(rd, a->vd, 1, MO_32); write_neon_element32(rd, a->vd, 1, MO_32);
return true; return true;
@ -1514,7 +1514,7 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
tcg_gen_concat_i32_i64(rtmp, rm1, rm2); tcg_gen_concat_i32_i64(rtmp, rm1, rm2);
narrowfn(rm1, cpu_env, rtmp); narrowfn(rm1, tcg_env, rtmp);
write_neon_element32(rm1, a->vd, 0, MO_32); write_neon_element32(rm1, a->vd, 0, MO_32);
shiftfn(rm3, rm3, constimm); shiftfn(rm3, rm3, constimm);
@ -1522,7 +1522,7 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
tcg_gen_concat_i32_i64(rtmp, rm3, rm4); tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
narrowfn(rm3, cpu_env, rtmp); narrowfn(rm3, tcg_env, rtmp);
write_neon_element32(rm3, a->vd, 1, MO_32); write_neon_element32(rm3, a->vd, 1, MO_32);
return true; return true;
} }
@ -2159,13 +2159,13 @@ DO_VMLAL(VMLSL_U,mull_u,sub)
static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
{ {
gen_helper_neon_mull_s16(rd, rn, rm); gen_helper_neon_mull_s16(rd, rn, rm);
gen_helper_neon_addl_saturate_s32(rd, cpu_env, rd, rd); gen_helper_neon_addl_saturate_s32(rd, tcg_env, rd, rd);
} }
static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
{ {
gen_mull_s32(rd, rn, rm); gen_mull_s32(rd, rn, rm);
gen_helper_neon_addl_saturate_s64(rd, cpu_env, rd, rd); gen_helper_neon_addl_saturate_s64(rd, tcg_env, rd, rd);
} }
static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a) static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a)
@ -2182,12 +2182,12 @@ static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a)
static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{ {
gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); gen_helper_neon_addl_saturate_s32(rd, tcg_env, rn, rm);
} }
static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{ {
gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); gen_helper_neon_addl_saturate_s64(rd, tcg_env, rn, rm);
} }
static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a) static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a)
@ -2211,13 +2211,13 @@ static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a)
static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{ {
gen_helper_neon_negl_u32(rm, rm); gen_helper_neon_negl_u32(rm, rm);
gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); gen_helper_neon_addl_saturate_s32(rd, tcg_env, rn, rm);
} }
static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{ {
tcg_gen_neg_i64(rm, rm); tcg_gen_neg_i64(rm, rm);
gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); gen_helper_neon_addl_saturate_s64(rd, tcg_env, rn, rm);
} }
static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a) static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a)
@ -2550,7 +2550,7 @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
for (pass = 0; pass < (a->q ? 4 : 2); pass++) { for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
read_neon_element32(rn, a->vn, pass, MO_32); read_neon_element32(rn, a->vn, pass, MO_32);
read_neon_element32(rd, a->vd, pass, MO_32); read_neon_element32(rd, a->vd, pass, MO_32);
opfn(rd, cpu_env, rn, scalar, rd); opfn(rd, tcg_env, rn, scalar, rd);
write_neon_element32(rd, a->vd, pass, MO_32); write_neon_element32(rd, a->vd, pass, MO_32);
} }
return true; return true;
@ -2837,7 +2837,7 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
val = tcg_temp_new_i64(); val = tcg_temp_new_i64();
read_neon_element64(val, a->vm, 0, MO_64); read_neon_element64(val, a->vm, 0, MO_64);
gen_helper_neon_tbl(val, cpu_env, desc, val, def); gen_helper_neon_tbl(val, tcg_env, desc, val, def);
write_neon_element64(val, a->vd, 0, MO_64); write_neon_element64(val, a->vd, 0, MO_64);
return true; return true;
} }
@ -3171,9 +3171,9 @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
rd1 = tcg_temp_new_i32(); rd1 = tcg_temp_new_i32();
read_neon_element64(rm, a->vm, 0, MO_64); read_neon_element64(rm, a->vm, 0, MO_64);
narrowfn(rd0, cpu_env, rm); narrowfn(rd0, tcg_env, rm);
read_neon_element64(rm, a->vm, 1, MO_64); read_neon_element64(rm, a->vm, 1, MO_64);
narrowfn(rd1, cpu_env, rm); narrowfn(rd1, tcg_env, rm);
write_neon_element32(rd0, a->vd, 0, MO_32); write_neon_element32(rd0, a->vd, 0, MO_32);
write_neon_element32(rd1, a->vd, 1, MO_32); write_neon_element32(rd1, a->vd, 1, MO_32);
return true; return true;
@ -3625,7 +3625,7 @@ static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a)
#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \ #define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \
static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \ static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \
{ \ { \
FUNC(d, cpu_env, m); \ FUNC(d, tcg_env, m); \
} }
WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8) WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8)

8
target/arm/tcg/translate-sme.c
View File

@ -90,7 +90,7 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
/* Add the byte offset to env to produce the final pointer. */ /* Add the byte offset to env to produce the final pointer. */
addr = tcg_temp_new_ptr(); addr = tcg_temp_new_ptr();
tcg_gen_ext_i32_ptr(addr, tmp); tcg_gen_ext_i32_ptr(addr, tmp);
tcg_gen_add_ptr(addr, addr, cpu_env); tcg_gen_add_ptr(addr, addr, tcg_env);
return addr; return addr;
} }
@ -106,7 +106,7 @@ static TCGv_ptr get_tile(DisasContext *s, int esz, int tile)
offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray); offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray);
tcg_gen_addi_ptr(addr, cpu_env, offset); tcg_gen_addi_ptr(addr, tcg_env, offset);
return addr; return addr;
} }
@ -116,7 +116,7 @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
return false; return false;
} }
if (sme_za_enabled_check(s)) { if (sme_za_enabled_check(s)) {
gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm), gen_helper_sme_zero(tcg_env, tcg_constant_i32(a->imm),
tcg_constant_i32(streaming_vec_reg_size(s))); tcg_constant_i32(streaming_vec_reg_size(s)));
} }
return true; return true;
@ -237,7 +237,7 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
svl = streaming_vec_reg_size(s); svl = streaming_vec_reg_size(s);
desc = simd_desc(svl, svl, desc); desc = simd_desc(svl, svl, desc);
fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr, fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
tcg_constant_i32(desc)); tcg_constant_i32(desc));
return true; return true;
} }

172
target/arm/tcg/translate-sve.c
View File

@ -497,8 +497,8 @@ static void do_predtest(DisasContext *s, int dofs, int gofs, int words)
TCGv_ptr gptr = tcg_temp_new_ptr(); TCGv_ptr gptr = tcg_temp_new_ptr();
TCGv_i32 t = tcg_temp_new_i32(); TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_addi_ptr(dptr, cpu_env, dofs); tcg_gen_addi_ptr(dptr, tcg_env, dofs);
tcg_gen_addi_ptr(gptr, cpu_env, gofs); tcg_gen_addi_ptr(gptr, tcg_env, gofs);
gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words)); gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words));
@ -956,8 +956,8 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
t_zn = tcg_temp_new_ptr(); t_zn = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr(); t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
fn(temp, t_zn, t_pg, desc); fn(temp, t_zn, t_pg, desc);
write_fp_dreg(s, a->rd, temp); write_fp_dreg(s, a->rd, temp);
@ -1209,7 +1209,7 @@ static bool do_index(DisasContext *s, int esz, int rd,
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
t_zd = tcg_temp_new_ptr(); t_zd = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, rd));
if (esz == 3) { if (esz == 3) {
gen_helper_sve_index_d(t_zd, start, incr, desc); gen_helper_sve_index_d(t_zd, start, incr, desc);
} else { } else {
@ -1379,12 +1379,12 @@ static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a,
TCGv_i64 pm = tcg_temp_new_i64(); TCGv_i64 pm = tcg_temp_new_i64();
TCGv_i64 pg = tcg_temp_new_i64(); TCGv_i64 pg = tcg_temp_new_i64();
tcg_gen_ld_i64(pn, cpu_env, nofs); tcg_gen_ld_i64(pn, tcg_env, nofs);
tcg_gen_ld_i64(pm, cpu_env, mofs); tcg_gen_ld_i64(pm, tcg_env, mofs);
tcg_gen_ld_i64(pg, cpu_env, gofs); tcg_gen_ld_i64(pg, tcg_env, gofs);
gvec_op->fni8(pd, pn, pm, pg); gvec_op->fni8(pd, pn, pm, pg);
tcg_gen_st_i64(pd, cpu_env, dofs); tcg_gen_st_i64(pd, tcg_env, dofs);
do_predtest1(pd, pg); do_predtest1(pd, pg);
} else { } else {
@ -1654,8 +1654,8 @@ static bool trans_PTEST(DisasContext *s, arg_PTEST *a)
TCGv_i64 pn = tcg_temp_new_i64(); TCGv_i64 pn = tcg_temp_new_i64();
TCGv_i64 pg = tcg_temp_new_i64(); TCGv_i64 pg = tcg_temp_new_i64();
tcg_gen_ld_i64(pn, cpu_env, nofs); tcg_gen_ld_i64(pn, tcg_env, nofs);
tcg_gen_ld_i64(pg, cpu_env, gofs); tcg_gen_ld_i64(pg, tcg_env, gofs);
do_predtest1(pn, pg); do_predtest1(pn, pg);
} else { } else {
do_predtest(s, nofs, gofs, words); do_predtest(s, nofs, gofs, words);
@ -1736,7 +1736,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
t = tcg_temp_new_i64(); t = tcg_temp_new_i64();
if (fullsz <= 64) { if (fullsz <= 64) {
tcg_gen_movi_i64(t, lastword); tcg_gen_movi_i64(t, lastword);
tcg_gen_st_i64(t, cpu_env, ofs); tcg_gen_st_i64(t, tcg_env, ofs);
goto done; goto done;
} }
@ -1755,17 +1755,17 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
tcg_gen_movi_i64(t, word); tcg_gen_movi_i64(t, word);
for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) { for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
tcg_gen_st_i64(t, cpu_env, ofs + i); tcg_gen_st_i64(t, tcg_env, ofs + i);
} }
if (lastword != word) { if (lastword != word) {
tcg_gen_movi_i64(t, lastword); tcg_gen_movi_i64(t, lastword);
tcg_gen_st_i64(t, cpu_env, ofs + i); tcg_gen_st_i64(t, tcg_env, ofs + i);
i += 8; i += 8;
} }
if (i < fullsz) { if (i < fullsz) {
tcg_gen_movi_i64(t, 0); tcg_gen_movi_i64(t, 0);
for (; i < fullsz; i += 8) { for (; i < fullsz; i += 8) {
tcg_gen_st_i64(t, cpu_env, ofs + i); tcg_gen_st_i64(t, tcg_env, ofs + i);
} }
} }
@ -1822,8 +1822,8 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(t_pd, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->rn));
t = tcg_temp_new_i32(); t = tcg_temp_new_i32();
gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc)); gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc));
@ -1919,8 +1919,8 @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
dptr = tcg_temp_new_ptr(); dptr = tcg_temp_new_ptr();
nptr = tcg_temp_new_ptr(); nptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd)); tcg_gen_addi_ptr(dptr, tcg_env, vec_full_reg_offset(s, rd));
tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn)); tcg_gen_addi_ptr(nptr, tcg_env, vec_full_reg_offset(s, rn));
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
switch (esz) { switch (esz) {
@ -2163,9 +2163,9 @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
TCGv_ptr t_zn = tcg_temp_new_ptr(); TCGv_ptr t_zn = tcg_temp_new_ptr();
TCGv_ptr t_pg = tcg_temp_new_ptr(); TCGv_ptr t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, rd));
tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, rn)); tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, rn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
fns[esz](t_zd, t_zn, t_pg, val, desc); fns[esz](t_zd, t_zn, t_pg, val, desc);
} }
@ -2310,8 +2310,8 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
TCGv_ptr t_zd = tcg_temp_new_ptr(); TCGv_ptr t_zd = tcg_temp_new_ptr();
TCGv_ptr t_zn = tcg_temp_new_ptr(); TCGv_ptr t_zn = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
fns[a->esz](t_zd, t_zn, val, desc); fns[a->esz](t_zd, t_zn, val, desc);
} }
@ -2323,7 +2323,7 @@ static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a)
} }
if (sve_access_check(s)) { if (sve_access_check(s)) {
TCGv_i64 t = tcg_temp_new_i64(); TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64)); tcg_gen_ld_i64(t, tcg_env, vec_reg_offset(s, a->rm, 0, MO_64));
do_insr_i64(s, a, t); do_insr_i64(s, a, t);
} }
return true; return true;
@ -2409,9 +2409,9 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd);
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(t_d, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_n, tcg_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(t_m, tcg_env, pred_full_reg_offset(s, a->rm));
fn(t_d, t_n, t_m, tcg_constant_i32(desc)); fn(t_d, t_n, t_m, tcg_constant_i32(desc));
return true; return true;
@ -2429,8 +2429,8 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
TCGv_ptr t_n = tcg_temp_new_ptr(); TCGv_ptr t_n = tcg_temp_new_ptr();
uint32_t desc = 0; uint32_t desc = 0;
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(t_d, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_n, tcg_env, pred_full_reg_offset(s, a->rn));
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
@ -2525,7 +2525,7 @@ static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg)
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz); desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg)); tcg_gen_addi_ptr(t_p, tcg_env, pred_full_reg_offset(s, pg));
gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc)); gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc));
} }
@ -2602,7 +2602,7 @@ static TCGv_i64 load_last_active(DisasContext *s, TCGv_i32 last,
} }
#endif #endif
tcg_gen_ext_i32_ptr(p, last); tcg_gen_ext_i32_ptr(p, last);
tcg_gen_add_ptr(p, p, cpu_env); tcg_gen_add_ptr(p, p, tcg_env);
return load_esz(p, vec_full_reg_offset(s, rm), esz); return load_esz(p, vec_full_reg_offset(s, rm), esz);
} }
@ -2674,7 +2674,7 @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
} }
/* The conceit here is that while last < 0 indicates not found, after /* The conceit here is that while last < 0 indicates not found, after
* adjusting for cpu_env->vfp.zregs[rm], it is still a valid address * adjusting for tcg_env->vfp.zregs[rm], it is still a valid address
* from which we can load garbage. We then discard the garbage with * from which we can load garbage. We then discard the garbage with
* a conditional move. * a conditional move.
*/ */
@ -2690,7 +2690,7 @@ static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before)
if (sve_access_check(s)) { if (sve_access_check(s)) {
int esz = a->esz; int esz = a->esz;
int ofs = vec_reg_offset(s, a->rd, 0, esz); int ofs = vec_reg_offset(s, a->rd, 0, esz);
TCGv_i64 reg = load_esz(cpu_env, ofs, esz); TCGv_i64 reg = load_esz(tcg_env, ofs, esz);
do_clast_scalar(s, esz, a->pg, a->rn, before, reg); do_clast_scalar(s, esz, a->pg, a->rn, before, reg);
write_fp_dreg(s, a->rd, reg); write_fp_dreg(s, a->rd, reg);
@ -2794,7 +2794,7 @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a)
} }
if (sve_access_check(s)) { if (sve_access_check(s)) {
int ofs = vec_reg_offset(s, a->rn, 0, a->esz); int ofs = vec_reg_offset(s, a->rn, 0, a->esz);
TCGv_i64 t = load_esz(cpu_env, ofs, a->esz); TCGv_i64 t = load_esz(tcg_env, ofs, a->esz);
do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t); do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t);
} }
return true; return true;
@ -2847,10 +2847,10 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
zm = tcg_temp_new_ptr(); zm = tcg_temp_new_ptr();
pg = tcg_temp_new_ptr(); pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(pd, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(zm, tcg_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); tcg_gen_addi_ptr(pg, tcg_env, pred_full_reg_offset(s, a->pg));
gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0))); gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0)));
@ -2920,9 +2920,9 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
zn = tcg_temp_new_ptr(); zn = tcg_temp_new_ptr();
pg = tcg_temp_new_ptr(); pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(pd, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); tcg_gen_addi_ptr(pg, tcg_env, pred_full_reg_offset(s, a->pg));
gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm))); gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm)));
@ -2971,10 +2971,10 @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
TCGv_ptr g = tcg_temp_new_ptr(); TCGv_ptr g = tcg_temp_new_ptr();
TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(d, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(n, tcg_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(m, cpu_env, pred_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(m, tcg_env, pred_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); tcg_gen_addi_ptr(g, tcg_env, pred_full_reg_offset(s, a->pg));
if (a->s) { if (a->s) {
TCGv_i32 t = tcg_temp_new_i32(); TCGv_i32 t = tcg_temp_new_i32();
@ -3001,9 +3001,9 @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
TCGv_ptr g = tcg_temp_new_ptr(); TCGv_ptr g = tcg_temp_new_ptr();
TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(d, tcg_env, pred_full_reg_offset(s, a->rd));
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(n, tcg_env, pred_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); tcg_gen_addi_ptr(g, tcg_env, pred_full_reg_offset(s, a->pg));
if (a->s) { if (a->s) {
TCGv_i32 t = tcg_temp_new_i32(); TCGv_i32 t = tcg_temp_new_i32();
@ -3044,10 +3044,10 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
if (psz <= 8) { if (psz <= 8) {
uint64_t psz_mask; uint64_t psz_mask;
tcg_gen_ld_i64(val, cpu_env, pred_full_reg_offset(s, pn)); tcg_gen_ld_i64(val, tcg_env, pred_full_reg_offset(s, pn));
if (pn != pg) { if (pn != pg) {
TCGv_i64 g = tcg_temp_new_i64(); TCGv_i64 g = tcg_temp_new_i64();
tcg_gen_ld_i64(g, cpu_env, pred_full_reg_offset(s, pg)); tcg_gen_ld_i64(g, tcg_env, pred_full_reg_offset(s, pg));
tcg_gen_and_i64(val, val, g); tcg_gen_and_i64(val, val, g);
} }
@ -3066,8 +3066,8 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz); desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz);
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz); desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn)); tcg_gen_addi_ptr(t_pn, tcg_env, pred_full_reg_offset(s, pn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc)); gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc));
} }
@ -3291,7 +3291,7 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
ptr = tcg_temp_new_ptr(); ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(ptr, tcg_env, pred_full_reg_offset(s, a->rd));
if (a->lt) { if (a->lt) {
gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
@ -3354,7 +3354,7 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
ptr = tcg_temp_new_ptr(); ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(ptr, tcg_env, pred_full_reg_offset(s, a->rd));
gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
do_pred_flags(t2); do_pred_flags(t2);
@ -3684,8 +3684,8 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
t_zn = tcg_temp_new_ptr(); t_zn = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr(); t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
fn(temp, t_zn, t_pg, status, t_desc); fn(temp, t_zn, t_pg, status, t_desc);
@ -3802,11 +3802,11 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
return true; return true;
} }
t_val = load_esz(cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz); t_val = load_esz(tcg_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz);
t_rm = tcg_temp_new_ptr(); t_rm = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr(); t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(t_rm, tcg_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
@ -3878,9 +3878,9 @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
t_zd = tcg_temp_new_ptr(); t_zd = tcg_temp_new_ptr();
t_zn = tcg_temp_new_ptr(); t_zn = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr(); t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, zd)); tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, zd));
tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, zn)); tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, zn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
@ -4228,7 +4228,7 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
/* /*
* Predicate register loads can be any multiple of 2. * Predicate register loads can be any multiple of 2.
* Note that we still store the entire 64-bit unit into cpu_env. * Note that we still store the entire 64-bit unit into tcg_env.
*/ */
if (len_remain >= 8) { if (len_remain >= 8) {
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
@ -4370,7 +4370,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) { if (sve_access_check(s)) {
int size = vec_full_reg_size(s); int size = vec_full_reg_size(s);
int off = vec_full_reg_offset(s, a->rd); int off = vec_full_reg_offset(s, a->rd);
gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); gen_sve_ldr(s, tcg_env, off, size, a->rn, a->imm * size);
} }
return true; return true;
} }
@ -4383,7 +4383,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) { if (sve_access_check(s)) {
int size = pred_full_reg_size(s); int size = pred_full_reg_size(s);
int off = pred_full_reg_offset(s, a->rd); int off = pred_full_reg_offset(s, a->rd);
gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); gen_sve_ldr(s, tcg_env, off, size, a->rn, a->imm * size);
} }
return true; return true;
} }
@ -4396,7 +4396,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) { if (sve_access_check(s)) {
int size = vec_full_reg_size(s); int size = vec_full_reg_size(s);
int off = vec_full_reg_offset(s, a->rd); int off = vec_full_reg_offset(s, a->rd);
gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); gen_sve_str(s, tcg_env, off, size, a->rn, a->imm * size);
} }
return true; return true;
} }
@ -4409,7 +4409,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) { if (sve_access_check(s)) {
int size = pred_full_reg_size(s); int size = pred_full_reg_size(s);
int off = pred_full_reg_offset(s, a->rd); int off = pred_full_reg_offset(s, a->rd);
gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); gen_sve_str(s, tcg_env, off, size, a->rn, a->imm * size);
} }
return true; return true;
} }
@ -4465,8 +4465,8 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
desc = simd_desc(vsz, vsz, zt | desc); desc = simd_desc(vsz, vsz, zt | desc);
t_pg = tcg_temp_new_ptr(); t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
fn(cpu_env, t_pg, addr, tcg_constant_i32(desc)); fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
} }
/* Indexed by [mte][be][dtype][nreg] */ /* Indexed by [mte][be][dtype][nreg] */
@ -4860,18 +4860,18 @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
#if HOST_BIG_ENDIAN #if HOST_BIG_ENDIAN
poff += 6; poff += 6;
#endif #endif
tcg_gen_ld16u_i64(tmp, cpu_env, poff); tcg_gen_ld16u_i64(tmp, tcg_env, poff);
poff = offsetof(CPUARMState, vfp.preg_tmp); poff = offsetof(CPUARMState, vfp.preg_tmp);
tcg_gen_st_i64(tmp, cpu_env, poff); tcg_gen_st_i64(tmp, tcg_env, poff);
} }
t_pg = tcg_temp_new_ptr(); t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_pg, cpu_env, poff); tcg_gen_addi_ptr(t_pg, tcg_env, poff);
gen_helper_gvec_mem *fn gen_helper_gvec_mem *fn
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt))); fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
/* Replicate that first quadword. */ /* Replicate that first quadword. */
if (vsz > 16) { if (vsz > 16) {
@ -4939,18 +4939,18 @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
#if HOST_BIG_ENDIAN #if HOST_BIG_ENDIAN
poff += 4; poff += 4;
#endif #endif
tcg_gen_ld32u_i64(tmp, cpu_env, poff); tcg_gen_ld32u_i64(tmp, tcg_env, poff);
poff = offsetof(CPUARMState, vfp.preg_tmp); poff = offsetof(CPUARMState, vfp.preg_tmp);
tcg_gen_st_i64(tmp, cpu_env, poff); tcg_gen_st_i64(tmp, tcg_env, poff);
} }
t_pg = tcg_temp_new_ptr(); t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_pg, cpu_env, poff); tcg_gen_addi_ptr(t_pg, tcg_env, poff);
gen_helper_gvec_mem *fn gen_helper_gvec_mem *fn
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt))); fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
/* /*
* Replicate that first octaword. * Replicate that first octaword.
@ -5027,7 +5027,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
*/ */
uint64_t psz_mask = MAKE_64BIT_MASK(0, psz * 8); uint64_t psz_mask = MAKE_64BIT_MASK(0, psz * 8);
temp = tcg_temp_new_i64(); temp = tcg_temp_new_i64();
tcg_gen_ld_i64(temp, cpu_env, pred_full_reg_offset(s, a->pg)); tcg_gen_ld_i64(temp, tcg_env, pred_full_reg_offset(s, a->pg));
tcg_gen_andi_i64(temp, temp, pred_esz_masks[esz] & psz_mask); tcg_gen_andi_i64(temp, temp, pred_esz_masks[esz] & psz_mask);
tcg_gen_brcondi_i64(TCG_COND_EQ, temp, 0, over); tcg_gen_brcondi_i64(TCG_COND_EQ, temp, 0, over);
} else { } else {
@ -5238,10 +5238,10 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
} }
desc = simd_desc(vsz, vsz, desc | scale); desc = simd_desc(vsz, vsz, desc | scale);
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm)); tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt)); tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
} }
/* Indexed by [mte][be][ff][xs][u][msz]. */ /* Indexed by [mte][be][ff][xs][u][msz]. */
@ -7197,7 +7197,7 @@ static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
{ {
return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzzw_s, return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzzw_s,
a->rd, a->rn, a->rm, a->ra, a->rd, a->rn, a->rm, a->ra,
(sel << 1) | sub, cpu_env); (sel << 1) | sub, tcg_env);
} }
TRANS_FEAT(FMLALB_zzzw, aa64_sve2, do_FMLAL_zzzw, a, false, false) TRANS_FEAT(FMLALB_zzzw, aa64_sve2, do_FMLAL_zzzw, a, false, false)
@ -7209,7 +7209,7 @@ static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool sel)
{ {
return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzxw_s, return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzxw_s,
a->rd, a->rn, a->rm, a->ra, a->rd, a->rn, a->rm, a->ra,
(a->index << 2) | (sel << 1) | sub, cpu_env); (a->index << 2) | (sel << 1) | sub, tcg_env);
} }
TRANS_FEAT(FMLALB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, false) TRANS_FEAT(FMLALB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, false)
@ -7289,7 +7289,7 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a)
/* Load the predicate word. */ /* Load the predicate word. */
tcg_gen_trunc_i64_ptr(ptr, didx); tcg_gen_trunc_i64_ptr(ptr, didx);
tcg_gen_add_ptr(ptr, ptr, cpu_env); tcg_gen_add_ptr(ptr, ptr, tcg_env);
tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm)); tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm));
/* Extract the predicate bit and replicate to MO_64. */ /* Extract the predicate bit and replicate to MO_64. */

56
target/arm/tcg/translate-vfp.c
View File

@ -30,22 +30,22 @@
static inline void vfp_load_reg64(TCGv_i64 var, int reg) static inline void vfp_load_reg64(TCGv_i64 var, int reg)
{ {
tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); tcg_gen_ld_i64(var, tcg_env, vfp_reg_offset(true, reg));
} }
static inline void vfp_store_reg64(TCGv_i64 var, int reg) static inline void vfp_store_reg64(TCGv_i64 var, int reg)
{ {
tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); tcg_gen_st_i64(var, tcg_env, vfp_reg_offset(true, reg));
} }
static inline void vfp_load_reg32(TCGv_i32 var, int reg) static inline void vfp_load_reg32(TCGv_i32 var, int reg)
{ {
tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); tcg_gen_ld_i32(var, tcg_env, vfp_reg_offset(false, reg));
} }
static inline void vfp_store_reg32(TCGv_i32 var, int reg) static inline void vfp_store_reg32(TCGv_i32 var, int reg)
{ {
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); tcg_gen_st_i32(var, tcg_env, vfp_reg_offset(false, reg));
} }
/* /*
@ -116,7 +116,7 @@ static void gen_preserve_fp_state(DisasContext *s, bool skip_context_update)
if (translator_io_start(&s->base)) { if (translator_io_start(&s->base)) {
s->base.is_jmp = DISAS_UPDATE_EXIT; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
gen_helper_v7m_preserve_fp_state(cpu_env); gen_helper_v7m_preserve_fp_state(tcg_env);
/* /*
* If the preserve_fp_state helper doesn't throw an exception * If the preserve_fp_state helper doesn't throw an exception
* then it will clear LSPACT; we don't need to repeat this for * then it will clear LSPACT; we don't need to repeat this for
@ -172,7 +172,7 @@ static void gen_update_fp_context(DisasContext *s)
uint32_t bits = R_V7M_CONTROL_FPCA_MASK; uint32_t bits = R_V7M_CONTROL_FPCA_MASK;
fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]);
gen_helper_vfp_set_fpscr(cpu_env, fpscr); gen_helper_vfp_set_fpscr(tcg_env, fpscr);
if (dc_isar_feature(aa32_mve, s)) { if (dc_isar_feature(aa32_mve, s)) {
store_cpu_field(tcg_constant_i32(0), v7m.vpr); store_cpu_field(tcg_constant_i32(0), v7m.vpr);
} }
@ -815,7 +815,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
if (s->current_el == 1) { if (s->current_el == 1) {
gen_set_condexec(s); gen_set_condexec(s);
gen_update_pc(s, 0); gen_update_pc(s, 0);
gen_helper_check_hcr_el2_trap(cpu_env, gen_helper_check_hcr_el2_trap(tcg_env,
tcg_constant_i32(a->rt), tcg_constant_i32(a->rt),
tcg_constant_i32(a->reg)); tcg_constant_i32(a->reg));
} }
@ -831,7 +831,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
} else { } else {
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env); gen_helper_vfp_get_fpscr(tmp, tcg_env);
} }
break; break;
default: default:
@ -855,7 +855,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
break; break;
case ARM_VFP_FPSCR: case ARM_VFP_FPSCR:
tmp = load_reg(s, a->rt); tmp = load_reg(s, a->rt);
gen_helper_vfp_set_fpscr(cpu_env, tmp); gen_helper_vfp_set_fpscr(tcg_env, tmp);
gen_lookup_tb(s); gen_lookup_tb(s);
break; break;
case ARM_VFP_FPEXC: case ARM_VFP_FPEXC:
@ -1169,7 +1169,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
* value is above, it is UNKNOWN whether the limit check * value is above, it is UNKNOWN whether the limit check
* triggers; we choose to trigger. * triggers; we choose to trigger.
*/ */
gen_helper_v8m_stackcheck(cpu_env, addr); gen_helper_v8m_stackcheck(tcg_env, addr);
} }
offset = 4; offset = 4;
@ -1252,7 +1252,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
* value is above, it is UNKNOWN whether the limit check * value is above, it is UNKNOWN whether the limit check
* triggers; we choose to trigger. * triggers; we choose to trigger.
*/ */
gen_helper_v8m_stackcheck(cpu_env, addr); gen_helper_v8m_stackcheck(tcg_env, addr);
} }
offset = 8; offset = 8;
@ -2419,17 +2419,17 @@ DO_VFP_2OP(VNEG, dp, gen_helper_vfp_negd, aa32_fpdp_v2)
static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm) static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm)
{ {
gen_helper_vfp_sqrth(vd, vm, cpu_env); gen_helper_vfp_sqrth(vd, vm, tcg_env);
} }
static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
{ {
gen_helper_vfp_sqrts(vd, vm, cpu_env); gen_helper_vfp_sqrts(vd, vm, tcg_env);
} }
static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
{ {
gen_helper_vfp_sqrtd(vd, vm, cpu_env); gen_helper_vfp_sqrtd(vd, vm, tcg_env);
} }
DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith) DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith)
@ -2464,9 +2464,9 @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a)
} }
if (a->e) { if (a->e) {
gen_helper_vfp_cmpeh(vd, vm, cpu_env); gen_helper_vfp_cmpeh(vd, vm, tcg_env);
} else { } else {
gen_helper_vfp_cmph(vd, vm, cpu_env); gen_helper_vfp_cmph(vd, vm, tcg_env);
} }
return true; return true;
} }
@ -2499,9 +2499,9 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
} }
if (a->e) { if (a->e) {
gen_helper_vfp_cmpes(vd, vm, cpu_env); gen_helper_vfp_cmpes(vd, vm, tcg_env);
} else { } else {
gen_helper_vfp_cmps(vd, vm, cpu_env); gen_helper_vfp_cmps(vd, vm, tcg_env);
} }
return true; return true;
} }
@ -2539,9 +2539,9 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
} }
if (a->e) { if (a->e) {
gen_helper_vfp_cmped(vd, vm, cpu_env); gen_helper_vfp_cmped(vd, vm, tcg_env);
} else { } else {
gen_helper_vfp_cmpd(vd, vm, cpu_env); gen_helper_vfp_cmpd(vd, vm, tcg_env);
} }
return true; return true;
} }
@ -2564,7 +2564,7 @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
ahp_mode = get_ahp_flag(); ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
/* The T bit tells us if we want the low or high 16 bits of Vm */ /* The T bit tells us if we want the low or high 16 bits of Vm */
tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); tcg_gen_ld16u_i32(tmp, tcg_env, vfp_f16_offset(a->vm, a->t));
gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
vfp_store_reg32(tmp, a->vd); vfp_store_reg32(tmp, a->vd);
return true; return true;
@ -2598,7 +2598,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
ahp_mode = get_ahp_flag(); ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
/* The T bit tells us if we want the low or high 16 bits of Vm */ /* The T bit tells us if we want the low or high 16 bits of Vm */
tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); tcg_gen_ld16u_i32(tmp, tcg_env, vfp_f16_offset(a->vm, a->t));
vd = tcg_temp_new_i64(); vd = tcg_temp_new_i64();
gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
vfp_store_reg64(vd, a->vd); vfp_store_reg64(vd, a->vd);
@ -2623,7 +2623,7 @@ static bool trans_VCVT_b16_f32(DisasContext *s, arg_VCVT_b16_f32 *a)
vfp_load_reg32(tmp, a->vm); vfp_load_reg32(tmp, a->vm);
gen_helper_bfcvt(tmp, tmp, fpst); gen_helper_bfcvt(tmp, tmp, fpst);
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t));
return true; return true;
} }
@ -2647,7 +2647,7 @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
vfp_load_reg32(tmp, a->vm); vfp_load_reg32(tmp, a->vm);
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t));
return true; return true;
} }
@ -2682,7 +2682,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
vfp_load_reg64(vm, a->vm); vfp_load_reg64(vm, a->vm);
gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t));
return true; return true;
} }
@ -2932,7 +2932,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
vm = tcg_temp_new_i32(); vm = tcg_temp_new_i32();
vd = tcg_temp_new_i64(); vd = tcg_temp_new_i64();
vfp_load_reg32(vm, a->vm); vfp_load_reg32(vm, a->vm);
gen_helper_vfp_fcvtds(vd, vm, cpu_env); gen_helper_vfp_fcvtds(vd, vm, tcg_env);
vfp_store_reg64(vd, a->vd); vfp_store_reg64(vd, a->vd);
return true; return true;
} }
@ -2958,7 +2958,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
vd = tcg_temp_new_i32(); vd = tcg_temp_new_i32();
vm = tcg_temp_new_i64(); vm = tcg_temp_new_i64();
vfp_load_reg64(vm, a->vm); vfp_load_reg64(vm, a->vm);
gen_helper_vfp_fcvtsd(vd, vm, cpu_env); gen_helper_vfp_fcvtsd(vd, vm, tcg_env);
vfp_store_reg32(vd, a->vd); vfp_store_reg32(vd, a->vd);
return true; return true;
} }
@ -3076,7 +3076,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
vm = tcg_temp_new_i64(); vm = tcg_temp_new_i64();
vd = tcg_temp_new_i32(); vd = tcg_temp_new_i32();
vfp_load_reg64(vm, a->vm); vfp_load_reg64(vm, a->vm);
gen_helper_vjcvt(vd, vm, cpu_env); gen_helper_vjcvt(vd, vm, tcg_env);
vfp_store_reg32(vd, a->vd); vfp_store_reg32(vd, a->vd);
return true; return true;
} }

228
target/arm/tcg/translate.c
View File

@ -63,18 +63,18 @@ void arm_translate_init(void)
int i; int i;
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env, cpu_R[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUARMState, regs[i]), offsetof(CPUARMState, regs[i]),
regnames[i]); regnames[i]);
} }
cpu_CF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, CF), "CF"); cpu_CF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, CF), "CF");
cpu_NF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, NF), "NF"); cpu_NF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, NF), "NF");
cpu_VF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, VF), "VF"); cpu_VF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, VF), "VF");
cpu_ZF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, ZF), "ZF"); cpu_ZF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, ZF), "ZF");
cpu_exclusive_addr = tcg_global_mem_new_i64(cpu_env, cpu_exclusive_addr = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUARMState, exclusive_addr), "exclusive_addr"); offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
cpu_exclusive_val = tcg_global_mem_new_i64(cpu_env, cpu_exclusive_val = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUARMState, exclusive_val), "exclusive_val"); offsetof(CPUARMState, exclusive_val), "exclusive_val");
a64_translate_init(); a64_translate_init();
@ -179,10 +179,10 @@ void store_cpu_offset(TCGv_i32 var, int offset, int size)
{ {
switch (size) { switch (size) {
case 1: case 1:
tcg_gen_st8_i32(var, cpu_env, offset); tcg_gen_st8_i32(var, tcg_env, offset);
break; break;
case 4: case 4:
tcg_gen_st_i32(var, cpu_env, offset); tcg_gen_st_i32(var, tcg_env, offset);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -329,7 +329,7 @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var)
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (s->v8m_stackcheck) { if (s->v8m_stackcheck) {
gen_helper_v8m_stackcheck(cpu_env, var); gen_helper_v8m_stackcheck(tcg_env, var);
} }
#endif #endif
store_reg(s, 13, var); store_reg(s, 13, var);
@ -346,7 +346,7 @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var)
void gen_set_cpsr(TCGv_i32 var, uint32_t mask) void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
{ {
gen_helper_cpsr_write(cpu_env, var, tcg_constant_i32(mask)); gen_helper_cpsr_write(tcg_env, var, tcg_constant_i32(mask));
} }
static void gen_rebuild_hflags(DisasContext *s, bool new_el) static void gen_rebuild_hflags(DisasContext *s, bool new_el)
@ -355,16 +355,16 @@ static void gen_rebuild_hflags(DisasContext *s, bool new_el)
if (new_el) { if (new_el) {
if (m_profile) { if (m_profile) {
gen_helper_rebuild_hflags_m32_newel(cpu_env); gen_helper_rebuild_hflags_m32_newel(tcg_env);
} else { } else {
gen_helper_rebuild_hflags_a32_newel(cpu_env); gen_helper_rebuild_hflags_a32_newel(tcg_env);
} }
} else { } else {
TCGv_i32 tcg_el = tcg_constant_i32(s->current_el); TCGv_i32 tcg_el = tcg_constant_i32(s->current_el);
if (m_profile) { if (m_profile) {
gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); gen_helper_rebuild_hflags_m32(tcg_env, tcg_el);
} else { } else {
gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); gen_helper_rebuild_hflags_a32(tcg_env, tcg_el);
} }
} }
} }
@ -372,7 +372,7 @@ static void gen_rebuild_hflags(DisasContext *s, bool new_el)
static void gen_exception_internal(int excp) static void gen_exception_internal(int excp)
{ {
assert(excp_is_internal(excp)); assert(excp_is_internal(excp));
gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); gen_helper_exception_internal(tcg_env, tcg_constant_i32(excp));
} }
static void gen_singlestep_exception(DisasContext *s) static void gen_singlestep_exception(DisasContext *s)
@ -617,10 +617,10 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, int shiftop,
{ {
if (flags) { if (flags) {
switch (shiftop) { switch (shiftop) {
case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break; case 0: gen_helper_shl_cc(var, tcg_env, var, shift); break;
case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break; case 1: gen_helper_shr_cc(var, tcg_env, var, shift); break;
case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break; case 2: gen_helper_sar_cc(var, tcg_env, var, shift); break;
case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break; case 3: gen_helper_ror_cc(var, tcg_env, var, shift); break;
} }
} else { } else {
switch (shiftop) { switch (shiftop) {
@ -849,7 +849,7 @@ static inline void gen_bxns(DisasContext *s, int rm)
* is correct in the non-UNPREDICTABLE cases, and we can choose * is correct in the non-UNPREDICTABLE cases, and we can choose
* "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise. * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise.
*/ */
gen_helper_v7m_bxns(cpu_env, var); gen_helper_v7m_bxns(tcg_env, var);
s->base.is_jmp = DISAS_EXIT; s->base.is_jmp = DISAS_EXIT;
} }
@ -862,7 +862,7 @@ static inline void gen_blxns(DisasContext *s, int rm)
* The blxns helper may throw an exception. * The blxns helper may throw an exception.
*/ */
gen_update_pc(s, curr_insn_len(s)); gen_update_pc(s, curr_insn_len(s));
gen_helper_v7m_blxns(cpu_env, var); gen_helper_v7m_blxns(tcg_env, var);
s->base.is_jmp = DISAS_EXIT; s->base.is_jmp = DISAS_EXIT;
} }
@ -1024,7 +1024,7 @@ static inline void gen_hvc(DisasContext *s, int imm16)
* the insn really executes). * the insn really executes).
*/ */
gen_update_pc(s, 0); gen_update_pc(s, 0);
gen_helper_pre_hvc(cpu_env); gen_helper_pre_hvc(tcg_env);
/* Otherwise we will treat this as a real exception which /* Otherwise we will treat this as a real exception which
* happens after execution of the insn. (The distinction matters * happens after execution of the insn. (The distinction matters
* for the PC value reported to the exception handler and also * for the PC value reported to the exception handler and also
@ -1041,7 +1041,7 @@ static inline void gen_smc(DisasContext *s)
* the insn executes. * the insn executes.
*/ */
gen_update_pc(s, 0); gen_update_pc(s, 0);
gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc())); gen_helper_pre_smc(tcg_env, tcg_constant_i32(syn_aa32_smc()));
gen_update_pc(s, curr_insn_len(s)); gen_update_pc(s, curr_insn_len(s));
s->base.is_jmp = DISAS_SMC; s->base.is_jmp = DISAS_SMC;
} }
@ -1056,7 +1056,7 @@ static void gen_exception_internal_insn(DisasContext *s, int excp)
static void gen_exception_el_v(int excp, uint32_t syndrome, TCGv_i32 tcg_el) static void gen_exception_el_v(int excp, uint32_t syndrome, TCGv_i32 tcg_el)
{ {
gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), gen_helper_exception_with_syndrome_el(tcg_env, tcg_constant_i32(excp),
tcg_constant_i32(syndrome), tcg_el); tcg_constant_i32(syndrome), tcg_el);
} }
@ -1067,7 +1067,7 @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el)
static void gen_exception(int excp, uint32_t syndrome) static void gen_exception(int excp, uint32_t syndrome)
{ {
gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), gen_helper_exception_with_syndrome(tcg_env, tcg_constant_i32(excp),
tcg_constant_i32(syndrome)); tcg_constant_i32(syndrome));
} }
@ -1108,7 +1108,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
{ {
gen_set_condexec(s); gen_set_condexec(s);
gen_update_pc(s, 0); gen_update_pc(s, 0);
gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn)); gen_helper_exception_bkpt_insn(tcg_env, tcg_constant_i32(syn));
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
@ -1192,20 +1192,20 @@ void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
switch (memop) { switch (memop) {
case MO_SB: case MO_SB:
tcg_gen_ld8s_i32(dest, cpu_env, off); tcg_gen_ld8s_i32(dest, tcg_env, off);
break; break;
case MO_UB: case MO_UB:
tcg_gen_ld8u_i32(dest, cpu_env, off); tcg_gen_ld8u_i32(dest, tcg_env, off);
break; break;
case MO_SW: case MO_SW:
tcg_gen_ld16s_i32(dest, cpu_env, off); tcg_gen_ld16s_i32(dest, tcg_env, off);
break; break;
case MO_UW: case MO_UW:
tcg_gen_ld16u_i32(dest, cpu_env, off); tcg_gen_ld16u_i32(dest, tcg_env, off);
break; break;
case MO_UL: case MO_UL:
case MO_SL: case MO_SL:
tcg_gen_ld_i32(dest, cpu_env, off); tcg_gen_ld_i32(dest, tcg_env, off);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -1218,13 +1218,13 @@ void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
switch (memop) { switch (memop) {
case MO_SL: case MO_SL:
tcg_gen_ld32s_i64(dest, cpu_env, off); tcg_gen_ld32s_i64(dest, tcg_env, off);
break; break;
case MO_UL: case MO_UL:
tcg_gen_ld32u_i64(dest, cpu_env, off); tcg_gen_ld32u_i64(dest, tcg_env, off);
break; break;
case MO_UQ: case MO_UQ:
tcg_gen_ld_i64(dest, cpu_env, off); tcg_gen_ld_i64(dest, tcg_env, off);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -1237,13 +1237,13 @@ void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
switch (memop) { switch (memop) {
case MO_8: case MO_8:
tcg_gen_st8_i32(src, cpu_env, off); tcg_gen_st8_i32(src, tcg_env, off);
break; break;
case MO_16: case MO_16:
tcg_gen_st16_i32(src, cpu_env, off); tcg_gen_st16_i32(src, tcg_env, off);
break; break;
case MO_32: case MO_32:
tcg_gen_st_i32(src, cpu_env, off); tcg_gen_st_i32(src, tcg_env, off);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -1256,10 +1256,10 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
switch (memop) { switch (memop) {
case MO_32: case MO_32:
tcg_gen_st32_i64(src, cpu_env, off); tcg_gen_st32_i64(src, tcg_env, off);
break; break;
case MO_64: case MO_64:
tcg_gen_st_i64(src, cpu_env, off); tcg_gen_st_i64(src, tcg_env, off);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -1270,24 +1270,24 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
{ {
tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); tcg_gen_ld_i64(var, tcg_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
} }
static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
{ {
tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); tcg_gen_st_i64(var, tcg_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
} }
static inline TCGv_i32 iwmmxt_load_creg(int reg) static inline TCGv_i32 iwmmxt_load_creg(int reg)
{ {
TCGv_i32 var = tcg_temp_new_i32(); TCGv_i32 var = tcg_temp_new_i32();
tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); tcg_gen_ld_i32(var, tcg_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
return var; return var;
} }
static inline void iwmmxt_store_creg(int reg, TCGv_i32 var) static inline void iwmmxt_store_creg(int reg, TCGv_i32 var)
{ {
tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); tcg_gen_st_i32(var, tcg_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
} }
static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
@ -1329,7 +1329,7 @@ static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
{ \ { \
iwmmxt_load_reg(cpu_V1, rn); \ iwmmxt_load_reg(cpu_V1, rn); \
gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \ gen_helper_iwmmxt_##name(cpu_M0, tcg_env, cpu_M0, cpu_V1); \
} }
#define IWMMXT_OP_ENV_SIZE(name) \ #define IWMMXT_OP_ENV_SIZE(name) \
@ -1340,7 +1340,7 @@ IWMMXT_OP_ENV(name##l)
#define IWMMXT_OP_ENV1(name) \ #define IWMMXT_OP_ENV1(name) \
static inline void gen_op_iwmmxt_##name##_M0(void) \ static inline void gen_op_iwmmxt_##name##_M0(void) \
{ \ { \
gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \ gen_helper_iwmmxt_##name(cpu_M0, tcg_env, cpu_M0); \
} }
IWMMXT_OP(maddsq) IWMMXT_OP(maddsq)
@ -2113,13 +2113,13 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
} }
switch ((insn >> 22) & 3) { switch ((insn >> 22) & 3) {
case 1: case 1:
gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_srlw(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
case 2: case 2:
gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_srll(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
case 3: case 3:
gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_srlq(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
} }
gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_movq_wRn_M0(wrd);
@ -2139,13 +2139,13 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
} }
switch ((insn >> 22) & 3) { switch ((insn >> 22) & 3) {
case 1: case 1:
gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_sraw(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
case 2: case 2:
gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_sral(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
case 3: case 3:
gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_sraq(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
} }
gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_movq_wRn_M0(wrd);
@ -2165,13 +2165,13 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
} }
switch ((insn >> 22) & 3) { switch ((insn >> 22) & 3) {
case 1: case 1:
gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_sllw(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
case 2: case 2:
gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_slll(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
case 3: case 3:
gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_sllq(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
} }
gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_movq_wRn_M0(wrd);
@ -2191,19 +2191,19 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
if (gen_iwmmxt_shift(insn, 0xf, tmp)) { if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
return 1; return 1;
} }
gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_rorw(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
case 2: case 2:
if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
return 1; return 1;
} }
gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_rorl(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
case 3: case 3:
if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
return 1; return 1;
} }
gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_rorq(cpu_M0, tcg_env, cpu_M0, tmp);
break; break;
} }
gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_movq_wRn_M0(wrd);
@ -2335,7 +2335,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
rd0 = (insn >> 16) & 0xf; rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0); gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp); gen_helper_iwmmxt_shufh(cpu_M0, tcg_env, cpu_M0, tmp);
gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup(); gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup(); gen_op_iwmmxt_set_cup();
@ -2857,7 +2857,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
gen_set_condexec(s); gen_set_condexec(s);
gen_update_pc(s, 0); gen_update_pc(s, 0);
tcg_reg = load_reg(s, rn); tcg_reg = load_reg(s, rn);
gen_helper_msr_banked(cpu_env, tcg_reg, gen_helper_msr_banked(tcg_env, tcg_reg,
tcg_constant_i32(tgtmode), tcg_constant_i32(tgtmode),
tcg_constant_i32(regno)); tcg_constant_i32(regno));
s->base.is_jmp = DISAS_UPDATE_EXIT; s->base.is_jmp = DISAS_UPDATE_EXIT;
@ -2876,7 +2876,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
gen_set_condexec(s); gen_set_condexec(s);
gen_update_pc(s, 0); gen_update_pc(s, 0);
tcg_reg = tcg_temp_new_i32(); tcg_reg = tcg_temp_new_i32();
gen_helper_mrs_banked(tcg_reg, cpu_env, gen_helper_mrs_banked(tcg_reg, tcg_env,
tcg_constant_i32(tgtmode), tcg_constant_i32(tgtmode),
tcg_constant_i32(regno)); tcg_constant_i32(regno));
store_reg(s, rn, tcg_reg); store_reg(s, rn, tcg_reg);
@ -2901,7 +2901,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr)
* be called after storing the new PC. * be called after storing the new PC.
*/ */
translator_io_start(&s->base); translator_io_start(&s->base);
gen_helper_cpsr_write_eret(cpu_env, cpsr); gen_helper_cpsr_write_eret(tcg_env, cpsr);
/* Must exit loop to check un-masked IRQs */ /* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT; s->base.is_jmp = DISAS_EXIT;
} }
@ -2918,7 +2918,7 @@ static void gen_gvec_fn3_qc(uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs,
{ {
TCGv_ptr qc_ptr = tcg_temp_new_ptr(); TCGv_ptr qc_ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc)); tcg_gen_addi_ptr(qc_ptr, tcg_env, offsetof(CPUARMState, vfp.qc));
tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, qc_ptr, tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, qc_ptr,
opr_sz, max_sz, 0, fn); opr_sz, max_sz, 0, fn);
} }
@ -4605,11 +4605,11 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
case 0: case 0:
if (arm_dc_feature(s, ARM_FEATURE_AARCH64) if (arm_dc_feature(s, ARM_FEATURE_AARCH64)
&& dc_isar_feature(aa64_tidcp1, s)) { && dc_isar_feature(aa64_tidcp1, s)) {
gen_helper_tidcp_el0(cpu_env, tcg_constant_i32(syndrome)); gen_helper_tidcp_el0(tcg_env, tcg_constant_i32(syndrome));
} }
break; break;
case 1: case 1:
gen_helper_tidcp_el1(cpu_env, tcg_constant_i32(syndrome)); gen_helper_tidcp_el1(tcg_env, tcg_constant_i32(syndrome));
break; break;
} }
} }
@ -4654,7 +4654,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
gen_set_condexec(s); gen_set_condexec(s);
gen_update_pc(s, 0); gen_update_pc(s, 0);
tcg_ri = tcg_temp_new_ptr(); tcg_ri = tcg_temp_new_ptr();
gen_helper_access_check_cp_reg(tcg_ri, cpu_env, gen_helper_access_check_cp_reg(tcg_ri, tcg_env,
tcg_constant_i32(key), tcg_constant_i32(key),
tcg_constant_i32(syndrome), tcg_constant_i32(syndrome),
tcg_constant_i32(isread)); tcg_constant_i32(isread));
@ -4702,10 +4702,10 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
tcg_ri = gen_lookup_cp_reg(key); tcg_ri = gen_lookup_cp_reg(key);
} }
tmp64 = tcg_temp_new_i64(); tmp64 = tcg_temp_new_i64();
gen_helper_get_cp_reg64(tmp64, cpu_env, tcg_ri); gen_helper_get_cp_reg64(tmp64, tcg_env, tcg_ri);
} else { } else {
tmp64 = tcg_temp_new_i64(); tmp64 = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset); tcg_gen_ld_i64(tmp64, tcg_env, ri->fieldoffset);
} }
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(tmp, tmp64); tcg_gen_extrl_i64_i32(tmp, tmp64);
@ -4722,7 +4722,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
tcg_ri = gen_lookup_cp_reg(key); tcg_ri = gen_lookup_cp_reg(key);
} }
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
gen_helper_get_cp_reg(tmp, cpu_env, tcg_ri); gen_helper_get_cp_reg(tmp, tcg_env, tcg_ri);
} else { } else {
tmp = load_cpu_offset(ri->fieldoffset); tmp = load_cpu_offset(ri->fieldoffset);
} }
@ -4752,9 +4752,9 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
if (!tcg_ri) { if (!tcg_ri) {
tcg_ri = gen_lookup_cp_reg(key); tcg_ri = gen_lookup_cp_reg(key);
} }
gen_helper_set_cp_reg64(cpu_env, tcg_ri, tmp64); gen_helper_set_cp_reg64(tcg_env, tcg_ri, tmp64);
} else { } else {
tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset); tcg_gen_st_i64(tmp64, tcg_env, ri->fieldoffset);
} }
} else { } else {
TCGv_i32 tmp = load_reg(s, rt); TCGv_i32 tmp = load_reg(s, rt);
@ -4762,7 +4762,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
if (!tcg_ri) { if (!tcg_ri) {
tcg_ri = gen_lookup_cp_reg(key); tcg_ri = gen_lookup_cp_reg(key);
} }
gen_helper_set_cp_reg(cpu_env, tcg_ri, tmp); gen_helper_set_cp_reg(tcg_env, tcg_ri, tmp);
} else { } else {
store_cpu_offset(tmp, ri->fieldoffset, 4); store_cpu_offset(tmp, ri->fieldoffset, 4);
} }
@ -5028,7 +5028,7 @@ static void gen_srs(DisasContext *s,
/* get_r13_banked() will raise an exception if called from System mode */ /* get_r13_banked() will raise an exception if called from System mode */
gen_set_condexec(s); gen_set_condexec(s);
gen_update_pc(s, 0); gen_update_pc(s, 0);
gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode)); gen_helper_get_r13_banked(addr, tcg_env, tcg_constant_i32(mode));
switch (amode) { switch (amode) {
case 0: /* DA */ case 0: /* DA */
offset = -4; offset = -4;
@ -5069,7 +5069,7 @@ static void gen_srs(DisasContext *s,
g_assert_not_reached(); g_assert_not_reached();
} }
tcg_gen_addi_i32(addr, addr, offset); tcg_gen_addi_i32(addr, addr, offset);
gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr); gen_helper_set_r13_banked(tcg_env, tcg_constant_i32(mode), addr);
} }
s->base.is_jmp = DISAS_UPDATE_EXIT; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
@ -5618,7 +5618,7 @@ static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
{ {
gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift)); gen_helper_mve_sqshll(r, tcg_env, n, tcg_constant_i32(shift));
} }
static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
@ -5628,7 +5628,7 @@ static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
{ {
gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift)); gen_helper_mve_uqshll(r, tcg_env, n, tcg_constant_i32(shift));
} }
static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
@ -5674,7 +5674,7 @@ static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
tcg_gen_concat_i32_i64(rda, rdalo, rdahi); tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
/* The helper takes care of the sign-extension of the low 8 bits of Rm */ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
fn(rda, cpu_env, rda, cpu_R[a->rm]); fn(rda, tcg_env, rda, cpu_R[a->rm]);
tcg_gen_extrl_i64_i32(rdalo, rda); tcg_gen_extrl_i64_i32(rdalo, rda);
tcg_gen_extrh_i64_i32(rdahi, rda); tcg_gen_extrh_i64_i32(rdahi, rda);
@ -5748,7 +5748,7 @@ static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
{ {
gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift)); gen_helper_mve_sqshl(r, tcg_env, n, tcg_constant_i32(shift));
} }
static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
@ -5758,7 +5758,7 @@ static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
{ {
gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift)); gen_helper_mve_uqshl(r, tcg_env, n, tcg_constant_i32(shift));
} }
static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
@ -5782,7 +5782,7 @@ static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
} }
/* The helper takes care of the sign-extension of the low 8 bits of Rm */ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]); fn(cpu_R[a->rda], tcg_env, cpu_R[a->rda], cpu_R[a->rm]);
return true; return true;
} }
@ -5928,12 +5928,12 @@ static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub)
t0 = load_reg(s, a->rm); t0 = load_reg(s, a->rm);
t1 = load_reg(s, a->rn); t1 = load_reg(s, a->rn);
if (doub) { if (doub) {
gen_helper_add_saturate(t1, cpu_env, t1, t1); gen_helper_add_saturate(t1, tcg_env, t1, t1);
} }
if (add) { if (add) {
gen_helper_add_saturate(t0, cpu_env, t0, t1); gen_helper_add_saturate(t0, tcg_env, t0, t1);
} else { } else {
gen_helper_sub_saturate(t0, cpu_env, t0, t1); gen_helper_sub_saturate(t0, tcg_env, t0, t1);
} }
store_reg(s, a->rd, t0); store_reg(s, a->rd, t0);
return true; return true;
@ -5977,7 +5977,7 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a,
break; break;
case 1: case 1:
t1 = load_reg(s, a->ra); t1 = load_reg(s, a->ra);
gen_helper_add_setq(t0, cpu_env, t0, t1); gen_helper_add_setq(t0, tcg_env, t0, t1);
store_reg(s, a->rd, t0); store_reg(s, a->rd, t0);
break; break;
case 2: case 2:
@ -6041,7 +6041,7 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt)
tcg_gen_muls2_i32(t0, t1, t0, t1); tcg_gen_muls2_i32(t0, t1, t0, t1);
if (add) { if (add) {
t0 = load_reg(s, a->ra); t0 = load_reg(s, a->ra);
gen_helper_add_setq(t1, cpu_env, t1, t0); gen_helper_add_setq(t1, tcg_env, t1, t0);
} }
store_reg(s, a->rd, t1); store_reg(s, a->rd, t1);
return true; return true;
@ -6120,7 +6120,7 @@ static bool trans_ESB(DisasContext *s, arg_ESB *a)
* Test for EL2 present, and defer test for SEL2 to runtime. * Test for EL2 present, and defer test for SEL2 to runtime.
*/ */
if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
gen_helper_vesb(cpu_env); gen_helper_vesb(tcg_env);
} }
} }
return true; return true;
@ -6228,7 +6228,7 @@ static bool trans_MRS_reg(DisasContext *s, arg_MRS_reg *a)
tmp = load_cpu_field(spsr); tmp = load_cpu_field(spsr);
} else { } else {
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
gen_helper_cpsr_read(tmp, cpu_env); gen_helper_cpsr_read(tmp, tcg_env);
} }
store_reg(s, a->rd, tmp); store_reg(s, a->rd, tmp);
return true; return true;
@ -6257,7 +6257,7 @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
return false; return false;
} }
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
gen_helper_v7m_mrs(tmp, cpu_env, tcg_constant_i32(a->sysm)); gen_helper_v7m_mrs(tmp, tcg_env, tcg_constant_i32(a->sysm));
store_reg(s, a->rd, tmp); store_reg(s, a->rd, tmp);
return true; return true;
} }
@ -6271,7 +6271,7 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
} }
addr = tcg_constant_i32((a->mask << 10) | a->sysm); addr = tcg_constant_i32((a->mask << 10) | a->sysm);
reg = load_reg(s, a->rn); reg = load_reg(s, a->rn);
gen_helper_v7m_msr(cpu_env, addr, reg); gen_helper_v7m_msr(tcg_env, addr, reg);
/* If we wrote to CONTROL, the EL might have changed */ /* If we wrote to CONTROL, the EL might have changed */
gen_rebuild_hflags(s, true); gen_rebuild_hflags(s, true);
gen_lookup_tb(s); gen_lookup_tb(s);
@ -6302,7 +6302,7 @@ static bool trans_BXJ(DisasContext *s, arg_BXJ *a)
if (!arm_dc_feature(s, ARM_FEATURE_V8) && if (!arm_dc_feature(s, ARM_FEATURE_V8) &&
arm_dc_feature(s, ARM_FEATURE_EL2) && arm_dc_feature(s, ARM_FEATURE_EL2) &&
s->current_el < 2 && s->ns) { s->current_el < 2 && s->ns) {
gen_helper_check_bxj_trap(cpu_env, tcg_constant_i32(a->rm)); gen_helper_check_bxj_trap(tcg_env, tcg_constant_i32(a->rm));
} }
/* Trivial implementation equivalent to bx. */ /* Trivial implementation equivalent to bx. */
gen_bx(s, load_reg(s, a->rm)); gen_bx(s, load_reg(s, a->rm));
@ -6480,7 +6480,7 @@ static bool trans_TT(DisasContext *s, arg_TT *a)
addr = load_reg(s, a->rn); addr = load_reg(s, a->rn);
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
gen_helper_v7m_tt(tmp, cpu_env, addr, tcg_constant_i32((a->A << 1) | a->T)); gen_helper_v7m_tt(tmp, tcg_env, addr, tcg_constant_i32((a->A << 1) | a->T));
store_reg(s, a->rd, tmp); store_reg(s, a->rd, tmp);
return true; return true;
} }
@ -6510,7 +6510,7 @@ static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a)
TCGv_i32 addr = load_reg(s, a->rn); TCGv_i32 addr = load_reg(s, a->rn);
if (s->v8m_stackcheck && a->rn == 13 && a->w) { if (s->v8m_stackcheck && a->rn == 13 && a->w) {
gen_helper_v8m_stackcheck(cpu_env, addr); gen_helper_v8m_stackcheck(tcg_env, addr);
} }
if (a->p) { if (a->p) {
@ -6665,9 +6665,9 @@ static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a)
if (!a->u) { if (!a->u) {
TCGv_i32 newsp = tcg_temp_new_i32(); TCGv_i32 newsp = tcg_temp_new_i32();
tcg_gen_addi_i32(newsp, cpu_R[13], ofs); tcg_gen_addi_i32(newsp, cpu_R[13], ofs);
gen_helper_v8m_stackcheck(cpu_env, newsp); gen_helper_v8m_stackcheck(tcg_env, newsp);
} else { } else {
gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]); gen_helper_v8m_stackcheck(tcg_env, cpu_R[13]);
} }
} }
@ -7319,7 +7319,7 @@ static bool op_par_addsub_ge(DisasContext *s, arg_rrr *a,
t1 = load_reg(s, a->rm); t1 = load_reg(s, a->rm);
ge = tcg_temp_new_ptr(); ge = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE)); tcg_gen_addi_ptr(ge, tcg_env, offsetof(CPUARMState, GE));
gen(t0, t0, t1, ge); gen(t0, t0, t1, ge);
store_reg(s, a->rd, t0); store_reg(s, a->rd, t0);
@ -7433,7 +7433,7 @@ static bool op_sat(DisasContext *s, arg_sat *a,
tcg_gen_shli_i32(tmp, tmp, shift); tcg_gen_shli_i32(tmp, tmp, shift);
} }
gen(tmp, cpu_env, tmp, tcg_constant_i32(a->satimm)); gen(tmp, tcg_env, tmp, tcg_constant_i32(a->satimm));
store_reg(s, a->rd, tmp); store_reg(s, a->rd, tmp);
return true; return true;
@ -7540,7 +7540,7 @@ static bool trans_SEL(DisasContext *s, arg_rrr *a)
t1 = load_reg(s, a->rn); t1 = load_reg(s, a->rn);
t2 = load_reg(s, a->rm); t2 = load_reg(s, a->rm);
t3 = tcg_temp_new_i32(); t3 = tcg_temp_new_i32();
tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE)); tcg_gen_ld_i32(t3, tcg_env, offsetof(CPUARMState, GE));
gen_helper_sel_flags(t1, t3, t1, t2); gen_helper_sel_flags(t1, t3, t1, t2);
store_reg(s, a->rd, t1); store_reg(s, a->rd, t1);
return true; return true;
@ -7618,11 +7618,11 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
if (a->ra != 15) { if (a->ra != 15) {
t2 = load_reg(s, a->ra); t2 = load_reg(s, a->ra);
gen_helper_add_setq(t1, cpu_env, t1, t2); gen_helper_add_setq(t1, tcg_env, t1, t2);
} }
} else if (a->ra == 15) { } else if (a->ra == 15) {
/* Single saturation-checking addition */ /* Single saturation-checking addition */
gen_helper_add_setq(t1, cpu_env, t1, t2); gen_helper_add_setq(t1, tcg_env, t1, t2);
} else { } else {
/* /*
* We need to add the products and Ra together and then * We need to add the products and Ra together and then
@ -7804,9 +7804,9 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool u)
t1 = load_reg(s, a->rn); t1 = load_reg(s, a->rn);
t2 = load_reg(s, a->rm); t2 = load_reg(s, a->rm);
if (u) { if (u) {
gen_helper_udiv(t1, cpu_env, t1, t2); gen_helper_udiv(t1, tcg_env, t1, t2);
} else { } else {
gen_helper_sdiv(t1, cpu_env, t1, t2); gen_helper_sdiv(t1, tcg_env, t1, t2);
} }
store_reg(s, a->rd, t1); store_reg(s, a->rd, t1);
return true; return true;
@ -7855,7 +7855,7 @@ static TCGv_i32 op_addr_block_pre(DisasContext *s, arg_ldst_block *a, int n)
* either the original SP (if incrementing) or our * either the original SP (if incrementing) or our
* final SP (if decrementing), so that's what we check. * final SP (if decrementing), so that's what we check.
*/ */
gen_helper_v8m_stackcheck(cpu_env, addr); gen_helper_v8m_stackcheck(tcg_env, addr);
} }
return addr; return addr;
@ -7916,7 +7916,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
if (user && i != 15) { if (user && i != 15) {
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
gen_helper_get_user_reg(tmp, cpu_env, tcg_constant_i32(i)); gen_helper_get_user_reg(tmp, tcg_env, tcg_constant_i32(i));
} else { } else {
tmp = load_reg(s, i); tmp = load_reg(s, i);
} }
@ -7999,7 +7999,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
if (user) { if (user) {
gen_helper_set_user_reg(cpu_env, tcg_constant_i32(i), tmp); gen_helper_set_user_reg(tcg_env, tcg_constant_i32(i), tmp);
} else if (i == a->rn) { } else if (i == a->rn) {
loaded_var = tmp; loaded_var = tmp;
loaded_base = true; loaded_base = true;
@ -8026,7 +8026,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
/* Restore CPSR from SPSR. */ /* Restore CPSR from SPSR. */
tmp = load_cpu_field(spsr); tmp = load_cpu_field(spsr);
translator_io_start(&s->base); translator_io_start(&s->base);
gen_helper_cpsr_write_eret(cpu_env, tmp); gen_helper_cpsr_write_eret(tcg_env, tmp);
/* Must exit loop to check un-masked IRQs */ /* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT; s->base.is_jmp = DISAS_EXIT;
} }
@ -8100,7 +8100,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
* Clear APSR (by calling the MSR helper with the same argument * Clear APSR (by calling the MSR helper with the same argument
* as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0) * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
*/ */
gen_helper_v7m_msr(cpu_env, tcg_constant_i32(0xc00), zero); gen_helper_v7m_msr(tcg_env, tcg_constant_i32(0xc00), zero);
} }
clear_eci_state(s); clear_eci_state(s);
return true; return true;
@ -8487,7 +8487,7 @@ static bool trans_VCTP(DisasContext *s, arg_VCTP *a)
tcg_gen_movcond_i32(TCG_COND_LEU, masklen, tcg_gen_movcond_i32(TCG_COND_LEU, masklen,
masklen, tcg_constant_i32(1 << (4 - a->size)), masklen, tcg_constant_i32(1 << (4 - a->size)),
rn_shifted, tcg_constant_i32(16)); rn_shifted, tcg_constant_i32(16));
gen_helper_mve_vctp(cpu_env, masklen); gen_helper_mve_vctp(tcg_env, masklen);
/* This insn updates predication bits */ /* This insn updates predication bits */
s->base.is_jmp = DISAS_UPDATE_NOCHAIN; s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
mve_update_eci(s); mve_update_eci(s);
@ -8665,12 +8665,12 @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
/* FAULTMASK */ /* FAULTMASK */
if (a->F) { if (a->F) {
addr = tcg_constant_i32(19); addr = tcg_constant_i32(19);
gen_helper_v7m_msr(cpu_env, addr, tmp); gen_helper_v7m_msr(tcg_env, addr, tmp);
} }
/* PRIMASK */ /* PRIMASK */
if (a->I) { if (a->I) {
addr = tcg_constant_i32(16); addr = tcg_constant_i32(16);
gen_helper_v7m_msr(cpu_env, addr, tmp); gen_helper_v7m_msr(tcg_env, addr, tmp);
} }
gen_rebuild_hflags(s, false); gen_rebuild_hflags(s, false);
gen_lookup_tb(s); gen_lookup_tb(s);
@ -8740,7 +8740,7 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND *a)
return false; return false;
} }
if (a->E != (s->be_data == MO_BE)) { if (a->E != (s->be_data == MO_BE)) {
gen_helper_setend(cpu_env); gen_helper_setend(tcg_env);
s->base.is_jmp = DISAS_UPDATE_EXIT; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
return true; return true;
@ -9335,7 +9335,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
* be possible after an indirect branch, at the start of the TB. * be possible after an indirect branch, at the start of the TB.
*/ */
assert(dc->base.num_insns == 1); assert(dc->base.num_insns == 1);
gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc));
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); dc->base.pc_next = QEMU_ALIGN_UP(pc, 4);
return; return;
@ -9615,7 +9615,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
/* nothing more to generate */ /* nothing more to generate */
break; break;
case DISAS_WFI: case DISAS_WFI:
gen_helper_wfi(cpu_env, tcg_constant_i32(curr_insn_len(dc))); gen_helper_wfi(tcg_env, tcg_constant_i32(curr_insn_len(dc)));
/* /*
* The helper doesn't necessarily throw an exception, but we * The helper doesn't necessarily throw an exception, but we
* must go back to the main loop to check for interrupts anyway. * must go back to the main loop to check for interrupts anyway.
@ -9623,10 +9623,10 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
tcg_gen_exit_tb(NULL, 0); tcg_gen_exit_tb(NULL, 0);
break; break;
case DISAS_WFE: case DISAS_WFE:
gen_helper_wfe(cpu_env); gen_helper_wfe(tcg_env);
break; break;
case DISAS_YIELD: case DISAS_YIELD:
gen_helper_yield(cpu_env); gen_helper_yield(tcg_env);
break; break;
case DISAS_SWI: case DISAS_SWI:
gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));

16
target/arm/tcg/translate.h
View File

@ -329,7 +329,7 @@ static inline TCGv_i32 get_ahp_flag(void)
{ {
TCGv_i32 ret = tcg_temp_new_i32(); TCGv_i32 ret = tcg_temp_new_i32();
tcg_gen_ld_i32(ret, cpu_env, tcg_gen_ld_i32(ret, tcg_env,
offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR])); offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
tcg_gen_extract_i32(ret, ret, 26, 1); tcg_gen_extract_i32(ret, ret, 26, 1);
@ -343,9 +343,9 @@ static inline void set_pstate_bits(uint32_t bits)
tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
tcg_gen_ori_i32(p, p, bits); tcg_gen_ori_i32(p, p, bits);
tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
} }
/* Clear bits within PSTATE. */ /* Clear bits within PSTATE. */
@ -355,9 +355,9 @@ static inline void clear_pstate_bits(uint32_t bits)
tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
tcg_gen_andi_i32(p, p, ~bits); tcg_gen_andi_i32(p, p, ~bits);
tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
} }
/* If the singlestep state is Active-not-pending, advance to Active-pending. */ /* If the singlestep state is Active-not-pending, advance to Active-pending. */
@ -374,7 +374,7 @@ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
{ {
/* Fill in the same_el field of the syndrome in the helper. */ /* Fill in the same_el field of the syndrome in the helper. */
uint32_t syn = syn_swstep(false, isv, ex); uint32_t syn = syn_swstep(false, isv, ex);
gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn)); gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn));
} }
/* /*
@ -557,7 +557,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }
tcg_gen_addi_ptr(statusptr, cpu_env, offset); tcg_gen_addi_ptr(statusptr, tcg_env, offset);
return statusptr; return statusptr;
} }
@ -679,7 +679,7 @@ static inline void set_disas_label(DisasContext *s, DisasLabel l)
static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key) static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
{ {
TCGv_ptr ret = tcg_temp_new_ptr(); TCGv_ptr ret = tcg_temp_new_ptr();
gen_helper_lookup_cp_reg(ret, cpu_env, tcg_constant_i32(key)); gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key));
return ret; return ret;
} }

64
target/avr/translate.c
View File

@ -127,25 +127,25 @@ void avr_cpu_tcg_init(void)
int i; int i;
#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x) #define AVR_REG_OFFS(x) offsetof(CPUAVRState, x)
cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc"); cpu_pc = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(pc_w), "pc");
cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf"); cpu_Cf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregC), "Cf");
cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf"); cpu_Zf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregZ), "Zf");
cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf"); cpu_Nf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregN), "Nf");
cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf"); cpu_Vf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregV), "Vf");
cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf"); cpu_Sf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregS), "Sf");
cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf"); cpu_Hf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregH), "Hf");
cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf"); cpu_Tf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregT), "Tf");
cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If"); cpu_If = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregI), "If");
cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD"); cpu_rampD = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampD), "rampD");
cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX"); cpu_rampX = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampX), "rampX");
cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY"); cpu_rampY = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampY), "rampY");
cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ"); cpu_rampZ = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampZ), "rampZ");
cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind"); cpu_eind = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(eind), "eind");
cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp"); cpu_sp = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sp), "sp");
cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip"); cpu_skip = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(skip), "skip");
for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) { for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) {
cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]), cpu_r[i] = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(r[i]),
reg_names[i]); reg_names[i]);
} }
#undef AVR_REG_OFFS #undef AVR_REG_OFFS
@ -184,7 +184,7 @@ static int append_16(DisasContext *ctx, int x)
static bool avr_have_feature(DisasContext *ctx, int feature) static bool avr_have_feature(DisasContext *ctx, int feature)
{ {
if (!avr_feature(ctx->env, feature)) { if (!avr_feature(ctx->env, feature)) {
gen_helper_unsupported(cpu_env); gen_helper_unsupported(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return false; return false;
} }
@ -1295,7 +1295,7 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
TCGv data = tcg_temp_new_i32(); TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg); TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port); gen_helper_inb(data, tcg_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit); tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_EQ; ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = data; ctx->skip_var0 = data;
@ -1313,7 +1313,7 @@ static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a)
TCGv data = tcg_temp_new_i32(); TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg); TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port); gen_helper_inb(data, tcg_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit); tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_NE; ctx->skip_cond = TCG_COND_NE;
ctx->skip_var0 = data; ctx->skip_var0 = data;
@ -1494,7 +1494,7 @@ static TCGv gen_get_zaddr(void)
static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
{ {
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
gen_helper_fullwr(cpu_env, data, addr); gen_helper_fullwr(tcg_env, data, addr);
} else { } else {
tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB); tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB);
} }
@ -1503,7 +1503,7 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
{ {
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
gen_helper_fullrd(data, cpu_env, addr); gen_helper_fullrd(data, tcg_env, addr);
} else { } else {
tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB);
} }
@ -2130,7 +2130,7 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a)
TCGv Rd = cpu_r[a->rd]; TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_constant_i32(a->imm); TCGv port = tcg_constant_i32(a->imm);
gen_helper_inb(Rd, cpu_env, port); gen_helper_inb(Rd, tcg_env, port);
return true; return true;
} }
@ -2143,7 +2143,7 @@ static bool trans_OUT(DisasContext *ctx, arg_OUT *a)
TCGv Rd = cpu_r[a->rd]; TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_constant_i32(a->imm); TCGv port = tcg_constant_i32(a->imm);
gen_helper_outb(cpu_env, port, Rd); gen_helper_outb(tcg_env, port, Rd);
return true; return true;
} }
@ -2411,9 +2411,9 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
TCGv data = tcg_temp_new_i32(); TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg); TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port); gen_helper_inb(data, tcg_env, port);
tcg_gen_ori_tl(data, data, 1 << a->bit); tcg_gen_ori_tl(data, data, 1 << a->bit);
gen_helper_outb(cpu_env, port, data); gen_helper_outb(tcg_env, port, data);
return true; return true;
} }
@ -2426,9 +2426,9 @@ static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
TCGv data = tcg_temp_new_i32(); TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg); TCGv port = tcg_constant_i32(a->reg);
gen_helper_inb(data, cpu_env, port); gen_helper_inb(data, tcg_env, port);
tcg_gen_andi_tl(data, data, ~(1 << a->bit)); tcg_gen_andi_tl(data, data, ~(1 << a->bit));
gen_helper_outb(cpu_env, port, data); gen_helper_outb(tcg_env, port, data);
return true; return true;
} }
@ -2551,7 +2551,7 @@ static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
#ifdef BREAKPOINT_ON_BREAK #ifdef BREAKPOINT_ON_BREAK
tcg_gen_movi_tl(cpu_pc, ctx->npc - 1); tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
gen_helper_debug(cpu_env); gen_helper_debug(tcg_env);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
#else #else
/* NOP */ /* NOP */
@ -2577,7 +2577,7 @@ static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
*/ */
static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a) static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
{ {
gen_helper_sleep(cpu_env); gen_helper_sleep(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return true; return true;
} }
@ -2589,7 +2589,7 @@ static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
*/ */
static bool trans_WDR(DisasContext *ctx, arg_WDR *a) static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
{ {
gen_helper_wdr(cpu_env); gen_helper_wdr(tcg_env);
return true; return true;
} }
@ -2608,7 +2608,7 @@ static void translate(DisasContext *ctx)
uint32_t opcode = next_word(ctx); uint32_t opcode = next_word(ctx);
if (!decode_insn(ctx, opcode)) { if (!decode_insn(ctx, opcode)) {
gen_helper_unsupported(cpu_env); gen_helper_unsupported(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
} }
} }

68
target/cris/translate.c
View File

@ -171,9 +171,9 @@ static const int preg_sizes[] = {
}; };
#define t_gen_mov_TN_env(tn, member) \ #define t_gen_mov_TN_env(tn, member) \
tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member)) tcg_gen_ld_tl(tn, tcg_env, offsetof(CPUCRISState, member))
#define t_gen_mov_env_TN(member, tn) \ #define t_gen_mov_env_TN(member, tn) \
tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member)) tcg_gen_st_tl(tn, tcg_env, offsetof(CPUCRISState, member))
#define t_gen_movi_env_TN(member, c) \ #define t_gen_movi_env_TN(member, c) \
t_gen_mov_env_TN(member, tcg_constant_tl(c)) t_gen_mov_env_TN(member, tcg_constant_tl(c))
@ -197,10 +197,10 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
tcg_gen_andi_tl(cpu_PR[r], tn, 3); tcg_gen_andi_tl(cpu_PR[r], tn, 3);
} else { } else {
if (r == PR_PID) { if (r == PR_PID) {
gen_helper_tlb_flush_pid(cpu_env, tn); gen_helper_tlb_flush_pid(tcg_env, tn);
} }
if (dc->tb_flags & S_FLAG && r == PR_SPC) { if (dc->tb_flags & S_FLAG && r == PR_SPC) {
gen_helper_spc_write(cpu_env, tn); gen_helper_spc_write(tcg_env, tn);
} else if (r == PR_CCS) { } else if (r == PR_CCS) {
dc->cpustate_changed = 1; dc->cpustate_changed = 1;
} }
@ -265,7 +265,7 @@ static void cris_lock_irq(DisasContext *dc)
static inline void t_gen_raise_exception(uint32_t index) static inline void t_gen_raise_exception(uint32_t index)
{ {
gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); gen_helper_raise_exception(tcg_env, tcg_constant_i32(index));
} }
static void t_gen_lsl(TCGv d, TCGv a, TCGv b) static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
@ -504,17 +504,17 @@ static void cris_evaluate_flags(DisasContext *dc)
switch (dc->cc_op) { switch (dc->cc_op) {
case CC_OP_MCP: case CC_OP_MCP:
gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env, gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_src, cpu_PR[PR_CCS], cc_src,
cc_dest, cc_result); cc_dest, cc_result);
break; break;
case CC_OP_MULS: case CC_OP_MULS:
gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env, gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_result, cpu_PR[PR_CCS], cc_result,
cpu_PR[PR_MOF]); cpu_PR[PR_MOF]);
break; break;
case CC_OP_MULU: case CC_OP_MULU:
gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env, gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_result, cpu_PR[PR_CCS], cc_result,
cpu_PR[PR_MOF]); cpu_PR[PR_MOF]);
break; break;
@ -528,14 +528,14 @@ static void cris_evaluate_flags(DisasContext *dc)
switch (dc->cc_size) { switch (dc->cc_size) {
case 4: case 4:
gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
cpu_env, cpu_PR[PR_CCS], cc_result); tcg_env, cpu_PR[PR_CCS], cc_result);
break; break;
case 2: case 2:
gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
cpu_env, cpu_PR[PR_CCS], cc_result); tcg_env, cpu_PR[PR_CCS], cc_result);
break; break;
default: default:
gen_helper_evaluate_flags(cpu_env); gen_helper_evaluate_flags(tcg_env);
break; break;
} }
break; break;
@ -545,21 +545,21 @@ static void cris_evaluate_flags(DisasContext *dc)
case CC_OP_SUB: case CC_OP_SUB:
case CC_OP_CMP: case CC_OP_CMP:
if (dc->cc_size == 4) { if (dc->cc_size == 4) {
gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env, gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
} else { } else {
gen_helper_evaluate_flags(cpu_env); gen_helper_evaluate_flags(tcg_env);
} }
break; break;
default: default:
switch (dc->cc_size) { switch (dc->cc_size) {
case 4: case 4:
gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env, gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
break; break;
default: default:
gen_helper_evaluate_flags(cpu_env); gen_helper_evaluate_flags(tcg_env);
break; break;
} }
break; break;
@ -1330,7 +1330,7 @@ static int dec_btstq(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZ); cris_cc_mask(dc, CC_MASK_NZ);
c = tcg_constant_tl(dc->op1); c = tcg_constant_tl(dc->op1);
cris_evaluate_flags(dc); cris_evaluate_flags(dc);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2],
c, cpu_PR[PR_CCS]); c, cpu_PR[PR_CCS]);
cris_alu(dc, CC_OP_MOVE, cris_alu(dc, CC_OP_MOVE,
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
@ -1744,7 +1744,7 @@ static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
dc->op1, dc->op2); dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ); cris_cc_mask(dc, CC_MASK_NZ);
cris_evaluate_flags(dc); cris_evaluate_flags(dc);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2],
cpu_R[dc->op1], cpu_PR[PR_CCS]); cpu_R[dc->op1], cpu_PR[PR_CCS]);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
cpu_R[dc->op2], cpu_R[dc->op2], 4); cpu_R[dc->op2], cpu_R[dc->op2], 4);
@ -1946,7 +1946,7 @@ static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
c1 = tcg_constant_tl(dc->op1); c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2); c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0); cris_cc_mask(dc, 0);
gen_helper_movl_sreg_reg(cpu_env, c2, c1); gen_helper_movl_sreg_reg(tcg_env, c2, c1);
return 2; return 2;
} }
static int dec_move_sr(CPUCRISState *env, DisasContext *dc) static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
@ -1956,7 +1956,7 @@ static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
c1 = tcg_constant_tl(dc->op1); c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2); c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0); cris_cc_mask(dc, 0);
gen_helper_movl_reg_sreg(cpu_env, c1, c2); gen_helper_movl_reg_sreg(tcg_env, c1, c2);
return 2; return 2;
} }
@ -2693,7 +2693,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, 0); cris_cc_mask(dc, 0);
if (dc->op2 == 15) { if (dc->op2 == 15) {
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(CRISCPU, env) + offsetof(CPUState, halted)); -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
tcg_gen_movi_tl(env_pc, dc->pc + 2); tcg_gen_movi_tl(env_pc, dc->pc + 2);
t_gen_raise_exception(EXCP_HLT); t_gen_raise_exception(EXCP_HLT);
@ -2706,7 +2706,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
/* rfe. */ /* rfe. */
LOG_DIS("rfe\n"); LOG_DIS("rfe\n");
cris_evaluate_flags(dc); cris_evaluate_flags(dc);
gen_helper_rfe(cpu_env); gen_helper_rfe(tcg_env);
dc->base.is_jmp = DISAS_UPDATE; dc->base.is_jmp = DISAS_UPDATE;
dc->cpustate_changed = true; dc->cpustate_changed = true;
break; break;
@ -2714,7 +2714,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
/* rfn. */ /* rfn. */
LOG_DIS("rfn\n"); LOG_DIS("rfn\n");
cris_evaluate_flags(dc); cris_evaluate_flags(dc);
gen_helper_rfn(cpu_env); gen_helper_rfn(tcg_env);
dc->base.is_jmp = DISAS_UPDATE; dc->base.is_jmp = DISAS_UPDATE;
dc->cpustate_changed = true; dc->cpustate_changed = true;
break; break;
@ -3238,41 +3238,41 @@ void cris_initialize_tcg(void)
{ {
int i; int i;
cc_x = tcg_global_mem_new(cpu_env, cc_x = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_x), "cc_x"); offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env, cc_src = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_src), "cc_src"); offsetof(CPUCRISState, cc_src), "cc_src");
cc_dest = tcg_global_mem_new(cpu_env, cc_dest = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_dest), offsetof(CPUCRISState, cc_dest),
"cc_dest"); "cc_dest");
cc_result = tcg_global_mem_new(cpu_env, cc_result = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_result), offsetof(CPUCRISState, cc_result),
"cc_result"); "cc_result");
cc_op = tcg_global_mem_new(cpu_env, cc_op = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_op), "cc_op"); offsetof(CPUCRISState, cc_op), "cc_op");
cc_size = tcg_global_mem_new(cpu_env, cc_size = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_size), offsetof(CPUCRISState, cc_size),
"cc_size"); "cc_size");
cc_mask = tcg_global_mem_new(cpu_env, cc_mask = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_mask), offsetof(CPUCRISState, cc_mask),
"cc_mask"); "cc_mask");
env_pc = tcg_global_mem_new(cpu_env, env_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pc), offsetof(CPUCRISState, pc),
"pc"); "pc");
env_btarget = tcg_global_mem_new(cpu_env, env_btarget = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btarget), offsetof(CPUCRISState, btarget),
"btarget"); "btarget");
env_btaken = tcg_global_mem_new(cpu_env, env_btaken = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btaken), offsetof(CPUCRISState, btaken),
"btaken"); "btaken");
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env, cpu_R[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, regs[i]), offsetof(CPUCRISState, regs[i]),
regnames_v32[i]); regnames_v32[i]);
} }
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
cpu_PR[i] = tcg_global_mem_new(cpu_env, cpu_PR[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pregs[i]), offsetof(CPUCRISState, pregs[i]),
pregnames_v32[i]); pregnames_v32[i]);
} }

28
target/cris/translate_v10.c.inc
View File

@ -282,7 +282,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
} else { } else {
/* BTST */ /* BTST */
cris_update_cc_op(dc, CC_OP_FLAGS, 4); cris_update_cc_op(dc, CC_OP_FLAGS, 4);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst], gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->dst],
c, cpu_PR[PR_CCS]); c, cpu_PR[PR_CCS]);
} }
break; break;
@ -696,7 +696,7 @@ static unsigned int dec10_reg(DisasContext *dc)
LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
cris_cc_mask(dc, CC_MASK_NZVC); cris_cc_mask(dc, CC_MASK_NZVC);
cris_update_cc_op(dc, CC_OP_FLAGS, 4); cris_update_cc_op(dc, CC_OP_FLAGS, 4);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst], gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->dst],
cpu_R[dc->src], cpu_PR[PR_CCS]); cpu_R[dc->src], cpu_PR[PR_CCS]);
break; break;
case CRISV10_REG_DSTEP: case CRISV10_REG_DSTEP:
@ -1235,41 +1235,41 @@ void cris_initialize_crisv10_tcg(void)
{ {
int i; int i;
cc_x = tcg_global_mem_new(cpu_env, cc_x = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_x), "cc_x"); offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env, cc_src = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_src), "cc_src"); offsetof(CPUCRISState, cc_src), "cc_src");
cc_dest = tcg_global_mem_new(cpu_env, cc_dest = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_dest), offsetof(CPUCRISState, cc_dest),
"cc_dest"); "cc_dest");
cc_result = tcg_global_mem_new(cpu_env, cc_result = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_result), offsetof(CPUCRISState, cc_result),
"cc_result"); "cc_result");
cc_op = tcg_global_mem_new(cpu_env, cc_op = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_op), "cc_op"); offsetof(CPUCRISState, cc_op), "cc_op");
cc_size = tcg_global_mem_new(cpu_env, cc_size = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_size), offsetof(CPUCRISState, cc_size),
"cc_size"); "cc_size");
cc_mask = tcg_global_mem_new(cpu_env, cc_mask = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_mask), offsetof(CPUCRISState, cc_mask),
"cc_mask"); "cc_mask");
env_pc = tcg_global_mem_new(cpu_env, env_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pc), offsetof(CPUCRISState, pc),
"pc"); "pc");
env_btarget = tcg_global_mem_new(cpu_env, env_btarget = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btarget), offsetof(CPUCRISState, btarget),
"btarget"); "btarget");
env_btaken = tcg_global_mem_new(cpu_env, env_btaken = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btaken), offsetof(CPUCRISState, btaken),
"btaken"); "btaken");
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env, cpu_R[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, regs[i]), offsetof(CPUCRISState, regs[i]),
regnames_v10[i]); regnames_v10[i]);
} }
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
cpu_PR[i] = tcg_global_mem_new(cpu_env, cpu_PR[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pregs[i]), offsetof(CPUCRISState, pregs[i]),
pregnames_v10[i]); pregnames_v10[i]);
} }

10
target/hexagon/README
View File

@ -86,7 +86,7 @@ tcg_funcs_generated.c.inc
const int RdN = insn->regno[0]; const int RdN = insn->regno[0];
TCGv RsV = hex_gpr[insn->regno[1]]; TCGv RsV = hex_gpr[insn->regno[1]];
TCGv RtV = hex_gpr[insn->regno[2]]; TCGv RtV = hex_gpr[insn->regno[2]];
gen_helper_A2_add(RdV, cpu_env, RsV, RtV); gen_helper_A2_add(RdV, tcg_env, RsV, RtV);
gen_log_reg_write(ctx, RdN, RdV); gen_log_reg_write(ctx, RdN, RdV);
} }
@ -143,7 +143,7 @@ istruction.
const intptr_t VdV_off = const intptr_t VdV_off =
ctx_future_vreg_off(ctx, VdN, 1, true); ctx_future_vreg_off(ctx, VdN, 1, true);
TCGv_ptr VdV = tcg_temp_new_ptr(); TCGv_ptr VdV = tcg_temp_new_ptr();
tcg_gen_addi_ptr(VdV, cpu_env, VdV_off); tcg_gen_addi_ptr(VdV, tcg_env, VdV_off);
const int VuN = insn->regno[1]; const int VuN = insn->regno[1];
const intptr_t VuV_off = const intptr_t VuV_off =
vreg_src_off(ctx, VuN); vreg_src_off(ctx, VuN);
@ -152,9 +152,9 @@ istruction.
const intptr_t VvV_off = const intptr_t VvV_off =
vreg_src_off(ctx, VvN); vreg_src_off(ctx, VvN);
TCGv_ptr VvV = tcg_temp_new_ptr(); TCGv_ptr VvV = tcg_temp_new_ptr();
tcg_gen_addi_ptr(VuV, cpu_env, VuV_off); tcg_gen_addi_ptr(VuV, tcg_env, VuV_off);
tcg_gen_addi_ptr(VvV, cpu_env, VvV_off); tcg_gen_addi_ptr(VvV, tcg_env, VvV_off);
gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV); gen_helper_V6_vaddw(tcg_env, VdV, VuV, VvV);
} }
Notice that we also generate a variable named <operand>_off for each operand of Notice that we also generate a variable named <operand>_off for each operand of

120
target/hexagon/gen_tcg.h
View File

@ -591,8 +591,8 @@
*/ */
#define fGEN_TCG_A5_ACS(SHORTCODE) \ #define fGEN_TCG_A5_ACS(SHORTCODE) \
do { \ do { \
gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \ gen_helper_vacsh_pred(PeV, tcg_env, RxxV, RssV, RttV); \
gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV, \ gen_helper_vacsh_val(RxxV, tcg_env, RxxV, RssV, RttV, \
tcg_constant_tl(ctx->need_commit)); \ tcg_constant_tl(ctx->need_commit)); \
} while (0) } while (0)
@ -614,7 +614,7 @@
#define fGEN_TCG_F2_sfrecipa(SHORTCODE) \ #define fGEN_TCG_F2_sfrecipa(SHORTCODE) \
do { \ do { \
TCGv_i64 tmp = tcg_temp_new_i64(); \ TCGv_i64 tmp = tcg_temp_new_i64(); \
gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \ gen_helper_sfrecipa(tmp, tcg_env, RsV, RtV); \
tcg_gen_extrh_i64_i32(RdV, tmp); \ tcg_gen_extrh_i64_i32(RdV, tmp); \
tcg_gen_extrl_i64_i32(PeV, tmp); \ tcg_gen_extrl_i64_i32(PeV, tmp); \
} while (0) } while (0)
@ -629,7 +629,7 @@
#define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \ #define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \
do { \ do { \
TCGv_i64 tmp = tcg_temp_new_i64(); \ TCGv_i64 tmp = tcg_temp_new_i64(); \
gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \ gen_helper_sfinvsqrta(tmp, tcg_env, RsV); \
tcg_gen_extrh_i64_i32(RdV, tmp); \ tcg_gen_extrh_i64_i32(RdV, tmp); \
tcg_gen_extrl_i64_i32(PeV, tmp); \ tcg_gen_extrl_i64_i32(PeV, tmp); \
} while (0) } while (0)
@ -1205,122 +1205,122 @@
/* Floating point */ /* Floating point */
#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
gen_helper_conv_sf2df(RddV, cpu_env, RsV) gen_helper_conv_sf2df(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \ #define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \
gen_helper_conv_df2sf(RdV, cpu_env, RssV) gen_helper_conv_df2sf(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \ #define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \
gen_helper_conv_uw2sf(RdV, cpu_env, RsV) gen_helper_conv_uw2sf(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \ #define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \
gen_helper_conv_uw2df(RddV, cpu_env, RsV) gen_helper_conv_uw2df(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \ #define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \
gen_helper_conv_w2sf(RdV, cpu_env, RsV) gen_helper_conv_w2sf(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \ #define fGEN_TCG_F2_conv_w2df(SHORTCODE) \
gen_helper_conv_w2df(RddV, cpu_env, RsV) gen_helper_conv_w2df(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \ #define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \
gen_helper_conv_ud2sf(RdV, cpu_env, RssV) gen_helper_conv_ud2sf(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \ #define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \
gen_helper_conv_ud2df(RddV, cpu_env, RssV) gen_helper_conv_ud2df(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \ #define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \
gen_helper_conv_d2sf(RdV, cpu_env, RssV) gen_helper_conv_d2sf(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \ #define fGEN_TCG_F2_conv_d2df(SHORTCODE) \
gen_helper_conv_d2df(RddV, cpu_env, RssV) gen_helper_conv_d2df(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \ #define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \
gen_helper_conv_sf2uw(RdV, cpu_env, RsV) gen_helper_conv_sf2uw(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \ #define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \
gen_helper_conv_sf2w(RdV, cpu_env, RsV) gen_helper_conv_sf2w(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \ #define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \
gen_helper_conv_sf2ud(RddV, cpu_env, RsV) gen_helper_conv_sf2ud(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \ #define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \
gen_helper_conv_sf2d(RddV, cpu_env, RsV) gen_helper_conv_sf2d(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \ #define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \
gen_helper_conv_df2uw(RdV, cpu_env, RssV) gen_helper_conv_df2uw(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \ #define fGEN_TCG_F2_conv_df2w(SHORTCODE) \
gen_helper_conv_df2w(RdV, cpu_env, RssV) gen_helper_conv_df2w(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \ #define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \
gen_helper_conv_df2ud(RddV, cpu_env, RssV) gen_helper_conv_df2ud(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \ #define fGEN_TCG_F2_conv_df2d(SHORTCODE) \
gen_helper_conv_df2d(RddV, cpu_env, RssV) gen_helper_conv_df2d(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \ #define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \
gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV) gen_helper_conv_sf2uw_chop(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \ #define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \
gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV) gen_helper_conv_sf2w_chop(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \ #define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \
gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV) gen_helper_conv_sf2ud_chop(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \ #define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \
gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV) gen_helper_conv_sf2d_chop(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \ #define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \
gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV) gen_helper_conv_df2uw_chop(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \ #define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \
gen_helper_conv_df2w_chop(RdV, cpu_env, RssV) gen_helper_conv_df2w_chop(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \ #define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \
gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV) gen_helper_conv_df2ud_chop(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \ #define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \
gen_helper_conv_df2d_chop(RddV, cpu_env, RssV) gen_helper_conv_df2d_chop(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_sfadd(SHORTCODE) \ #define fGEN_TCG_F2_sfadd(SHORTCODE) \
gen_helper_sfadd(RdV, cpu_env, RsV, RtV) gen_helper_sfadd(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfsub(SHORTCODE) \ #define fGEN_TCG_F2_sfsub(SHORTCODE) \
gen_helper_sfsub(RdV, cpu_env, RsV, RtV) gen_helper_sfsub(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \ #define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \
gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV) gen_helper_sfcmpeq(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \ #define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \
gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV) gen_helper_sfcmpgt(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \ #define fGEN_TCG_F2_sfcmpge(SHORTCODE) \
gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV) gen_helper_sfcmpge(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \ #define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \
gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV) gen_helper_sfcmpuo(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfmax(SHORTCODE) \ #define fGEN_TCG_F2_sfmax(SHORTCODE) \
gen_helper_sfmax(RdV, cpu_env, RsV, RtV) gen_helper_sfmax(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfmin(SHORTCODE) \ #define fGEN_TCG_F2_sfmin(SHORTCODE) \
gen_helper_sfmin(RdV, cpu_env, RsV, RtV) gen_helper_sfmin(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfclass(SHORTCODE) \ #define fGEN_TCG_F2_sfclass(SHORTCODE) \
do { \ do { \
TCGv imm = tcg_constant_tl(uiV); \ TCGv imm = tcg_constant_tl(uiV); \
gen_helper_sfclass(PdV, cpu_env, RsV, imm); \ gen_helper_sfclass(PdV, tcg_env, RsV, imm); \
} while (0) } while (0)
#define fGEN_TCG_F2_sffixupn(SHORTCODE) \ #define fGEN_TCG_F2_sffixupn(SHORTCODE) \
gen_helper_sffixupn(RdV, cpu_env, RsV, RtV) gen_helper_sffixupn(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sffixupd(SHORTCODE) \ #define fGEN_TCG_F2_sffixupd(SHORTCODE) \
gen_helper_sffixupd(RdV, cpu_env, RsV, RtV) gen_helper_sffixupd(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sffixupr(SHORTCODE) \ #define fGEN_TCG_F2_sffixupr(SHORTCODE) \
gen_helper_sffixupr(RdV, cpu_env, RsV) gen_helper_sffixupr(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_dfadd(SHORTCODE) \ #define fGEN_TCG_F2_dfadd(SHORTCODE) \
gen_helper_dfadd(RddV, cpu_env, RssV, RttV) gen_helper_dfadd(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfsub(SHORTCODE) \ #define fGEN_TCG_F2_dfsub(SHORTCODE) \
gen_helper_dfsub(RddV, cpu_env, RssV, RttV) gen_helper_dfsub(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfmax(SHORTCODE) \ #define fGEN_TCG_F2_dfmax(SHORTCODE) \
gen_helper_dfmax(RddV, cpu_env, RssV, RttV) gen_helper_dfmax(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfmin(SHORTCODE) \ #define fGEN_TCG_F2_dfmin(SHORTCODE) \
gen_helper_dfmin(RddV, cpu_env, RssV, RttV) gen_helper_dfmin(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \ #define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \
gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV) gen_helper_dfcmpeq(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \ #define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \
gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV) gen_helper_dfcmpgt(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \ #define fGEN_TCG_F2_dfcmpge(SHORTCODE) \
gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV) gen_helper_dfcmpge(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \ #define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \
gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV) gen_helper_dfcmpuo(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfclass(SHORTCODE) \ #define fGEN_TCG_F2_dfclass(SHORTCODE) \
do { \ do { \
TCGv imm = tcg_constant_tl(uiV); \ TCGv imm = tcg_constant_tl(uiV); \
gen_helper_dfclass(PdV, cpu_env, RssV, imm); \ gen_helper_dfclass(PdV, tcg_env, RssV, imm); \
} while (0) } while (0)
#define fGEN_TCG_F2_sfmpy(SHORTCODE) \ #define fGEN_TCG_F2_sfmpy(SHORTCODE) \
gen_helper_sfmpy(RdV, cpu_env, RsV, RtV) gen_helper_sfmpy(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sffma(SHORTCODE) \ #define fGEN_TCG_F2_sffma(SHORTCODE) \
gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV) gen_helper_sffma(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \ #define fGEN_TCG_F2_sffma_sc(SHORTCODE) \
gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV) gen_helper_sffma_sc(RxV, tcg_env, RxV, RsV, RtV, PuV)
#define fGEN_TCG_F2_sffms(SHORTCODE) \ #define fGEN_TCG_F2_sffms(SHORTCODE) \
gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV) gen_helper_sffms(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \ #define fGEN_TCG_F2_sffma_lib(SHORTCODE) \
gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV) gen_helper_sffma_lib(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \ #define fGEN_TCG_F2_sffms_lib(SHORTCODE) \
gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV) gen_helper_sffms_lib(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \ #define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \
gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV) gen_helper_dfmpyfix(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \ #define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV) gen_helper_dfmpyhh(RxxV, tcg_env, RxxV, RssV, RttV)
/* Nothing to do for these in qemu, need to suppress compiler warnings */ /* Nothing to do for these in qemu, need to suppress compiler warnings */
#define fGEN_TCG_Y4_l2fetch(SHORTCODE) \ #define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
@ -1367,6 +1367,6 @@
uiV = uiV; \ uiV = uiV; \
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \ tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \
TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \ TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \
gen_helper_raise_exception(cpu_env, excp); \ gen_helper_raise_exception(tcg_env, excp); \
} while (0) } while (0)
#endif #endif

16
target/hexagon/gen_tcg_funcs.py
View File

@ -120,7 +120,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
if not hex_common.skip_qemu_helper(tag): if not hex_common.skip_qemu_helper(tag):
f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n") f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
f.write( f.write(
f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n" f"{regtype}{regid}V_off);\n"
) )
elif regid in {"uu", "vv", "xx"}: elif regid in {"uu", "vv", "xx"}:
@ -130,7 +130,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
if not hex_common.skip_qemu_helper(tag): if not hex_common.skip_qemu_helper(tag):
f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n") f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
f.write( f.write(
f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n" f"{regtype}{regid}V_off);\n"
) )
elif regid in {"s", "u", "v", "w"}: elif regid in {"s", "u", "v", "w"}:
@ -155,7 +155,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
if not hex_common.skip_qemu_helper(tag): if not hex_common.skip_qemu_helper(tag):
f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n") f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
f.write( f.write(
f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n" f"{regtype}{regid}V_off);\n"
) )
else: else:
@ -168,7 +168,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
if not hex_common.skip_qemu_helper(tag): if not hex_common.skip_qemu_helper(tag):
f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n") f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
f.write( f.write(
f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n" f"{regtype}{regid}V_off);\n"
) )
elif regid in {"s", "t", "u", "v"}: elif regid in {"s", "t", "u", "v"}:
@ -303,7 +303,7 @@ def genptr_src_read(f, tag, regtype, regid):
elif regid in {"s", "u", "v", "w"}: elif regid in {"s", "u", "v", "w"}:
if not hex_common.skip_qemu_helper(tag): if not hex_common.skip_qemu_helper(tag):
f.write( f.write(
f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n" f"{regtype}{regid}V_off);\n"
) )
elif regid in {"x", "y"}: elif regid in {"x", "y"}:
@ -316,7 +316,7 @@ def genptr_src_read(f, tag, regtype, regid):
if regid in {"s", "t", "u", "v"}: if regid in {"s", "t", "u", "v"}:
if not hex_common.skip_qemu_helper(tag): if not hex_common.skip_qemu_helper(tag):
f.write( f.write(
f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n" f"{regtype}{regid}V_off);\n"
) )
elif regid in {"x"}: elif regid in {"x"}:
@ -490,7 +490,7 @@ def genptr_dst_write_opn(f, regtype, regid, tag):
## if hex_common.skip_qemu_helper(tag) is True ## if hex_common.skip_qemu_helper(tag) is True
## <GEN> is fGEN_TCG_A2_add({ RdV=RsV+RtV;}); ## <GEN> is fGEN_TCG_A2_add({ RdV=RsV+RtV;});
## if hex_common.skip_qemu_helper(tag) is False ## if hex_common.skip_qemu_helper(tag) is False
## <GEN> is gen_helper_A2_add(RdV, cpu_env, RsV, RtV); ## <GEN> is gen_helper_A2_add(RdV, tcg_env, RsV, RtV);
## ##
def gen_tcg_func(f, tag, regs, imms): def gen_tcg_func(f, tag, regs, imms):
f.write(f"static void generate_{tag}(DisasContext *ctx)\n") f.write(f"static void generate_{tag}(DisasContext *ctx)\n")
@ -572,7 +572,7 @@ def gen_tcg_func(f, tag, regs, imms):
i += 1 i += 1
if i > 0: if i > 0:
f.write(", ") f.write(", ")
f.write("cpu_env") f.write("tcg_env")
i = 1 i = 1
## For conditional instructions, we pass in the destination register ## For conditional instructions, we pass in the destination register
if "A_CONDEXEC" in hex_common.attribdict[tag]: if "A_CONDEXEC" in hex_common.attribdict[tag]:

20
target/hexagon/gen_tcg_hvx.h
View File

@ -43,7 +43,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
#define fGEN_TCG_V6_vhist(SHORTCODE) \ #define fGEN_TCG_V6_vhist(SHORTCODE) \
if (!ctx->pre_commit) { \ if (!ctx->pre_commit) { \
assert_vhist_tmp(ctx); \ assert_vhist_tmp(ctx); \
gen_helper_vhist(cpu_env); \ gen_helper_vhist(tcg_env); \
} }
#define fGEN_TCG_V6_vhistq(SHORTCODE) \ #define fGEN_TCG_V6_vhistq(SHORTCODE) \
do { \ do { \
@ -53,13 +53,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
sizeof(MMVector), sizeof(MMVector)); \ sizeof(MMVector), sizeof(MMVector)); \
} else { \ } else { \
assert_vhist_tmp(ctx); \ assert_vhist_tmp(ctx); \
gen_helper_vhistq(cpu_env); \ gen_helper_vhistq(tcg_env); \
} \ } \
} while (0) } while (0)
#define fGEN_TCG_V6_vwhist256(SHORTCODE) \ #define fGEN_TCG_V6_vwhist256(SHORTCODE) \
if (!ctx->pre_commit) { \ if (!ctx->pre_commit) { \
assert_vhist_tmp(ctx); \ assert_vhist_tmp(ctx); \
gen_helper_vwhist256(cpu_env); \ gen_helper_vwhist256(tcg_env); \
} }
#define fGEN_TCG_V6_vwhist256q(SHORTCODE) \ #define fGEN_TCG_V6_vwhist256q(SHORTCODE) \
do { \ do { \
@ -69,13 +69,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
sizeof(MMVector), sizeof(MMVector)); \ sizeof(MMVector), sizeof(MMVector)); \
} else { \ } else { \
assert_vhist_tmp(ctx); \ assert_vhist_tmp(ctx); \
gen_helper_vwhist256q(cpu_env); \ gen_helper_vwhist256q(tcg_env); \
} \ } \
} while (0) } while (0)
#define fGEN_TCG_V6_vwhist256_sat(SHORTCODE) \ #define fGEN_TCG_V6_vwhist256_sat(SHORTCODE) \
if (!ctx->pre_commit) { \ if (!ctx->pre_commit) { \
assert_vhist_tmp(ctx); \ assert_vhist_tmp(ctx); \
gen_helper_vwhist256_sat(cpu_env); \ gen_helper_vwhist256_sat(tcg_env); \
} }
#define fGEN_TCG_V6_vwhist256q_sat(SHORTCODE) \ #define fGEN_TCG_V6_vwhist256q_sat(SHORTCODE) \
do { \ do { \
@ -85,13 +85,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
sizeof(MMVector), sizeof(MMVector)); \ sizeof(MMVector), sizeof(MMVector)); \
} else { \ } else { \
assert_vhist_tmp(ctx); \ assert_vhist_tmp(ctx); \
gen_helper_vwhist256q_sat(cpu_env); \ gen_helper_vwhist256q_sat(tcg_env); \
} \ } \
} while (0) } while (0)
#define fGEN_TCG_V6_vwhist128(SHORTCODE) \ #define fGEN_TCG_V6_vwhist128(SHORTCODE) \
if (!ctx->pre_commit) { \ if (!ctx->pre_commit) { \
assert_vhist_tmp(ctx); \ assert_vhist_tmp(ctx); \
gen_helper_vwhist128(cpu_env); \ gen_helper_vwhist128(tcg_env); \
} }
#define fGEN_TCG_V6_vwhist128q(SHORTCODE) \ #define fGEN_TCG_V6_vwhist128q(SHORTCODE) \
do { \ do { \
@ -101,14 +101,14 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
sizeof(MMVector), sizeof(MMVector)); \ sizeof(MMVector), sizeof(MMVector)); \
} else { \ } else { \
assert_vhist_tmp(ctx); \ assert_vhist_tmp(ctx); \
gen_helper_vwhist128q(cpu_env); \ gen_helper_vwhist128q(tcg_env); \
} \ } \
} while (0) } while (0)
#define fGEN_TCG_V6_vwhist128m(SHORTCODE) \ #define fGEN_TCG_V6_vwhist128m(SHORTCODE) \
if (!ctx->pre_commit) { \ if (!ctx->pre_commit) { \
TCGv tcgv_uiV = tcg_constant_tl(uiV); \ TCGv tcgv_uiV = tcg_constant_tl(uiV); \
assert_vhist_tmp(ctx); \ assert_vhist_tmp(ctx); \
gen_helper_vwhist128m(cpu_env, tcgv_uiV); \ gen_helper_vwhist128m(tcg_env, tcgv_uiV); \
} }
#define fGEN_TCG_V6_vwhist128qm(SHORTCODE) \ #define fGEN_TCG_V6_vwhist128qm(SHORTCODE) \
do { \ do { \
@ -119,7 +119,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
} else { \ } else { \
TCGv tcgv_uiV = tcg_constant_tl(uiV); \ TCGv tcgv_uiV = tcg_constant_tl(uiV); \
assert_vhist_tmp(ctx); \ assert_vhist_tmp(ctx); \
gen_helper_vwhist128qm(cpu_env, tcgv_uiV); \ gen_helper_vwhist128qm(tcg_env, tcgv_uiV); \
} \ } \
} while (0) } while (0)

36
target/hexagon/genptr.c
View File

@ -414,50 +414,50 @@ void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
tcg_gen_mov_tl(hex_store_val32[slot], src); tcg_gen_mov_tl(hex_store_val32[slot], src);
} }
void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) void gen_store1(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
{ {
gen_store32(vaddr, src, 1, slot); gen_store32(vaddr, src, 1, slot);
} }
void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) void gen_store1i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
{ {
TCGv tmp = tcg_constant_tl(src); TCGv tmp = tcg_constant_tl(src);
gen_store1(cpu_env, vaddr, tmp, slot); gen_store1(tcg_env, vaddr, tmp, slot);
} }
void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) void gen_store2(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
{ {
gen_store32(vaddr, src, 2, slot); gen_store32(vaddr, src, 2, slot);
} }
void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) void gen_store2i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
{ {
TCGv tmp = tcg_constant_tl(src); TCGv tmp = tcg_constant_tl(src);
gen_store2(cpu_env, vaddr, tmp, slot); gen_store2(tcg_env, vaddr, tmp, slot);
} }
void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) void gen_store4(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
{ {
gen_store32(vaddr, src, 4, slot); gen_store32(vaddr, src, 4, slot);
} }
void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) void gen_store4i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
{ {
TCGv tmp = tcg_constant_tl(src); TCGv tmp = tcg_constant_tl(src);
gen_store4(cpu_env, vaddr, tmp, slot); gen_store4(tcg_env, vaddr, tmp, slot);
} }
void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot) void gen_store8(TCGv_env tcg_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
{ {
tcg_gen_mov_tl(hex_store_addr[slot], vaddr); tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], 8); tcg_gen_movi_tl(hex_store_width[slot], 8);
tcg_gen_mov_i64(hex_store_val64[slot], src); tcg_gen_mov_i64(hex_store_val64[slot], src);
} }
void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot) void gen_store8i(TCGv_env tcg_env, TCGv vaddr, int64_t src, uint32_t slot)
{ {
TCGv_i64 tmp = tcg_constant_i64(src); TCGv_i64 tmp = tcg_constant_i64(src);
gen_store8(cpu_env, vaddr, tmp, slot); gen_store8(tcg_env, vaddr, tmp, slot);
} }
TCGv gen_8bitsof(TCGv result, TCGv value) TCGv gen_8bitsof(TCGv result, TCGv value)
@ -783,7 +783,7 @@ static void gen_allocframe(DisasContext *ctx, TCGv r29, int framesize)
TCGv_i64 frame; TCGv_i64 frame;
tcg_gen_addi_tl(r30, r29, -8); tcg_gen_addi_tl(r30, r29, -8);
frame = gen_frame_scramble(); frame = gen_frame_scramble();
gen_store8(cpu_env, r30, frame, ctx->insn->slot); gen_store8(tcg_env, r30, frame, ctx->insn->slot);
gen_log_reg_write(ctx, HEX_REG_FP, r30); gen_log_reg_write(ctx, HEX_REG_FP, r30);
gen_framecheck(r30, framesize); gen_framecheck(r30, framesize);
tcg_gen_subi_tl(r29, r30, framesize); tcg_gen_subi_tl(r29, r30, framesize);
@ -1239,7 +1239,7 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
for (int i = 0; i < sizeof(MMVector) / 8; i++) { for (int i = 0; i < sizeof(MMVector) / 8; i++) {
tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ); tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
tcg_gen_addi_tl(src, src, 8); tcg_gen_addi_tl(src, src, 8);
tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8); tcg_gen_st_i64(tmp, tcg_env, dstoff + i * 8);
} }
} }
@ -1251,7 +1251,7 @@ static void gen_vreg_store(DisasContext *ctx, TCGv EA, intptr_t srcoff,
if (is_gather_store_insn(ctx)) { if (is_gather_store_insn(ctx)) {
TCGv sl = tcg_constant_tl(slot); TCGv sl = tcg_constant_tl(slot);
gen_helper_gather_store(cpu_env, EA, sl); gen_helper_gather_store(tcg_env, EA, sl);
return; return;
} }
@ -1301,7 +1301,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff, intptr_t srcoff)
TCGv_i64 ones = tcg_constant_i64(~0); TCGv_i64 ones = tcg_constant_i64(~0);
for (int i = 0; i < sizeof(MMVector) / 8; i++) { for (int i = 0; i < sizeof(MMVector) / 8; i++) {
tcg_gen_ld_i64(tmp, cpu_env, srcoff + i * 8); tcg_gen_ld_i64(tmp, tcg_env, srcoff + i * 8);
tcg_gen_movi_i64(mask, 0); tcg_gen_movi_i64(mask, 0);
for (int j = 0; j < 8; j += size) { for (int j = 0; j < 8; j += size) {
@ -1310,7 +1310,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff, intptr_t srcoff)
tcg_gen_deposit_i64(mask, mask, bits, j, size); tcg_gen_deposit_i64(mask, mask, bits, j, size);
} }
tcg_gen_st8_i64(mask, cpu_env, dstoff + i); tcg_gen_st8_i64(mask, tcg_env, dstoff + i);
} }
} }
@ -1318,7 +1318,7 @@ void probe_noshuf_load(TCGv va, int s, int mi)
{ {
TCGv size = tcg_constant_tl(s); TCGv size = tcg_constant_tl(s);
TCGv mem_idx = tcg_constant_tl(mi); TCGv mem_idx = tcg_constant_tl(mi);
gen_helper_probe_noshuf_load(cpu_env, va, size, mem_idx); gen_helper_probe_noshuf_load(tcg_env, va, size, mem_idx);
} }
/* /*

2
target/hexagon/idef-parser/parser-helpers.c
View File

@ -1773,7 +1773,7 @@ void gen_store(Context *c, YYLTYPE *locp, HexValue *width, HexValue *ea,
/* Lookup the effective address EA */ /* Lookup the effective address EA */
find_variable(c, locp, ea, ea); find_variable(c, locp, ea, ea);
src_m = rvalue_materialize(c, locp, &src_m); src_m = rvalue_materialize(c, locp, &src_m);
OUT(c, locp, "gen_store", &mem_width, "(cpu_env, ", ea, ", ", &src_m); OUT(c, locp, "gen_store", &mem_width, "(tcg_env, ", ea, ", ", &src_m);
OUT(c, locp, ", insn->slot);\n"); OUT(c, locp, ", insn->slot);\n");
} }

8
target/hexagon/macros.h
View File

@ -147,7 +147,7 @@
__builtin_choose_expr(TYPE_TCGV(X), \ __builtin_choose_expr(TYPE_TCGV(X), \
gen_store1, (void)0)) gen_store1, (void)0))
#define MEM_STORE1(VA, DATA, SLOT) \ #define MEM_STORE1(VA, DATA, SLOT) \
MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT) MEM_STORE1_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#define MEM_STORE2_FUNC(X) \ #define MEM_STORE2_FUNC(X) \
__builtin_choose_expr(TYPE_INT(X), \ __builtin_choose_expr(TYPE_INT(X), \
@ -155,7 +155,7 @@
__builtin_choose_expr(TYPE_TCGV(X), \ __builtin_choose_expr(TYPE_TCGV(X), \
gen_store2, (void)0)) gen_store2, (void)0))
#define MEM_STORE2(VA, DATA, SLOT) \ #define MEM_STORE2(VA, DATA, SLOT) \
MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT) MEM_STORE2_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#define MEM_STORE4_FUNC(X) \ #define MEM_STORE4_FUNC(X) \
__builtin_choose_expr(TYPE_INT(X), \ __builtin_choose_expr(TYPE_INT(X), \
@ -163,7 +163,7 @@
__builtin_choose_expr(TYPE_TCGV(X), \ __builtin_choose_expr(TYPE_TCGV(X), \
gen_store4, (void)0)) gen_store4, (void)0))
#define MEM_STORE4(VA, DATA, SLOT) \ #define MEM_STORE4(VA, DATA, SLOT) \
MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT) MEM_STORE4_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#define MEM_STORE8_FUNC(X) \ #define MEM_STORE8_FUNC(X) \
__builtin_choose_expr(TYPE_INT(X), \ __builtin_choose_expr(TYPE_INT(X), \
@ -171,7 +171,7 @@
__builtin_choose_expr(TYPE_TCGV_I64(X), \ __builtin_choose_expr(TYPE_TCGV_I64(X), \
gen_store8, (void)0)) gen_store8, (void)0))
#define MEM_STORE8(VA, DATA, SLOT) \ #define MEM_STORE8(VA, DATA, SLOT) \
MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT) MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#else #else
#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA)) #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA)) #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA))

48
target/hexagon/translate.c
View File

@ -115,7 +115,7 @@ intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
static void gen_exception_raw(int excp) static void gen_exception_raw(int excp)
{ {
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
} }
static void gen_exec_counters(DisasContext *ctx) static void gen_exec_counters(DisasContext *ctx)
@ -528,7 +528,7 @@ static void gen_start_packet(DisasContext *ctx)
if (HEX_DEBUG) { if (HEX_DEBUG) {
/* Handy place to set a breakpoint before the packet executes */ /* Handy place to set a breakpoint before the packet executes */
gen_helper_debug_start_packet(cpu_env); gen_helper_debug_start_packet(tcg_env);
} }
/* Initialize the runtime state for packet semantics */ /* Initialize the runtime state for packet semantics */
@ -701,7 +701,7 @@ static void gen_check_store_width(DisasContext *ctx, int slot_num)
if (HEX_DEBUG) { if (HEX_DEBUG) {
TCGv slot = tcg_constant_tl(slot_num); TCGv slot = tcg_constant_tl(slot_num);
TCGv check = tcg_constant_tl(ctx->store_width[slot_num]); TCGv check = tcg_constant_tl(ctx->store_width[slot_num]);
gen_helper_debug_check_store_width(cpu_env, slot, check); gen_helper_debug_check_store_width(tcg_env, slot, check);
} }
} }
@ -783,7 +783,7 @@ void process_store(DisasContext *ctx, int slot_num)
* avoid branching based on the width at runtime. * avoid branching based on the width at runtime.
*/ */
TCGv slot = tcg_constant_tl(slot_num); TCGv slot = tcg_constant_tl(slot_num);
gen_helper_commit_store(cpu_env, slot); gen_helper_commit_store(tcg_env, slot);
} }
} }
} }
@ -882,7 +882,7 @@ static void gen_commit_hvx(DisasContext *ctx)
} }
if (pkt_has_hvx_store(ctx->pkt)) { if (pkt_has_hvx_store(ctx->pkt)) {
gen_helper_commit_hvx_stores(cpu_env); gen_helper_commit_hvx_stores(tcg_env);
} }
} }
@ -942,7 +942,7 @@ static void gen_commit_packet(DisasContext *ctx)
} else if (has_hvx_store) { } else if (has_hvx_store) {
if (!has_store_s0 && !has_store_s1) { if (!has_store_s0 && !has_store_s1) {
TCGv mem_idx = tcg_constant_tl(ctx->mem_idx); TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
gen_helper_probe_hvx_stores(cpu_env, mem_idx); gen_helper_probe_hvx_stores(tcg_env, mem_idx);
} else { } else {
int mask = 0; int mask = 0;
@ -971,7 +971,7 @@ static void gen_commit_packet(DisasContext *ctx)
} }
mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX,
ctx->mem_idx); ctx->mem_idx);
gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, gen_helper_probe_pkt_scalar_hvx_stores(tcg_env,
tcg_constant_tl(mask)); tcg_constant_tl(mask));
} }
} else if (has_store_s0 && has_store_s1) { } else if (has_store_s0 && has_store_s1) {
@ -987,7 +987,7 @@ static void gen_commit_packet(DisasContext *ctx)
FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1); FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1);
} }
TCGv args_tcgv = tcg_constant_tl(args); TCGv args_tcgv = tcg_constant_tl(args);
gen_helper_probe_pkt_scalar_store_s0(cpu_env, args_tcgv); gen_helper_probe_pkt_scalar_store_s0(tcg_env, args_tcgv);
} }
process_store_log(ctx); process_store_log(ctx);
@ -1005,7 +1005,7 @@ static void gen_commit_packet(DisasContext *ctx)
tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa);
/* Handy place to set a breakpoint at the end of execution */ /* Handy place to set a breakpoint at the end of execution */
gen_helper_debug_commit_end(cpu_env, tcg_constant_tl(ctx->pkt->pc), gen_helper_debug_commit_end(tcg_env, tcg_constant_tl(ctx->pkt->pc),
ctx->pred_written, has_st0, has_st1); ctx->pred_written, has_st0, has_st1);
} }
@ -1179,68 +1179,68 @@ void hexagon_translate_init(void)
opcode_init(); opcode_init();
for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
hex_gpr[i] = tcg_global_mem_new(cpu_env, hex_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, gpr[i]), offsetof(CPUHexagonState, gpr[i]),
hexagon_regnames[i]); hexagon_regnames[i]);
if (HEX_DEBUG) { if (HEX_DEBUG) {
snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
hexagon_regnames[i]); hexagon_regnames[i]);
hex_reg_written[i] = tcg_global_mem_new(cpu_env, hex_reg_written[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, reg_written[i]), offsetof(CPUHexagonState, reg_written[i]),
reg_written_names[i]); reg_written_names[i]);
} }
} }
hex_new_value_usr = tcg_global_mem_new(cpu_env, hex_new_value_usr = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); offsetof(CPUHexagonState, new_value_usr), "new_value_usr");
for (i = 0; i < NUM_PREGS; i++) { for (i = 0; i < NUM_PREGS; i++) {
hex_pred[i] = tcg_global_mem_new(cpu_env, hex_pred[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, pred[i]), offsetof(CPUHexagonState, pred[i]),
hexagon_prednames[i]); hexagon_prednames[i]);
} }
hex_slot_cancelled = tcg_global_mem_new(cpu_env, hex_slot_cancelled = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled");
hex_llsc_addr = tcg_global_mem_new(cpu_env, hex_llsc_addr = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); offsetof(CPUHexagonState, llsc_addr), "llsc_addr");
hex_llsc_val = tcg_global_mem_new(cpu_env, hex_llsc_val = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, llsc_val), "llsc_val"); offsetof(CPUHexagonState, llsc_val), "llsc_val");
hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env, hex_llsc_val_i64 = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64");
for (i = 0; i < STORES_MAX; i++) { for (i = 0; i < STORES_MAX; i++) {
snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i);
hex_store_addr[i] = tcg_global_mem_new(cpu_env, hex_store_addr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, mem_log_stores[i].va), offsetof(CPUHexagonState, mem_log_stores[i].va),
store_addr_names[i]); store_addr_names[i]);
snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i);
hex_store_width[i] = tcg_global_mem_new(cpu_env, hex_store_width[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, mem_log_stores[i].width), offsetof(CPUHexagonState, mem_log_stores[i].width),
store_width_names[i]); store_width_names[i]);
snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i);
hex_store_val32[i] = tcg_global_mem_new(cpu_env, hex_store_val32[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, mem_log_stores[i].data32), offsetof(CPUHexagonState, mem_log_stores[i].data32),
store_val32_names[i]); store_val32_names[i]);
snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i);
hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env, hex_store_val64[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHexagonState, mem_log_stores[i].data64), offsetof(CPUHexagonState, mem_log_stores[i].data64),
store_val64_names[i]); store_val64_names[i]);
} }
for (int i = 0; i < VSTORES_MAX; i++) { for (int i = 0; i < VSTORES_MAX; i++) {
snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i);
hex_vstore_addr[i] = tcg_global_mem_new(cpu_env, hex_vstore_addr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, vstore[i].va), offsetof(CPUHexagonState, vstore[i].va),
vstore_addr_names[i]); vstore_addr_names[i]);
snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i); snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i);
hex_vstore_size[i] = tcg_global_mem_new(cpu_env, hex_vstore_size[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, vstore[i].size), offsetof(CPUHexagonState, vstore[i].size),
vstore_size_names[i]); vstore_size_names[i]);
snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i); snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i);
hex_vstore_pending[i] = tcg_global_mem_new(cpu_env, hex_vstore_pending[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, vstore_pending[i]), offsetof(CPUHexagonState, vstore_pending[i]),
vstore_pending_names[i]); vstore_pending_names[i]);
} }

157
target/hppa/translate.c
View File

@ -396,28 +396,28 @@ void hppa_translate_init(void)
cpu_gr[0] = NULL; cpu_gr[0] = NULL;
for (i = 1; i < 32; i++) { for (i = 1; i < 32; i++) {
cpu_gr[i] = tcg_global_mem_new(cpu_env, cpu_gr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHPPAState, gr[i]), offsetof(CPUHPPAState, gr[i]),
gr_names[i]); gr_names[i]);
} }
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
cpu_sr[i] = tcg_global_mem_new_i64(cpu_env, cpu_sr[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHPPAState, sr[i]), offsetof(CPUHPPAState, sr[i]),
sr_names[i]); sr_names[i]);
} }
cpu_srH = tcg_global_mem_new_i64(cpu_env, cpu_srH = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHPPAState, sr[4]), offsetof(CPUHPPAState, sr[4]),
sr_names[4]); sr_names[4]);
for (i = 0; i < ARRAY_SIZE(vars); ++i) { for (i = 0; i < ARRAY_SIZE(vars); ++i) {
const GlobalVar *v = &vars[i]; const GlobalVar *v = &vars[i];
*v->var = tcg_global_mem_new(cpu_env, v->ofs, v->name); *v->var = tcg_global_mem_new(tcg_env, v->ofs, v->name);
} }
cpu_iasq_f = tcg_global_mem_new_i64(cpu_env, cpu_iasq_f = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHPPAState, iasq_f), offsetof(CPUHPPAState, iasq_f),
"iasq_f"); "iasq_f");
cpu_iasq_b = tcg_global_mem_new_i64(cpu_env, cpu_iasq_b = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHPPAState, iasq_b), offsetof(CPUHPPAState, iasq_b),
"iasq_b"); "iasq_b");
} }
@ -563,7 +563,7 @@ static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t)
static TCGv_i32 load_frw_i32(unsigned rt) static TCGv_i32 load_frw_i32(unsigned rt)
{ {
TCGv_i32 ret = tcg_temp_new_i32(); TCGv_i32 ret = tcg_temp_new_i32();
tcg_gen_ld_i32(ret, cpu_env, tcg_gen_ld_i32(ret, tcg_env,
offsetof(CPUHPPAState, fr[rt & 31]) offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS)); + (rt & 32 ? LO_OFS : HI_OFS));
return ret; return ret;
@ -586,7 +586,7 @@ static TCGv_i64 load_frw0_i64(unsigned rt)
if (rt == 0) { if (rt == 0) {
tcg_gen_movi_i64(ret, 0); tcg_gen_movi_i64(ret, 0);
} else { } else {
tcg_gen_ld32u_i64(ret, cpu_env, tcg_gen_ld32u_i64(ret, tcg_env,
offsetof(CPUHPPAState, fr[rt & 31]) offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS)); + (rt & 32 ? LO_OFS : HI_OFS));
} }
@ -595,7 +595,7 @@ static TCGv_i64 load_frw0_i64(unsigned rt)
static void save_frw_i32(unsigned rt, TCGv_i32 val) static void save_frw_i32(unsigned rt, TCGv_i32 val)
{ {
tcg_gen_st_i32(val, cpu_env, tcg_gen_st_i32(val, tcg_env,
offsetof(CPUHPPAState, fr[rt & 31]) offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS)); + (rt & 32 ? LO_OFS : HI_OFS));
} }
@ -606,7 +606,7 @@ static void save_frw_i32(unsigned rt, TCGv_i32 val)
static TCGv_i64 load_frd(unsigned rt) static TCGv_i64 load_frd(unsigned rt)
{ {
TCGv_i64 ret = tcg_temp_new_i64(); TCGv_i64 ret = tcg_temp_new_i64();
tcg_gen_ld_i64(ret, cpu_env, offsetof(CPUHPPAState, fr[rt])); tcg_gen_ld_i64(ret, tcg_env, offsetof(CPUHPPAState, fr[rt]));
return ret; return ret;
} }
@ -623,7 +623,7 @@ static TCGv_i64 load_frd0(unsigned rt)
static void save_frd(unsigned rt, TCGv_i64 val) static void save_frd(unsigned rt, TCGv_i64 val)
{ {
tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt])); tcg_gen_st_i64(val, tcg_env, offsetof(CPUHPPAState, fr[rt]));
} }
static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg)
@ -636,7 +636,7 @@ static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg)
} else if (ctx->tb_flags & TB_FLAG_SR_SAME) { } else if (ctx->tb_flags & TB_FLAG_SR_SAME) {
tcg_gen_mov_i64(dest, cpu_srH); tcg_gen_mov_i64(dest, cpu_srH);
} else { } else {
tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); tcg_gen_ld_i64(dest, tcg_env, offsetof(CPUHPPAState, sr[reg]));
} }
#endif #endif
} }
@ -752,7 +752,7 @@ static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp)
static void gen_excp_1(int exception) static void gen_excp_1(int exception)
{ {
gen_helper_excp(cpu_env, tcg_constant_i32(exception)); gen_helper_excp(tcg_env, tcg_constant_i32(exception));
} }
static void gen_excp(DisasContext *ctx, int exception) static void gen_excp(DisasContext *ctx, int exception)
@ -768,7 +768,7 @@ static bool gen_excp_iir(DisasContext *ctx, int exc)
{ {
nullify_over(ctx); nullify_over(ctx);
tcg_gen_st_reg(tcg_constant_reg(ctx->insn), tcg_gen_st_reg(tcg_constant_reg(ctx->insn),
cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); tcg_env, offsetof(CPUHPPAState, cr[CR_IIR]));
gen_excp(ctx, exc); gen_excp(ctx, exc);
return nullify_end(ctx); return nullify_end(ctx);
} }
@ -1138,7 +1138,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
sv = do_add_sv(ctx, dest, in1, in2); sv = do_add_sv(ctx, dest, in1, in2);
if (is_tsv) { if (is_tsv) {
/* ??? Need to include overflow from shift. */ /* ??? Need to include overflow from shift. */
gen_helper_tsv(cpu_env, sv); gen_helper_tsv(tcg_env, sv);
} }
} }
@ -1147,7 +1147,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
if (is_tc) { if (is_tc) {
tmp = tcg_temp_new(); tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(cpu_env, tmp); gen_helper_tcond(tcg_env, tmp);
} }
/* Write back the result. */ /* Write back the result. */
@ -1224,7 +1224,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
if (is_tsv || cond_need_sv(c)) { if (is_tsv || cond_need_sv(c)) {
sv = do_sub_sv(ctx, dest, in1, in2); sv = do_sub_sv(ctx, dest, in1, in2);
if (is_tsv) { if (is_tsv) {
gen_helper_tsv(cpu_env, sv); gen_helper_tsv(tcg_env, sv);
} }
} }
@ -1239,7 +1239,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
if (is_tc) { if (is_tc) {
tmp = tcg_temp_new(); tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(cpu_env, tmp); gen_helper_tcond(tcg_env, tmp);
} }
/* Write back the result. */ /* Write back the result. */
@ -1358,7 +1358,7 @@ static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
if (is_tc) { if (is_tc) {
TCGv_reg tmp = tcg_temp_new(); TCGv_reg tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(cpu_env, tmp); gen_helper_tcond(tcg_env, tmp);
} }
save_gpr(ctx, rt, dest); save_gpr(ctx, rt, dest);
@ -1398,7 +1398,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
tcg_gen_andi_reg(tmp, tmp, 030); tcg_gen_andi_reg(tmp, tmp, 030);
tcg_gen_trunc_reg_ptr(ptr, tmp); tcg_gen_trunc_reg_ptr(ptr, tmp);
tcg_gen_add_ptr(ptr, ptr, cpu_env); tcg_gen_add_ptr(ptr, ptr, tcg_env);
tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4]));
return spc; return spc;
@ -1559,7 +1559,7 @@ static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb,
save_frw_i32(rt, tmp); save_frw_i32(rt, tmp);
if (rt == 0) { if (rt == 0) {
gen_helper_loaded_fr0(cpu_env); gen_helper_loaded_fr0(tcg_env);
} }
return nullify_end(ctx); return nullify_end(ctx);
@ -1584,7 +1584,7 @@ static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb,
save_frd(rt, tmp); save_frd(rt, tmp);
if (rt == 0) { if (rt == 0) {
gen_helper_loaded_fr0(cpu_env); gen_helper_loaded_fr0(tcg_env);
} }
return nullify_end(ctx); return nullify_end(ctx);
@ -1653,7 +1653,7 @@ static bool do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra,
nullify_over(ctx); nullify_over(ctx);
tmp = load_frw0_i32(ra); tmp = load_frw0_i32(ra);
func(tmp, cpu_env, tmp); func(tmp, tcg_env, tmp);
save_frw_i32(rt, tmp); save_frw_i32(rt, tmp);
return nullify_end(ctx); return nullify_end(ctx);
@ -1669,7 +1669,7 @@ static bool do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra,
src = load_frd(ra); src = load_frd(ra);
dst = tcg_temp_new_i32(); dst = tcg_temp_new_i32();
func(dst, cpu_env, src); func(dst, tcg_env, src);
save_frw_i32(rt, dst); save_frw_i32(rt, dst);
return nullify_end(ctx); return nullify_end(ctx);
@ -1683,7 +1683,7 @@ static bool do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra,
nullify_over(ctx); nullify_over(ctx);
tmp = load_frd0(ra); tmp = load_frd0(ra);
func(tmp, cpu_env, tmp); func(tmp, tcg_env, tmp);
save_frd(rt, tmp); save_frd(rt, tmp);
return nullify_end(ctx); return nullify_end(ctx);
@ -1699,7 +1699,7 @@ static bool do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra,
src = load_frw0_i32(ra); src = load_frw0_i32(ra);
dst = tcg_temp_new_i64(); dst = tcg_temp_new_i64();
func(dst, cpu_env, src); func(dst, tcg_env, src);
save_frd(rt, dst); save_frd(rt, dst);
return nullify_end(ctx); return nullify_end(ctx);
@ -1715,7 +1715,7 @@ static bool do_fop_weww(DisasContext *ctx, unsigned rt,
a = load_frw0_i32(ra); a = load_frw0_i32(ra);
b = load_frw0_i32(rb); b = load_frw0_i32(rb);
func(a, cpu_env, a, b); func(a, tcg_env, a, b);
save_frw_i32(rt, a); save_frw_i32(rt, a);
return nullify_end(ctx); return nullify_end(ctx);
@ -1731,7 +1731,7 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt,
a = load_frd0(ra); a = load_frd0(ra);
b = load_frd0(rb); b = load_frd0(rb);
func(a, cpu_env, a, b); func(a, tcg_env, a, b);
save_frd(rt, a); save_frd(rt, a);
return nullify_end(ctx); return nullify_end(ctx);
@ -1996,7 +1996,7 @@ static void do_page_zero(DisasContext *ctx)
break; break;
case 0xe0: /* SET_THREAD_POINTER */ case 0xe0: /* SET_THREAD_POINTER */
tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27])); tcg_gen_st_reg(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27]));
tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3); tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3);
tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4);
ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
@ -2105,7 +2105,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
} }
tmp = get_temp(ctx); tmp = get_temp(ctx);
tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
save_gpr(ctx, rt, tmp); save_gpr(ctx, rt, tmp);
done: done:
@ -2129,7 +2129,7 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a)
tcg_gen_shli_i64(t64, t64, 32); tcg_gen_shli_i64(t64, t64, 32);
if (rs >= 4) { if (rs >= 4) {
tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); tcg_gen_st_i64(t64, tcg_env, offsetof(CPUHPPAState, sr[rs]));
ctx->tb_flags &= ~TB_FLAG_SR_SAME; ctx->tb_flags &= ~TB_FLAG_SR_SAME;
} else { } else {
tcg_gen_mov_i64(cpu_sr[rs], t64); tcg_gen_mov_i64(cpu_sr[rs], t64);
@ -2163,13 +2163,13 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
switch (ctl) { switch (ctl) {
case CR_IT: case CR_IT:
gen_helper_write_interval_timer(cpu_env, reg); gen_helper_write_interval_timer(tcg_env, reg);
break; break;
case CR_EIRR: case CR_EIRR:
gen_helper_write_eirr(cpu_env, reg); gen_helper_write_eirr(tcg_env, reg);
break; break;
case CR_EIEM: case CR_EIEM:
gen_helper_write_eiem(cpu_env, reg); gen_helper_write_eiem(tcg_env, reg);
ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
break; break;
@ -2178,10 +2178,10 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
/* FIXME: Respect PSW_Q bit */ /* FIXME: Respect PSW_Q bit */
/* The write advances the queue and stores to the back element. */ /* The write advances the queue and stores to the back element. */
tmp = get_temp(ctx); tmp = get_temp(ctx);
tcg_gen_ld_reg(tmp, cpu_env, tcg_gen_ld_reg(tmp, tcg_env,
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
tcg_gen_st_reg(reg, cpu_env, tcg_gen_st_reg(reg, tcg_env,
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
break; break;
@ -2189,14 +2189,14 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
case CR_PID2: case CR_PID2:
case CR_PID3: case CR_PID3:
case CR_PID4: case CR_PID4:
tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_helper_change_prot_id(cpu_env); gen_helper_change_prot_id(tcg_env);
#endif #endif
break; break;
default: default:
tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
break; break;
} }
return nullify_end(ctx); return nullify_end(ctx);
@ -2244,9 +2244,9 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a)
nullify_over(ctx); nullify_over(ctx);
tmp = get_temp(ctx); tmp = get_temp(ctx);
tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw));
tcg_gen_andi_reg(tmp, tmp, ~a->i); tcg_gen_andi_reg(tmp, tmp, ~a->i);
gen_helper_swap_system_mask(tmp, cpu_env, tmp); gen_helper_swap_system_mask(tmp, tcg_env, tmp);
save_gpr(ctx, a->t, tmp); save_gpr(ctx, a->t, tmp);
/* Exit the TB to recognize new interrupts, e.g. PSW_M. */ /* Exit the TB to recognize new interrupts, e.g. PSW_M. */
@ -2264,9 +2264,9 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a)
nullify_over(ctx); nullify_over(ctx);
tmp = get_temp(ctx); tmp = get_temp(ctx);
tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw));
tcg_gen_ori_reg(tmp, tmp, a->i); tcg_gen_ori_reg(tmp, tmp, a->i);
gen_helper_swap_system_mask(tmp, cpu_env, tmp); gen_helper_swap_system_mask(tmp, tcg_env, tmp);
save_gpr(ctx, a->t, tmp); save_gpr(ctx, a->t, tmp);
/* Exit the TB to recognize new interrupts, e.g. PSW_I. */ /* Exit the TB to recognize new interrupts, e.g. PSW_I. */
@ -2284,7 +2284,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a)
reg = load_gpr(ctx, a->r); reg = load_gpr(ctx, a->r);
tmp = get_temp(ctx); tmp = get_temp(ctx);
gen_helper_swap_system_mask(tmp, cpu_env, reg); gen_helper_swap_system_mask(tmp, tcg_env, reg);
/* Exit the TB to recognize new interrupts. */ /* Exit the TB to recognize new interrupts. */
ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
@ -2299,9 +2299,9 @@ static bool do_rfi(DisasContext *ctx, bool rfi_r)
nullify_over(ctx); nullify_over(ctx);
if (rfi_r) { if (rfi_r) {
gen_helper_rfi_r(cpu_env); gen_helper_rfi_r(tcg_env);
} else { } else {
gen_helper_rfi(cpu_env); gen_helper_rfi(tcg_env);
} }
/* Exit the TB to recognize new interrupts. */ /* Exit the TB to recognize new interrupts. */
tcg_gen_exit_tb(NULL, 0); tcg_gen_exit_tb(NULL, 0);
@ -2326,7 +2326,7 @@ static bool trans_halt(DisasContext *ctx, arg_halt *a)
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
nullify_over(ctx); nullify_over(ctx);
gen_helper_halt(cpu_env); gen_helper_halt(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx); return nullify_end(ctx);
#endif #endif
@ -2337,7 +2337,7 @@ static bool trans_reset(DisasContext *ctx, arg_reset *a)
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
nullify_over(ctx); nullify_over(ctx);
gen_helper_reset(cpu_env); gen_helper_reset(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx); return nullify_end(ctx);
#endif #endif
@ -2348,7 +2348,7 @@ static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a)
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
nullify_over(ctx); nullify_over(ctx);
gen_helper_getshadowregs(cpu_env); gen_helper_getshadowregs(tcg_env);
return nullify_end(ctx); return nullify_end(ctx);
#endif #endif
} }
@ -2388,7 +2388,7 @@ static bool trans_probe(DisasContext *ctx, arg_probe *a)
} }
want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ);
gen_helper_probe(dest, cpu_env, addr, level, want); gen_helper_probe(dest, tcg_env, addr, level, want);
save_gpr(ctx, a->t, dest); save_gpr(ctx, a->t, dest);
return nullify_end(ctx); return nullify_end(ctx);
@ -2406,9 +2406,9 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false);
reg = load_gpr(ctx, a->r); reg = load_gpr(ctx, a->r);
if (a->addr) { if (a->addr) {
gen_helper_itlba(cpu_env, addr, reg); gen_helper_itlba(tcg_env, addr, reg);
} else { } else {
gen_helper_itlbp(cpu_env, addr, reg); gen_helper_itlbp(tcg_env, addr, reg);
} }
/* Exit TB for TLB change if mmu is enabled. */ /* Exit TB for TLB change if mmu is enabled. */
@ -2433,9 +2433,9 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a)
save_gpr(ctx, a->b, ofs); save_gpr(ctx, a->b, ofs);
} }
if (a->local) { if (a->local) {
gen_helper_ptlbe(cpu_env); gen_helper_ptlbe(tcg_env);
} else { } else {
gen_helper_ptlb(cpu_env, addr); gen_helper_ptlb(tcg_env, addr);
} }
/* Exit TB for TLB change if mmu is enabled. */ /* Exit TB for TLB change if mmu is enabled. */
@ -2473,10 +2473,10 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
stl = tcg_temp_new_tl(); stl = tcg_temp_new_tl();
addr = tcg_temp_new_tl(); addr = tcg_temp_new_tl();
tcg_gen_ld32u_i64(stl, cpu_env, tcg_gen_ld32u_i64(stl, tcg_env,
a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) a->data ? offsetof(CPUHPPAState, cr[CR_ISR])
: offsetof(CPUHPPAState, cr[CR_IIASQ])); : offsetof(CPUHPPAState, cr[CR_IIASQ]));
tcg_gen_ld32u_i64(atl, cpu_env, tcg_gen_ld32u_i64(atl, tcg_env,
a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) a->data ? offsetof(CPUHPPAState, cr[CR_IOR])
: offsetof(CPUHPPAState, cr[CR_IIAOQ])); : offsetof(CPUHPPAState, cr[CR_IIAOQ]));
tcg_gen_shli_i64(stl, stl, 32); tcg_gen_shli_i64(stl, stl, 32);
@ -2484,9 +2484,9 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
reg = load_gpr(ctx, a->r); reg = load_gpr(ctx, a->r);
if (a->addr) { if (a->addr) {
gen_helper_itlba(cpu_env, addr, reg); gen_helper_itlba(tcg_env, addr, reg);
} else { } else {
gen_helper_itlbp(cpu_env, addr, reg); gen_helper_itlbp(tcg_env, addr, reg);
} }
/* Exit TB for TLB change if mmu is enabled. */ /* Exit TB for TLB change if mmu is enabled. */
@ -2509,7 +2509,7 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false);
paddr = tcg_temp_new(); paddr = tcg_temp_new();
gen_helper_lpa(paddr, cpu_env, vaddr); gen_helper_lpa(paddr, tcg_env, vaddr);
/* Note that physical address result overrides base modification. */ /* Note that physical address result overrides base modification. */
if (a->m) { if (a->m) {
@ -2640,7 +2640,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a)
nullify_set(ctx, 0); nullify_set(ctx, 0);
/* Tell the qemu main loop to halt until this cpu has work. */ /* Tell the qemu main loop to halt until this cpu has work. */
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
offsetof(CPUState, halted) - offsetof(HPPACPU, env)); offsetof(CPUState, halted) - offsetof(HPPACPU, env));
gen_excp_1(EXCP_HALTED); gen_excp_1(EXCP_HALTED);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
@ -2907,15 +2907,15 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a)
val = load_gpr(ctx, a->r); val = load_gpr(ctx, a->r);
if (a->a) { if (a->a) {
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
gen_helper_stby_e_parallel(cpu_env, addr, val); gen_helper_stby_e_parallel(tcg_env, addr, val);
} else { } else {
gen_helper_stby_e(cpu_env, addr, val); gen_helper_stby_e(tcg_env, addr, val);
} }
} else { } else {
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
gen_helper_stby_b_parallel(cpu_env, addr, val); gen_helper_stby_b_parallel(tcg_env, addr, val);
} else { } else {
gen_helper_stby_b(cpu_env, addr, val); gen_helper_stby_b(tcg_env, addr, val);
} }
} }
if (a->m) { if (a->m) {
@ -3806,7 +3806,7 @@ static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a)
ty = tcg_constant_i32(a->y); ty = tcg_constant_i32(a->y);
tc = tcg_constant_i32(a->c); tc = tcg_constant_i32(a->c);
gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc); gen_helper_fcmp_s(tcg_env, ta, tb, ty, tc);
return nullify_end(ctx); return nullify_end(ctx);
} }
@ -3823,7 +3823,7 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a)
ty = tcg_constant_i32(a->y); ty = tcg_constant_i32(a->y);
tc = tcg_constant_i32(a->c); tc = tcg_constant_i32(a->c);
gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc); gen_helper_fcmp_d(tcg_env, ta, tb, ty, tc);
return nullify_end(ctx); return nullify_end(ctx);
} }
@ -3835,7 +3835,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
nullify_over(ctx); nullify_over(ctx);
t = get_temp(ctx); t = get_temp(ctx);
tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow));
if (a->y == 1) { if (a->y == 1) {
int mask; int mask;
@ -4012,9 +4012,9 @@ static bool trans_fmpyfadd_f(DisasContext *ctx, arg_fmpyfadd_f *a)
z = load_frw0_i32(a->ra3); z = load_frw0_i32(a->ra3);
if (a->neg) { if (a->neg) {
gen_helper_fmpynfadd_s(x, cpu_env, x, y, z); gen_helper_fmpynfadd_s(x, tcg_env, x, y, z);
} else { } else {
gen_helper_fmpyfadd_s(x, cpu_env, x, y, z); gen_helper_fmpyfadd_s(x, tcg_env, x, y, z);
} }
save_frw_i32(a->t, x); save_frw_i32(a->t, x);
@ -4031,9 +4031,9 @@ static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a)
z = load_frd0(a->ra3); z = load_frd0(a->ra3);
if (a->neg) { if (a->neg) {
gen_helper_fmpynfadd_d(x, cpu_env, x, y, z); gen_helper_fmpynfadd_d(x, tcg_env, x, y, z);
} else { } else {
gen_helper_fmpyfadd_d(x, cpu_env, x, y, z); gen_helper_fmpyfadd_d(x, tcg_env, x, y, z);
} }
save_frd(a->t, x); save_frd(a->t, x);
@ -4042,19 +4042,18 @@ static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a)
static bool trans_diag(DisasContext *ctx, arg_diag *a) static bool trans_diag(DisasContext *ctx, arg_diag *a)
{ {
nullify_over(ctx);
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (a->i == 0x100) { if (a->i == 0x100) {
/* emulate PDC BTLB, called by SeaBIOS-hppa */ /* emulate PDC BTLB, called by SeaBIOS-hppa */
gen_helper_diag_btlb(cpu_env); nullify_over(ctx);
} else gen_helper_diag_btlb(tcg_env);
#endif
{
qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i);
}
return nullify_end(ctx); return nullify_end(ctx);
} }
#endif
qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i);
return true;
}
static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{ {

2
target/i386/tcg/decode-new.c.inc
View File

@ -1822,7 +1822,7 @@ static void disas_insn_new(DisasContext *s, CPUState *cpu, int b)
} }
if (decode.e.special == X86_SPECIAL_MMX && if (decode.e.special == X86_SPECIAL_MMX &&
!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) { !(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
gen_helper_enter_mmx(cpu_env); gen_helper_enter_mmx(tcg_env);
} }
if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) { if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) {

262
target/i386/tcg/emit.c.inc
View File

@ -175,15 +175,15 @@ static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs, boo
switch(ot) { switch(ot) {
case MO_8: case MO_8:
gen_op_ld_v(s, MO_8, temp, s->A0); gen_op_ld_v(s, MO_8, temp, s->A0);
tcg_gen_st8_tl(temp, cpu_env, dest_ofs); tcg_gen_st8_tl(temp, tcg_env, dest_ofs);
break; break;
case MO_16: case MO_16:
gen_op_ld_v(s, MO_16, temp, s->A0); gen_op_ld_v(s, MO_16, temp, s->A0);
tcg_gen_st16_tl(temp, cpu_env, dest_ofs); tcg_gen_st16_tl(temp, tcg_env, dest_ofs);
break; break;
case MO_32: case MO_32:
gen_op_ld_v(s, MO_32, temp, s->A0); gen_op_ld_v(s, MO_32, temp, s->A0);
tcg_gen_st32_tl(temp, cpu_env, dest_ofs); tcg_gen_st32_tl(temp, tcg_env, dest_ofs);
break; break;
case MO_64: case MO_64:
gen_ldq_env_A0(s, dest_ofs); gen_ldq_env_A0(s, dest_ofs);
@ -226,14 +226,14 @@ static void gen_load(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v)
case X86_OP_SKIP: case X86_OP_SKIP:
return; return;
case X86_OP_SEG: case X86_OP_SEG:
tcg_gen_ld32u_tl(v, cpu_env, tcg_gen_ld32u_tl(v, tcg_env,
offsetof(CPUX86State,segs[op->n].selector)); offsetof(CPUX86State,segs[op->n].selector));
break; break;
case X86_OP_CR: case X86_OP_CR:
tcg_gen_ld_tl(v, cpu_env, offsetof(CPUX86State, cr[op->n])); tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, cr[op->n]));
break; break;
case X86_OP_DR: case X86_OP_DR:
tcg_gen_ld_tl(v, cpu_env, offsetof(CPUX86State, dr[op->n])); tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, dr[op->n]));
break; break;
case X86_OP_INT: case X86_OP_INT:
if (op->has_ea) { if (op->has_ea) {
@ -273,7 +273,7 @@ static TCGv_ptr op_ptr(X86DecodedInsn *decode, int opn)
op->v_ptr = tcg_temp_new_ptr(); op->v_ptr = tcg_temp_new_ptr();
/* The temporary points to the MMXReg or ZMMReg. */ /* The temporary points to the MMXReg or ZMMReg. */
tcg_gen_addi_ptr(op->v_ptr, cpu_env, vector_reg_offset(op)); tcg_gen_addi_ptr(op->v_ptr, tcg_env, vector_reg_offset(op));
return op->v_ptr; return op->v_ptr;
} }
@ -400,12 +400,12 @@ static void gen_3dnow(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
return; return;
} }
gen_helper_enter_mmx(cpu_env); gen_helper_enter_mmx(tcg_env);
if (fn == FN_3DNOW_MOVE) { if (fn == FN_3DNOW_MOVE) {
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset); tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset);
tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset); tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset);
} else { } else {
fn(cpu_env, OP_PTR0, OP_PTR1); fn(tcg_env, OP_PTR0, OP_PTR1);
} }
} }
@ -426,7 +426,7 @@ static inline void gen_unary_fp_sse(DisasContext *s, CPUX86State *env, X86Decode
gen_illegal_opcode(s); gen_illegal_opcode(s);
return; return;
} }
fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} else { } else {
SSEFunc_0_epp ps, pd, fn; SSEFunc_0_epp ps, pd, fn;
ps = s->vex_l ? ps_ymm : ps_xmm; ps = s->vex_l ? ps_ymm : ps_xmm;
@ -436,7 +436,7 @@ static inline void gen_unary_fp_sse(DisasContext *s, CPUX86State *env, X86Decode
gen_illegal_opcode(s); gen_illegal_opcode(s);
return; return;
} }
fn(cpu_env, OP_PTR0, OP_PTR2); fn(tcg_env, OP_PTR0, OP_PTR2);
} }
} }
#define UNARY_FP_SSE(uname, lname) \ #define UNARY_FP_SSE(uname, lname) \
@ -472,7 +472,7 @@ static inline void gen_fp_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn
fn = s->prefix & PREFIX_DATA ? pd : ps; fn = s->prefix & PREFIX_DATA ? pd : ps;
} }
if (fn) { if (fn) {
fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} else { } else {
gen_illegal_opcode(s); gen_illegal_opcode(s);
} }
@ -503,7 +503,7 @@ static void gen_##uname##Px(DisasContext *s, CPUX86State *env, X86DecodedInsn *d
SSEFunc_0_eppppii ymm = s->vex_w ? gen_helper_fma4pd_ymm : gen_helper_fma4ps_ymm; \ SSEFunc_0_eppppii ymm = s->vex_w ? gen_helper_fma4pd_ymm : gen_helper_fma4ps_ymm; \
SSEFunc_0_eppppii fn = s->vex_l ? ymm : xmm; \ SSEFunc_0_eppppii fn = s->vex_l ? ymm : xmm; \
\ \
fn(cpu_env, OP_PTR0, ptr0, ptr1, ptr2, \ fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \
tcg_constant_i32(even), \ tcg_constant_i32(even), \
tcg_constant_i32((even) ^ (odd))); \ tcg_constant_i32((even) ^ (odd))); \
} }
@ -514,7 +514,7 @@ static void gen_##uname##Sx(DisasContext *s, CPUX86State *env, X86DecodedInsn *d
{ \ { \
SSEFunc_0_eppppi fn = s->vex_w ? gen_helper_fma4sd : gen_helper_fma4ss; \ SSEFunc_0_eppppi fn = s->vex_w ? gen_helper_fma4sd : gen_helper_fma4ss; \
\ \
fn(cpu_env, OP_PTR0, ptr0, ptr1, ptr2, \ fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \
tcg_constant_i32(flags)); \ tcg_constant_i32(flags)); \
} \ } \
@ -571,13 +571,13 @@ static inline void gen_unary_fp32_sse(DisasContext *s, CPUX86State *env, X86Deco
if (!ss) { if (!ss) {
goto illegal_op; goto illegal_op;
} }
ss(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} else { } else {
SSEFunc_0_epp fn = s->vex_l ? ps_ymm : ps_xmm; SSEFunc_0_epp fn = s->vex_l ? ps_ymm : ps_xmm;
if (!fn) { if (!fn) {
goto illegal_op; goto illegal_op;
} }
fn(cpu_env, OP_PTR0, OP_PTR2); fn(tcg_env, OP_PTR0, OP_PTR2);
} }
return; return;
@ -607,7 +607,7 @@ static inline void gen_horizontal_fp_sse(DisasContext *s, CPUX86State *env, X86D
ps = s->vex_l ? ps_ymm : ps_xmm; ps = s->vex_l ? ps_ymm : ps_xmm;
pd = s->vex_l ? pd_ymm : pd_xmm; pd = s->vex_l ? pd_ymm : pd_xmm;
fn = s->prefix & PREFIX_DATA ? pd : ps; fn = s->prefix & PREFIX_DATA ? pd : ps;
fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} }
#define HORIZONTAL_FP_SSE(uname, lname) \ #define HORIZONTAL_FP_SSE(uname, lname) \
static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
@ -627,8 +627,8 @@ static inline void gen_ternary_sse(DisasContext *s, CPUX86State *env, X86Decoded
TCGv_ptr ptr3 = tcg_temp_new_ptr(); TCGv_ptr ptr3 = tcg_temp_new_ptr();
/* The format of the fourth input is Lx */ /* The format of the fourth input is Lx */
tcg_gen_addi_ptr(ptr3, cpu_env, ZMM_OFFSET(op3)); tcg_gen_addi_ptr(ptr3, tcg_env, ZMM_OFFSET(op3));
fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3); fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3);
} }
#define TERNARY_SSE(uname, uvname, lname) \ #define TERNARY_SSE(uname, uvname, lname) \
static void gen_##uvname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \ static void gen_##uvname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
@ -650,9 +650,9 @@ static inline void gen_binary_imm_sse(DisasContext *s, CPUX86State *env, X86Deco
{ {
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
if (!s->vex_l) { if (!s->vex_l) {
xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
} else { } else {
ymm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
} }
} }
@ -763,11 +763,11 @@ static inline void gen_binary_int_sse(DisasContext *s, CPUX86State *env, X86Deco
return; return;
} }
if (!(s->prefix & PREFIX_DATA)) { if (!(s->prefix & PREFIX_DATA)) {
mmx(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} else if (!s->vex_l) { } else if (!s->vex_l) {
xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} else { } else {
ymm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} }
} }
@ -850,9 +850,9 @@ BINARY_INT_SSE(VAESENCLAST, aesenclast)
static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
{ \ { \
if (!s->vex_l) { \ if (!s->vex_l) { \
gen_helper_##lname##_xmm(cpu_env, OP_PTR1, OP_PTR2); \ gen_helper_##lname##_xmm(tcg_env, OP_PTR1, OP_PTR2); \
} else { \ } else { \
gen_helper_##lname##_ymm(cpu_env, OP_PTR1, OP_PTR2); \ gen_helper_##lname##_ymm(tcg_env, OP_PTR1, OP_PTR2); \
} \ } \
set_cc_op(s, CC_OP_EFLAGS); \ set_cc_op(s, CC_OP_EFLAGS); \
} }
@ -864,9 +864,9 @@ static inline void gen_unary_int_sse(DisasContext *s, CPUX86State *env, X86Decod
SSEFunc_0_epp xmm, SSEFunc_0_epp ymm) SSEFunc_0_epp xmm, SSEFunc_0_epp ymm)
{ {
if (!s->vex_l) { if (!s->vex_l) {
xmm(cpu_env, OP_PTR0, OP_PTR2); xmm(tcg_env, OP_PTR0, OP_PTR2);
} else { } else {
ymm(cpu_env, OP_PTR0, OP_PTR2); ymm(tcg_env, OP_PTR0, OP_PTR2);
} }
} }
@ -937,9 +937,9 @@ static inline void gen_unary_imm_fp_sse(DisasContext *s, CPUX86State *env, X86De
{ {
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
if (!s->vex_l) { if (!s->vex_l) {
xmm(cpu_env, OP_PTR0, OP_PTR1, imm); xmm(tcg_env, OP_PTR0, OP_PTR1, imm);
} else { } else {
ymm(cpu_env, OP_PTR0, OP_PTR1, imm); ymm(tcg_env, OP_PTR0, OP_PTR1, imm);
} }
} }
@ -961,7 +961,7 @@ static inline void gen_vexw_avx(DisasContext *s, CPUX86State *env, X86DecodedIns
SSEFunc_0_eppp d = s->vex_l ? d_ymm : d_xmm; SSEFunc_0_eppp d = s->vex_l ? d_ymm : d_xmm;
SSEFunc_0_eppp q = s->vex_l ? q_ymm : q_xmm; SSEFunc_0_eppp q = s->vex_l ? q_ymm : q_xmm;
SSEFunc_0_eppp fn = s->vex_w ? q : d; SSEFunc_0_eppp fn = s->vex_w ? q : d;
fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} }
/* VEX.W affects whether to operate on 32- or 64-bit elements. */ /* VEX.W affects whether to operate on 32- or 64-bit elements. */
@ -989,8 +989,8 @@ static inline void gen_vsib_avx(DisasContext *s, CPUX86State *env, X86DecodedIns
TCGv_ptr index = tcg_temp_new_ptr(); TCGv_ptr index = tcg_temp_new_ptr();
/* Pass third input as (index, base, scale) */ /* Pass third input as (index, base, scale) */
tcg_gen_addi_ptr(index, cpu_env, ZMM_OFFSET(decode->mem.index)); tcg_gen_addi_ptr(index, tcg_env, ZMM_OFFSET(decode->mem.index));
fn(cpu_env, OP_PTR0, OP_PTR1, index, s->A0, scale); fn(tcg_env, OP_PTR0, OP_PTR1, index, s->A0, scale);
/* /*
* There are two output operands, so zero OP1's high 128 bits * There are two output operands, so zero OP1's high 128 bits
@ -1175,37 +1175,37 @@ static void gen_CRC32(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
static void gen_CVTPI2Px(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_CVTPI2Px(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
gen_helper_enter_mmx(cpu_env); gen_helper_enter_mmx(tcg_env);
if (s->prefix & PREFIX_DATA) { if (s->prefix & PREFIX_DATA) {
gen_helper_cvtpi2pd(cpu_env, OP_PTR0, OP_PTR2); gen_helper_cvtpi2pd(tcg_env, OP_PTR0, OP_PTR2);
} else { } else {
gen_helper_cvtpi2ps(cpu_env, OP_PTR0, OP_PTR2); gen_helper_cvtpi2ps(tcg_env, OP_PTR0, OP_PTR2);
} }
} }
static void gen_CVTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_CVTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
gen_helper_enter_mmx(cpu_env); gen_helper_enter_mmx(tcg_env);
if (s->prefix & PREFIX_DATA) { if (s->prefix & PREFIX_DATA) {
gen_helper_cvtpd2pi(cpu_env, OP_PTR0, OP_PTR2); gen_helper_cvtpd2pi(tcg_env, OP_PTR0, OP_PTR2);
} else { } else {
gen_helper_cvtps2pi(cpu_env, OP_PTR0, OP_PTR2); gen_helper_cvtps2pi(tcg_env, OP_PTR0, OP_PTR2);
} }
} }
static void gen_CVTTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_CVTTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
gen_helper_enter_mmx(cpu_env); gen_helper_enter_mmx(tcg_env);
if (s->prefix & PREFIX_DATA) { if (s->prefix & PREFIX_DATA) {
gen_helper_cvttpd2pi(cpu_env, OP_PTR0, OP_PTR2); gen_helper_cvttpd2pi(tcg_env, OP_PTR0, OP_PTR2);
} else { } else {
gen_helper_cvttps2pi(cpu_env, OP_PTR0, OP_PTR2); gen_helper_cvttps2pi(tcg_env, OP_PTR0, OP_PTR2);
} }
} }
static void gen_EMMS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_EMMS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
gen_helper_emms(cpu_env); gen_helper_emms(tcg_env);
} }
static void gen_EXTRQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_EXTRQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
@ -1213,12 +1213,12 @@ static void gen_EXTRQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
TCGv_i32 length = tcg_constant_i32(decode->immediate & 63); TCGv_i32 length = tcg_constant_i32(decode->immediate & 63);
TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63); TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63);
gen_helper_extrq_i(cpu_env, OP_PTR0, index, length); gen_helper_extrq_i(tcg_env, OP_PTR0, index, length);
} }
static void gen_EXTRQ_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_EXTRQ_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
gen_helper_extrq_r(cpu_env, OP_PTR0, OP_PTR2); gen_helper_extrq_r(tcg_env, OP_PTR0, OP_PTR2);
} }
static void gen_INSERTQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_INSERTQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
@ -1226,12 +1226,12 @@ static void gen_INSERTQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
TCGv_i32 length = tcg_constant_i32(decode->immediate & 63); TCGv_i32 length = tcg_constant_i32(decode->immediate & 63);
TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63); TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63);
gen_helper_insertq_i(cpu_env, OP_PTR0, OP_PTR1, index, length); gen_helper_insertq_i(tcg_env, OP_PTR0, OP_PTR1, index, length);
} }
static void gen_INSERTQ_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_INSERTQ_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
gen_helper_insertq_r(cpu_env, OP_PTR0, OP_PTR2); gen_helper_insertq_r(tcg_env, OP_PTR0, OP_PTR2);
} }
static void gen_LDMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_LDMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
@ -1241,7 +1241,7 @@ static void gen_LDMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
return; return;
} }
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T1); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T1);
gen_helper_ldmxcsr(cpu_env, s->tmp2_i32); gen_helper_ldmxcsr(tcg_env, s->tmp2_i32);
} }
static void gen_MASKMOV(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_MASKMOV(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
@ -1251,9 +1251,9 @@ static void gen_MASKMOV(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
gen_add_A0_ds_seg(s); gen_add_A0_ds_seg(s);
if (s->prefix & PREFIX_DATA) { if (s->prefix & PREFIX_DATA) {
gen_helper_maskmov_xmm(cpu_env, OP_PTR1, OP_PTR2, s->A0); gen_helper_maskmov_xmm(tcg_env, OP_PTR1, OP_PTR2, s->A0);
} else { } else {
gen_helper_maskmov_mmx(cpu_env, OP_PTR1, OP_PTR2, s->A0); gen_helper_maskmov_mmx(tcg_env, OP_PTR1, OP_PTR2, s->A0);
} }
} }
@ -1276,11 +1276,11 @@ static void gen_MOVD_from(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
switch (ot) { switch (ot) {
case MO_32: case MO_32:
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
tcg_gen_ld32u_tl(s->T0, cpu_env, decode->op[2].offset); tcg_gen_ld32u_tl(s->T0, tcg_env, decode->op[2].offset);
break; break;
case MO_64: case MO_64:
#endif #endif
tcg_gen_ld_tl(s->T0, cpu_env, decode->op[2].offset); tcg_gen_ld_tl(s->T0, tcg_env, decode->op[2].offset);
break; break;
default: default:
abort(); abort();
@ -1298,11 +1298,11 @@ static void gen_MOVD_to(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
switch (ot) { switch (ot) {
case MO_32: case MO_32:
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
tcg_gen_st32_tl(s->T1, cpu_env, lo_ofs); tcg_gen_st32_tl(s->T1, tcg_env, lo_ofs);
break; break;
case MO_64: case MO_64:
#endif #endif
tcg_gen_st_tl(s->T1, cpu_env, lo_ofs); tcg_gen_st_tl(s->T1, tcg_env, lo_ofs);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -1320,7 +1320,7 @@ static void gen_MOVMSK(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode
ps = s->vex_l ? gen_helper_movmskps_ymm : gen_helper_movmskps_xmm; ps = s->vex_l ? gen_helper_movmskps_ymm : gen_helper_movmskps_xmm;
pd = s->vex_l ? gen_helper_movmskpd_ymm : gen_helper_movmskpd_xmm; pd = s->vex_l ? gen_helper_movmskpd_ymm : gen_helper_movmskpd_xmm;
fn = s->prefix & PREFIX_DATA ? pd : ps; fn = s->prefix & PREFIX_DATA ? pd : ps;
fn(s->tmp2_i32, cpu_env, OP_PTR2); fn(s->tmp2_i32, tcg_env, OP_PTR2);
tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
} }
@ -1329,7 +1329,7 @@ static void gen_MOVQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
int vec_len = vector_len(s, decode); int vec_len = vector_len(s, decode);
int lo_ofs = vector_elem_offset(&decode->op[0], MO_64, 0); int lo_ofs = vector_elem_offset(&decode->op[0], MO_64, 0);
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset); tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset);
if (decode->op[0].has_ea) { if (decode->op[0].has_ea) {
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ);
} else { } else {
@ -1342,13 +1342,13 @@ static void gen_MOVQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
* it disqualifies using oprsz < maxsz to emulate VEX128. * it disqualifies using oprsz < maxsz to emulate VEX128.
*/ */
tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
tcg_gen_st_i64(s->tmp1_i64, cpu_env, lo_ofs); tcg_gen_st_i64(s->tmp1_i64, tcg_env, lo_ofs);
} }
} }
static void gen_MOVq_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_MOVq_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
gen_helper_enter_mmx(cpu_env); gen_helper_enter_mmx(tcg_env);
/* Otherwise the same as any other movq. */ /* Otherwise the same as any other movq. */
return gen_MOVQ(s, env, decode); return gen_MOVQ(s, env, decode);
} }
@ -1380,11 +1380,11 @@ static void gen_PALIGNR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
{ {
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
if (!(s->prefix & PREFIX_DATA)) { if (!(s->prefix & PREFIX_DATA)) {
gen_helper_palignr_mmx(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); gen_helper_palignr_mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
} else if (!s->vex_l) { } else if (!s->vex_l) {
gen_helper_palignr_xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); gen_helper_palignr_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
} else { } else {
gen_helper_palignr_ymm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); gen_helper_palignr_ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
} }
} }
@ -1401,14 +1401,14 @@ static void gen_PANDN(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
static void gen_PCMPESTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_PCMPESTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
gen_helper_pcmpestri_xmm(cpu_env, OP_PTR1, OP_PTR2, imm); gen_helper_pcmpestri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm);
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
} }
static void gen_PCMPESTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_PCMPESTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
gen_helper_pcmpestrm_xmm(cpu_env, OP_PTR1, OP_PTR2, imm); gen_helper_pcmpestrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm);
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
if ((s->prefix & PREFIX_VEX) && !s->vex_l) { if ((s->prefix & PREFIX_VEX) && !s->vex_l) {
tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)), tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)),
@ -1419,14 +1419,14 @@ static void gen_PCMPESTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
static void gen_PCMPISTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_PCMPISTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
gen_helper_pcmpistri_xmm(cpu_env, OP_PTR1, OP_PTR2, imm); gen_helper_pcmpistri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm);
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
} }
static void gen_PCMPISTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_PCMPISTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
gen_helper_pcmpistrm_xmm(cpu_env, OP_PTR1, OP_PTR2, imm); gen_helper_pcmpistrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm);
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
if ((s->prefix & PREFIX_VEX) && !s->vex_l) { if ((s->prefix & PREFIX_VEX) && !s->vex_l) {
tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)), tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)),
@ -1460,18 +1460,18 @@ static inline void gen_pextr(DisasContext *s, CPUX86State *env, X86DecodedInsn *
switch (ot) { switch (ot) {
case MO_8: case MO_8:
tcg_gen_ld8u_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1], ot, val)); tcg_gen_ld8u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val));
break; break;
case MO_16: case MO_16:
tcg_gen_ld16u_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1], ot, val)); tcg_gen_ld16u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val));
break; break;
case MO_32: case MO_32:
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
tcg_gen_ld32u_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1], ot, val)); tcg_gen_ld32u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val));
break; break;
case MO_64: case MO_64:
#endif #endif
tcg_gen_ld_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1], ot, val)); tcg_gen_ld_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val));
break; break;
default: default:
abort(); abort();
@ -1507,18 +1507,18 @@ static inline void gen_pinsr(DisasContext *s, CPUX86State *env, X86DecodedInsn *
switch (ot) { switch (ot) {
case MO_8: case MO_8:
tcg_gen_st8_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0], ot, val)); tcg_gen_st8_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val));
break; break;
case MO_16: case MO_16:
tcg_gen_st16_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0], ot, val)); tcg_gen_st16_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val));
break; break;
case MO_32: case MO_32:
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
tcg_gen_st32_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0], ot, val)); tcg_gen_st32_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val));
break; break;
case MO_64: case MO_64:
#endif #endif
tcg_gen_st_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0], ot, val)); tcg_gen_st_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val));
break; break;
default: default:
abort(); abort();
@ -1599,7 +1599,7 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
tcg_gen_gvec_2(offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), decode->op[2].offset, tcg_gen_gvec_2(offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), decode->op[2].offset,
vec_len, vec_len, &g); vec_len, vec_len, &g);
tcg_gen_ld8u_tl(s->T0, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
while (vec_len > 8) { while (vec_len > 8) {
vec_len -= 8; vec_len -= 8;
if (TCG_TARGET_HAS_extract2_tl) { if (TCG_TARGET_HAS_extract2_tl) {
@ -1609,9 +1609,9 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
* loading the whole word, the shift left is avoided. * loading the whole word, the shift left is avoided.
*/ */
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((vec_len - 1) / 8))); tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((vec_len - 1) / 8)));
#else #else
tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_L((vec_len - 1) / 4))); tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L((vec_len - 1) / 4)));
#endif #endif
tcg_gen_extract2_tl(s->T0, t, s->T0, TARGET_LONG_BITS - 8); tcg_gen_extract2_tl(s->T0, t, s->T0, TARGET_LONG_BITS - 8);
@ -1621,7 +1621,7 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
* those bits are known to be zero after ld8u, this becomes a shift+or * those bits are known to be zero after ld8u, this becomes a shift+or
* if deposit is not available. * if deposit is not available.
*/ */
tcg_gen_ld8u_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); tcg_gen_ld8u_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8); tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8);
} }
} }
@ -1744,8 +1744,8 @@ static TCGv_ptr make_imm8u_xmm_vec(uint8_t imm, int vec_len)
tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_t0) + xmm_offset(ot),
vec_len, vec_len, 0); vec_len, vec_len, 0);
tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_t0)); tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_t0));
tcg_gen_st_i32(imm_v, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_L(0))); tcg_gen_st_i32(imm_v, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L(0)));
return ptr; return ptr;
} }
@ -1755,9 +1755,9 @@ static void gen_PSRLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len); TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len);
if (s->vex_l) { if (s->vex_l) {
gen_helper_psrldq_ymm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); gen_helper_psrldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec);
} else { } else {
gen_helper_psrldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); gen_helper_psrldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec);
} }
} }
@ -1767,9 +1767,9 @@ static void gen_PSLLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len); TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len);
if (s->vex_l) { if (s->vex_l) {
gen_helper_pslldq_ymm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); gen_helper_pslldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec);
} else { } else {
gen_helper_pslldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); gen_helper_pslldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec);
} }
} }
@ -1827,7 +1827,7 @@ static void gen_VAESKEYGEN(DisasContext *s, CPUX86State *env, X86DecodedInsn *de
{ {
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
assert(!s->vex_l); assert(!s->vex_l);
gen_helper_aeskeygenassist_xmm(cpu_env, OP_PTR0, OP_PTR1, imm); gen_helper_aeskeygenassist_xmm(tcg_env, OP_PTR0, OP_PTR1, imm);
} }
static void gen_STMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_STMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
@ -1836,14 +1836,14 @@ static void gen_STMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
gen_illegal_opcode(s); gen_illegal_opcode(s);
return; return;
} }
gen_helper_update_mxcsr(cpu_env); gen_helper_update_mxcsr(tcg_env);
tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, mxcsr)); tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr));
} }
static void gen_VAESIMC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VAESIMC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
assert(!s->vex_l); assert(!s->vex_l);
gen_helper_aesimc_xmm(cpu_env, OP_PTR0, OP_PTR2); gen_helper_aesimc_xmm(tcg_env, OP_PTR0, OP_PTR2);
} }
/* /*
@ -1903,32 +1903,32 @@ static void gen_VCMP(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
s->prefix & PREFIX_REPNZ ? 3 /* sd */ : s->prefix & PREFIX_REPNZ ? 3 /* sd */ :
!!(s->prefix & PREFIX_DATA) /* pd */ + (s->vex_l << 2); !!(s->prefix & PREFIX_DATA) /* pd */ + (s->vex_l << 2);
gen_helper_cmp_funcs[index][b](cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); gen_helper_cmp_funcs[index][b](tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} }
static void gen_VCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
SSEFunc_0_epp fn; SSEFunc_0_epp fn;
fn = s->prefix & PREFIX_DATA ? gen_helper_comisd : gen_helper_comiss; fn = s->prefix & PREFIX_DATA ? gen_helper_comisd : gen_helper_comiss;
fn(cpu_env, OP_PTR1, OP_PTR2); fn(tcg_env, OP_PTR1, OP_PTR2);
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
} }
static void gen_VCVTPD2PS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VCVTPD2PS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
if (s->vex_l) { if (s->vex_l) {
gen_helper_cvtpd2ps_ymm(cpu_env, OP_PTR0, OP_PTR2); gen_helper_cvtpd2ps_ymm(tcg_env, OP_PTR0, OP_PTR2);
} else { } else {
gen_helper_cvtpd2ps_xmm(cpu_env, OP_PTR0, OP_PTR2); gen_helper_cvtpd2ps_xmm(tcg_env, OP_PTR0, OP_PTR2);
} }
} }
static void gen_VCVTPS2PD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VCVTPS2PD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
if (s->vex_l) { if (s->vex_l) {
gen_helper_cvtps2pd_ymm(cpu_env, OP_PTR0, OP_PTR2); gen_helper_cvtps2pd_ymm(tcg_env, OP_PTR0, OP_PTR2);
} else { } else {
gen_helper_cvtps2pd_xmm(cpu_env, OP_PTR0, OP_PTR2); gen_helper_cvtps2pd_xmm(tcg_env, OP_PTR0, OP_PTR2);
} }
} }
@ -1948,12 +1948,12 @@ static void gen_VCVTPS2PH(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
static void gen_VCVTSD2SS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VCVTSD2SS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
gen_helper_cvtsd2ss(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); gen_helper_cvtsd2ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} }
static void gen_VCVTSS2SD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VCVTSS2SD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
gen_helper_cvtss2sd(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); gen_helper_cvtss2sd(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} }
static void gen_VCVTSI2Sx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VCVTSI2Sx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
@ -1967,9 +1967,9 @@ static void gen_VCVTSI2Sx(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
MemOp ot = decode->op[2].ot; MemOp ot = decode->op[2].ot;
if (ot == MO_64) { if (ot == MO_64) {
if (s->prefix & PREFIX_REPNZ) { if (s->prefix & PREFIX_REPNZ) {
gen_helper_cvtsq2sd(cpu_env, OP_PTR0, s->T1); gen_helper_cvtsq2sd(tcg_env, OP_PTR0, s->T1);
} else { } else {
gen_helper_cvtsq2ss(cpu_env, OP_PTR0, s->T1); gen_helper_cvtsq2ss(tcg_env, OP_PTR0, s->T1);
} }
return; return;
} }
@ -1980,9 +1980,9 @@ static void gen_VCVTSI2Sx(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
#endif #endif
if (s->prefix & PREFIX_REPNZ) { if (s->prefix & PREFIX_REPNZ) {
gen_helper_cvtsi2sd(cpu_env, OP_PTR0, in); gen_helper_cvtsi2sd(tcg_env, OP_PTR0, in);
} else { } else {
gen_helper_cvtsi2ss(cpu_env, OP_PTR0, in); gen_helper_cvtsi2ss(tcg_env, OP_PTR0, in);
} }
} }
@ -1996,9 +1996,9 @@ static inline void gen_VCVTtSx2SI(DisasContext *s, CPUX86State *env, X86DecodedI
MemOp ot = decode->op[0].ot; MemOp ot = decode->op[0].ot;
if (ot == MO_64) { if (ot == MO_64) {
if (s->prefix & PREFIX_REPNZ) { if (s->prefix & PREFIX_REPNZ) {
sd2sq(s->T0, cpu_env, OP_PTR2); sd2sq(s->T0, tcg_env, OP_PTR2);
} else { } else {
ss2sq(s->T0, cpu_env, OP_PTR2); ss2sq(s->T0, tcg_env, OP_PTR2);
} }
return; return;
} }
@ -2008,9 +2008,9 @@ static inline void gen_VCVTtSx2SI(DisasContext *s, CPUX86State *env, X86DecodedI
out = s->T0; out = s->T0;
#endif #endif
if (s->prefix & PREFIX_REPNZ) { if (s->prefix & PREFIX_REPNZ) {
sd2si(out, cpu_env, OP_PTR2); sd2si(out, tcg_env, OP_PTR2);
} else { } else {
ss2si(out, cpu_env, OP_PTR2); ss2si(out, tcg_env, OP_PTR2);
} }
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
tcg_gen_extu_i32_tl(s->T0, out); tcg_gen_extu_i32_tl(s->T0, out);
@ -2072,7 +2072,7 @@ static void gen_vinsertps(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
} }
if (new_mask != (val & 15)) { if (new_mask != (val & 15)) {
tcg_gen_st_i32(s->tmp2_i32, cpu_env, tcg_gen_st_i32(s->tmp2_i32, tcg_env,
vector_elem_offset(&decode->op[0], MO_32, dest_word)); vector_elem_offset(&decode->op[0], MO_32, dest_word));
} }
@ -2081,7 +2081,7 @@ static void gen_vinsertps(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
int i; int i;
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
if ((val >> i) & 1) { if ((val >> i) & 1) {
tcg_gen_st_i32(zero, cpu_env, tcg_gen_st_i32(zero, tcg_env,
vector_elem_offset(&decode->op[0], MO_32, i)); vector_elem_offset(&decode->op[0], MO_32, i));
} }
} }
@ -2091,7 +2091,7 @@ static void gen_vinsertps(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
static void gen_VINSERTPS_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VINSERTPS_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
int val = decode->immediate; int val = decode->immediate;
tcg_gen_ld_i32(s->tmp2_i32, cpu_env, tcg_gen_ld_i32(s->tmp2_i32, tcg_env,
vector_elem_offset(&decode->op[2], MO_32, (val >> 6) & 3)); vector_elem_offset(&decode->op[2], MO_32, (val >> 6) & 3));
gen_vinsertps(s, env, decode); gen_vinsertps(s, env, decode);
} }
@ -2117,9 +2117,9 @@ static inline void gen_maskmov(DisasContext *s, CPUX86State *env, X86DecodedInsn
SSEFunc_0_eppt xmm, SSEFunc_0_eppt ymm) SSEFunc_0_eppt xmm, SSEFunc_0_eppt ymm)
{ {
if (!s->vex_l) { if (!s->vex_l) {
xmm(cpu_env, OP_PTR2, OP_PTR1, s->A0); xmm(tcg_env, OP_PTR2, OP_PTR1, s->A0);
} else { } else {
ymm(cpu_env, OP_PTR2, OP_PTR1, s->A0); ymm(tcg_env, OP_PTR2, OP_PTR1, s->A0);
} }
} }
@ -2137,8 +2137,8 @@ static void gen_VMOVHPx_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *de
{ {
gen_ldq_env_A0(s, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); gen_ldq_env_A0(s, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
if (decode->op[0].offset != decode->op[1].offset) { if (decode->op[0].offset != decode->op[1].offset) {
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
} }
} }
@ -2150,32 +2150,32 @@ static void gen_VMOVHPx_st(DisasContext *s, CPUX86State *env, X86DecodedInsn *de
static void gen_VMOVHPx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VMOVHPx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
if (decode->op[0].offset != decode->op[2].offset) { if (decode->op[0].offset != decode->op[2].offset) {
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1)));
tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
} }
if (decode->op[0].offset != decode->op[1].offset) { if (decode->op[0].offset != decode->op[1].offset) {
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
} }
} }
static void gen_VMOVHLPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VMOVHLPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1)));
tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
if (decode->op[0].offset != decode->op[1].offset) { if (decode->op[0].offset != decode->op[1].offset) {
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(1))); tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(1)));
tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
} }
} }
static void gen_VMOVLHPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VMOVLHPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset); tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset);
tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
if (decode->op[0].offset != decode->op[1].offset) { if (decode->op[0].offset != decode->op[1].offset) {
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
} }
} }
@ -2188,9 +2188,9 @@ static void gen_VMOVLPx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decod
{ {
int vec_len = vector_len(s, decode); int vec_len = vector_len(s, decode);
tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len);
tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
} }
static void gen_VMOVLPx_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VMOVLPx_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
@ -2266,21 +2266,21 @@ static void gen_VPERM2x128(DisasContext *s, CPUX86State *env, X86DecodedInsn *de
static void gen_VPHMINPOSUW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VPHMINPOSUW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
assert(!s->vex_l); assert(!s->vex_l);
gen_helper_phminposuw_xmm(cpu_env, OP_PTR0, OP_PTR2); gen_helper_phminposuw_xmm(tcg_env, OP_PTR0, OP_PTR2);
} }
static void gen_VROUNDSD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VROUNDSD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
assert(!s->vex_l); assert(!s->vex_l);
gen_helper_roundsd_xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); gen_helper_roundsd_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
} }
static void gen_VROUNDSS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VROUNDSS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{ {
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
assert(!s->vex_l); assert(!s->vex_l);
gen_helper_roundss_xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); gen_helper_roundss_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
} }
static void gen_VSHUF(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_VSHUF(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
@ -2297,7 +2297,7 @@ static void gen_VUCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode
{ {
SSEFunc_0_epp fn; SSEFunc_0_epp fn;
fn = s->prefix & PREFIX_DATA ? gen_helper_ucomisd : gen_helper_ucomiss; fn = s->prefix & PREFIX_DATA ? gen_helper_ucomisd : gen_helper_ucomiss;
fn(cpu_env, OP_PTR1, OP_PTR2); fn(tcg_env, OP_PTR1, OP_PTR2);
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
} }
@ -2305,7 +2305,7 @@ static void gen_VZEROALL(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
{ {
TCGv_ptr ptr = tcg_temp_new_ptr(); TCGv_ptr ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_regs)); tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_regs));
gen_helper_memset(ptr, ptr, tcg_constant_i32(0), gen_helper_memset(ptr, ptr, tcg_constant_i32(0),
tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg))); tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg)));
} }

580
target/i386/tcg/translate.c
View File

File diff suppressed because it is too large Load Diff

4
target/loongarch/insn_trans/trans_atomic.c.inc
View File

@ -10,8 +10,8 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
TCGv t0 = make_address_i(ctx, src1, a->imm); TCGv t0 = make_address_i(ctx, src1, a->imm);
tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop); tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop);
tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr)); tcg_gen_st_tl(t0, tcg_env, offsetof(CPULoongArchState, lladdr));
tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval)); tcg_gen_st_tl(dest, tcg_env, offsetof(CPULoongArchState, llval));
gen_set_gpr(a->rd, dest, EXT_NONE); gen_set_gpr(a->rd, dest, EXT_NONE);
return true; return true;

2
target/loongarch/insn_trans/trans_branch.c.inc
View File

@ -66,7 +66,7 @@ static bool gen_cz_bc(DisasContext *ctx, arg_c_offs *a, TCGCond cond)
TCGv src1 = tcg_temp_new(); TCGv src1 = tcg_temp_new();
TCGv src2 = tcg_constant_tl(0); TCGv src2 = tcg_constant_tl(0);
tcg_gen_ld8u_tl(src1, cpu_env, tcg_gen_ld8u_tl(src1, tcg_env,
offsetof(CPULoongArchState, cf[a->cj])); offsetof(CPULoongArchState, cf[a->cj]));
gen_bc(ctx, src1, src2, a->offs, cond); gen_bc(ctx, src1, src2, a->offs, cond);
return true; return true;

10
target/loongarch/insn_trans/trans_extra.c.inc
View File

@ -24,7 +24,7 @@ static bool trans_asrtle_d(DisasContext *ctx, arg_asrtle_d * a)
return false; return false;
} }
gen_helper_asrtle_d(cpu_env, src1, src2); gen_helper_asrtle_d(tcg_env, src1, src2);
return true; return true;
} }
@ -37,7 +37,7 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a)
return false; return false;
} }
gen_helper_asrtgt_d(cpu_env, src1, src2); gen_helper_asrtgt_d(tcg_env, src1, src2);
return true; return true;
} }
@ -48,11 +48,11 @@ static bool gen_rdtime(DisasContext *ctx, arg_rr *a,
TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE); TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_rdtime_d(dst1, cpu_env); gen_helper_rdtime_d(dst1, tcg_env);
if (word) { if (word) {
tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32); tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
} }
tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TID)); tcg_gen_ld_i64(dst2, tcg_env, offsetof(CPULoongArchState, CSR_TID));
return true; return true;
} }
@ -77,7 +77,7 @@ static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a)
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
gen_helper_cpucfg(dest, cpu_env, src1); gen_helper_cpucfg(dest, tcg_env, src1);
gen_set_gpr(a->rd, dest, EXT_NONE); gen_set_gpr(a->rd, dest, EXT_NONE);
return true; return true;

6
target/loongarch/insn_trans/trans_farith.c.inc
View File

@ -23,7 +23,7 @@ static bool gen_fff(DisasContext *ctx, arg_fff *a,
CHECK_FPE; CHECK_FPE;
func(dest, cpu_env, src1, src2); func(dest, tcg_env, src1, src2);
set_fpr(a->fd, dest); set_fpr(a->fd, dest);
return true; return true;
@ -37,7 +37,7 @@ static bool gen_ff(DisasContext *ctx, arg_ff *a,
CHECK_FPE; CHECK_FPE;
func(dest, cpu_env, src); func(dest, tcg_env, src);
set_fpr(a->fd, dest); set_fpr(a->fd, dest);
return true; return true;
@ -55,7 +55,7 @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
CHECK_FPE; CHECK_FPE;
func(dest, cpu_env, src1, src2, src3, tflag); func(dest, tcg_env, src1, src2, src3, tflag);
set_fpr(a->fd, dest); set_fpr(a->fd, dest);
return true; return true;

8
target/loongarch/insn_trans/trans_fcmp.c.inc
View File

@ -41,9 +41,9 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s); fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
flags = get_fcmp_flags(a->fcond >> 1); flags = get_fcmp_flags(a->fcond >> 1);
fn(var, cpu_env, src1, src2, tcg_constant_i32(flags)); fn(var, tcg_env, src1, src2, tcg_constant_i32(flags));
tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd])); tcg_gen_st8_tl(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd]));
return true; return true;
} }
@ -65,8 +65,8 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d); fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d);
flags = get_fcmp_flags(a->fcond >> 1); flags = get_fcmp_flags(a->fcond >> 1);
fn(var, cpu_env, src1, src2, tcg_constant_i32(flags)); fn(var, tcg_env, src1, src2, tcg_constant_i32(flags));
tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd])); tcg_gen_st8_tl(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd]));
return true; return true;
} }

8
target/loongarch/insn_trans/trans_fmemory.c.inc
View File

@ -81,7 +81,7 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
CHECK_FPE; CHECK_FPE;
gen_helper_asrtgt_d(cpu_env, src1, src2); gen_helper_asrtgt_d(tcg_env, src1, src2);
addr = make_address_x(ctx, src1, src2); addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop); maybe_nanbox_load(dest, mop);
@ -99,7 +99,7 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
CHECK_FPE; CHECK_FPE;
gen_helper_asrtgt_d(cpu_env, src1, src2); gen_helper_asrtgt_d(tcg_env, src1, src2);
addr = make_address_x(ctx, src1, src2); addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
@ -115,7 +115,7 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop)
CHECK_FPE; CHECK_FPE;
gen_helper_asrtle_d(cpu_env, src1, src2); gen_helper_asrtle_d(tcg_env, src1, src2);
addr = make_address_x(ctx, src1, src2); addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop); maybe_nanbox_load(dest, mop);
@ -133,7 +133,7 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
CHECK_FPE; CHECK_FPE;
gen_helper_asrtle_d(cpu_env, src1, src2); gen_helper_asrtle_d(tcg_env, src1, src2);
addr = make_address_x(ctx, src1, src2); addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);

20
target/loongarch/insn_trans/trans_fmov.c.inc
View File

@ -22,7 +22,7 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a)
CHECK_FPE; CHECK_FPE;
cond = tcg_temp_new(); cond = tcg_temp_new();
tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca])); tcg_gen_ld8u_tl(cond, tcg_env, offsetof(CPULoongArchState, cf[a->ca]));
tcg_gen_movcond_tl(TCG_COND_EQ, dest, cond, zero, src1, src2); tcg_gen_movcond_tl(TCG_COND_EQ, dest, cond, zero, src1, src2);
set_fpr(a->fd, dest); set_fpr(a->fd, dest);
@ -94,17 +94,17 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a)
CHECK_FPE; CHECK_FPE;
if (mask == UINT32_MAX) { if (mask == UINT32_MAX) {
tcg_gen_st32_i64(Rj, cpu_env, offsetof(CPULoongArchState, fcsr0)); tcg_gen_st32_i64(Rj, tcg_env, offsetof(CPULoongArchState, fcsr0));
} else { } else {
TCGv_i32 fcsr0 = tcg_temp_new_i32(); TCGv_i32 fcsr0 = tcg_temp_new_i32();
TCGv_i32 temp = tcg_temp_new_i32(); TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_ld_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); tcg_gen_ld_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0));
tcg_gen_extrl_i64_i32(temp, Rj); tcg_gen_extrl_i64_i32(temp, Rj);
tcg_gen_andi_i32(temp, temp, mask); tcg_gen_andi_i32(temp, temp, mask);
tcg_gen_andi_i32(fcsr0, fcsr0, ~mask); tcg_gen_andi_i32(fcsr0, fcsr0, ~mask);
tcg_gen_or_i32(fcsr0, fcsr0, temp); tcg_gen_or_i32(fcsr0, fcsr0, temp);
tcg_gen_st_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); tcg_gen_st_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0));
} }
/* /*
@ -112,7 +112,7 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a)
* Note that FCSR3 is exactly the rounding mode field. * Note that FCSR3 is exactly the rounding mode field.
*/ */
if (mask & FCSR0_M3) { if (mask & FCSR0_M3) {
gen_helper_set_rounding_mode(cpu_env); gen_helper_set_rounding_mode(tcg_env);
} }
return true; return true;
} }
@ -127,7 +127,7 @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a)
CHECK_FPE; CHECK_FPE;
tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0)); tcg_gen_ld32u_i64(dest, tcg_env, offsetof(CPULoongArchState, fcsr0));
tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]); tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]);
gen_set_gpr(a->rd, dest, EXT_NONE); gen_set_gpr(a->rd, dest, EXT_NONE);
@ -162,7 +162,7 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)
t0 = tcg_temp_new(); t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src, 0x1); tcg_gen_andi_tl(t0, src, 0x1);
tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); tcg_gen_st8_tl(t0, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
return true; return true;
} }
@ -177,7 +177,7 @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)
CHECK_FPE; CHECK_FPE;
tcg_gen_ld8u_tl(dest, cpu_env, tcg_gen_ld8u_tl(dest, tcg_env,
offsetof(CPULoongArchState, cf[a->cj & 0x7])); offsetof(CPULoongArchState, cf[a->cj & 0x7]));
set_fpr(a->fd, dest); set_fpr(a->fd, dest);
@ -196,7 +196,7 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)
t0 = tcg_temp_new(); t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1); tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1);
tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); tcg_gen_st8_tl(t0, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
return true; return true;
} }
@ -209,7 +209,7 @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
CHECK_FPE; CHECK_FPE;
tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env, tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), tcg_env,
offsetof(CPULoongArchState, cf[a->cj & 0x7])); offsetof(CPULoongArchState, cf[a->cj & 0x7]));
return true; return true;
} }

8
target/loongarch/insn_trans/trans_memory.c.inc
View File

@ -57,7 +57,7 @@ static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
gen_helper_asrtgt_d(cpu_env, src1, src2); gen_helper_asrtgt_d(tcg_env, src1, src2);
src1 = make_address_i(ctx, src1, 0); src1 = make_address_i(ctx, src1, 0);
tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop); tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE); gen_set_gpr(a->rd, dest, EXT_NONE);
@ -71,7 +71,7 @@ static bool gen_load_le(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
gen_helper_asrtle_d(cpu_env, src1, src2); gen_helper_asrtle_d(tcg_env, src1, src2);
src1 = make_address_i(ctx, src1, 0); src1 = make_address_i(ctx, src1, 0);
tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop); tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE); gen_set_gpr(a->rd, dest, EXT_NONE);
@ -85,7 +85,7 @@ static bool gen_store_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
gen_helper_asrtgt_d(cpu_env, src1, src2); gen_helper_asrtgt_d(tcg_env, src1, src2);
src1 = make_address_i(ctx, src1, 0); src1 = make_address_i(ctx, src1, 0);
tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop); tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
@ -98,7 +98,7 @@ static bool gen_store_le(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
gen_helper_asrtle_d(cpu_env, src1, src2); gen_helper_asrtle_d(tcg_env, src1, src2);
src1 = make_address_i(ctx, src1, 0); src1 = make_address_i(ctx, src1, 0);
tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop); tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);

52
target/loongarch/insn_trans/trans_privileged.c.inc
View File

@ -203,9 +203,9 @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
check_csr_flags(ctx, csr, false); check_csr_flags(ctx, csr, false);
dest = gpr_dst(ctx, a->rd, EXT_NONE); dest = gpr_dst(ctx, a->rd, EXT_NONE);
if (csr->readfn) { if (csr->readfn) {
csr->readfn(dest, cpu_env); csr->readfn(dest, tcg_env);
} else { } else {
tcg_gen_ld_tl(dest, cpu_env, csr->offset); tcg_gen_ld_tl(dest, tcg_env, csr->offset);
} }
} }
gen_set_gpr(a->rd, dest, EXT_NONE); gen_set_gpr(a->rd, dest, EXT_NONE);
@ -233,11 +233,11 @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
src1 = gpr_src(ctx, a->rd, EXT_NONE); src1 = gpr_src(ctx, a->rd, EXT_NONE);
if (csr->writefn) { if (csr->writefn) {
dest = gpr_dst(ctx, a->rd, EXT_NONE); dest = gpr_dst(ctx, a->rd, EXT_NONE);
csr->writefn(dest, cpu_env, src1); csr->writefn(dest, tcg_env, src1);
} else { } else {
dest = tcg_temp_new(); dest = tcg_temp_new();
tcg_gen_ld_tl(dest, cpu_env, csr->offset); tcg_gen_ld_tl(dest, tcg_env, csr->offset);
tcg_gen_st_tl(src1, cpu_env, csr->offset); tcg_gen_st_tl(src1, tcg_env, csr->offset);
} }
gen_set_gpr(a->rd, dest, EXT_NONE); gen_set_gpr(a->rd, dest, EXT_NONE);
return true; return true;
@ -272,15 +272,15 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
newv = tcg_temp_new(); newv = tcg_temp_new();
temp = tcg_temp_new(); temp = tcg_temp_new();
tcg_gen_ld_tl(oldv, cpu_env, csr->offset); tcg_gen_ld_tl(oldv, tcg_env, csr->offset);
tcg_gen_and_tl(newv, src1, mask); tcg_gen_and_tl(newv, src1, mask);
tcg_gen_andc_tl(temp, oldv, mask); tcg_gen_andc_tl(temp, oldv, mask);
tcg_gen_or_tl(newv, newv, temp); tcg_gen_or_tl(newv, newv, temp);
if (csr->writefn) { if (csr->writefn) {
csr->writefn(oldv, cpu_env, newv); csr->writefn(oldv, tcg_env, newv);
} else { } else {
tcg_gen_st_tl(newv, cpu_env, csr->offset); tcg_gen_st_tl(newv, tcg_env, csr->offset);
} }
gen_set_gpr(a->rd, oldv, EXT_NONE); gen_set_gpr(a->rd, oldv, EXT_NONE);
return true; return true;
@ -295,7 +295,7 @@ static bool gen_iocsrrd(DisasContext *ctx, arg_rr *a,
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
func(dest, cpu_env, src1); func(dest, tcg_env, src1);
return true; return true;
} }
@ -308,7 +308,7 @@ static bool gen_iocsrwr(DisasContext *ctx, arg_rr *a,
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
func(cpu_env, addr, val); func(tcg_env, addr, val);
return true; return true;
} }
@ -334,7 +334,7 @@ static bool trans_tlbsrch(DisasContext *ctx, arg_tlbsrch *a)
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
gen_helper_tlbsrch(cpu_env); gen_helper_tlbsrch(tcg_env);
return true; return true;
} }
@ -343,7 +343,7 @@ static bool trans_tlbrd(DisasContext *ctx, arg_tlbrd *a)
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
gen_helper_tlbrd(cpu_env); gen_helper_tlbrd(tcg_env);
return true; return true;
} }
@ -352,7 +352,7 @@ static bool trans_tlbwr(DisasContext *ctx, arg_tlbwr *a)
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
gen_helper_tlbwr(cpu_env); gen_helper_tlbwr(tcg_env);
check_mmu_idx(ctx); check_mmu_idx(ctx);
return true; return true;
} }
@ -362,7 +362,7 @@ static bool trans_tlbfill(DisasContext *ctx, arg_tlbfill *a)
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
gen_helper_tlbfill(cpu_env); gen_helper_tlbfill(tcg_env);
check_mmu_idx(ctx); check_mmu_idx(ctx);
return true; return true;
} }
@ -372,7 +372,7 @@ static bool trans_tlbclr(DisasContext *ctx, arg_tlbclr *a)
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
gen_helper_tlbclr(cpu_env); gen_helper_tlbclr(tcg_env);
check_mmu_idx(ctx); check_mmu_idx(ctx);
return true; return true;
} }
@ -382,7 +382,7 @@ static bool trans_tlbflush(DisasContext *ctx, arg_tlbflush *a)
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
gen_helper_tlbflush(cpu_env); gen_helper_tlbflush(tcg_env);
check_mmu_idx(ctx); check_mmu_idx(ctx);
return true; return true;
} }
@ -399,22 +399,22 @@ static bool trans_invtlb(DisasContext *ctx, arg_invtlb *a)
switch (a->imm) { switch (a->imm) {
case 0: case 0:
case 1: case 1:
gen_helper_invtlb_all(cpu_env); gen_helper_invtlb_all(tcg_env);
break; break;
case 2: case 2:
gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(1)); gen_helper_invtlb_all_g(tcg_env, tcg_constant_i32(1));
break; break;
case 3: case 3:
gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(0)); gen_helper_invtlb_all_g(tcg_env, tcg_constant_i32(0));
break; break;
case 4: case 4:
gen_helper_invtlb_all_asid(cpu_env, rj); gen_helper_invtlb_all_asid(tcg_env, rj);
break; break;
case 5: case 5:
gen_helper_invtlb_page_asid(cpu_env, rj, rk); gen_helper_invtlb_page_asid(tcg_env, rj, rk);
break; break;
case 6: case 6:
gen_helper_invtlb_page_asid_or_g(cpu_env, rj, rk); gen_helper_invtlb_page_asid_or_g(tcg_env, rj, rk);
break; break;
default: default:
return false; return false;
@ -444,7 +444,7 @@ static bool trans_ldpte(DisasContext *ctx, arg_ldpte *a)
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
gen_helper_ldpte(cpu_env, src1, tcg_constant_tl(a->imm), mem_idx); gen_helper_ldpte(tcg_env, src1, tcg_constant_tl(a->imm), mem_idx);
return true; return true;
} }
@ -461,7 +461,7 @@ static bool trans_lddir(DisasContext *ctx, arg_lddir *a)
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
gen_helper_lddir(dest, cpu_env, src, tcg_constant_tl(a->imm), mem_idx); gen_helper_lddir(dest, tcg_env, src, tcg_constant_tl(a->imm), mem_idx);
return true; return true;
} }
@ -470,7 +470,7 @@ static bool trans_ertn(DisasContext *ctx, arg_ertn *a)
if (check_plv(ctx)) { if (check_plv(ctx)) {
return false; return false;
} }
gen_helper_ertn(cpu_env); gen_helper_ertn(tcg_env);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
return true; return true;
} }
@ -491,7 +491,7 @@ static bool trans_idle(DisasContext *ctx, arg_idle *a)
} }
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4); tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
gen_helper_idle(cpu_env); gen_helper_idle(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return true; return true;
} }

24
target/loongarch/insn_trans/trans_vec.c.inc
View File

@ -41,7 +41,7 @@ static bool gen_vvvv_ptr_vl(DisasContext *ctx, arg_vvvv *a, uint32_t oprsz,
vec_full_offset(a->vj), vec_full_offset(a->vj),
vec_full_offset(a->vk), vec_full_offset(a->vk),
vec_full_offset(a->va), vec_full_offset(a->va),
cpu_env, tcg_env,
oprsz, ctx->vl / 8, 0, fn); oprsz, ctx->vl / 8, 0, fn);
return true; return true;
} }
@ -94,7 +94,7 @@ static bool gen_vvv_ptr_vl(DisasContext *ctx, arg_vvv *a, uint32_t oprsz,
tcg_gen_gvec_3_ptr(vec_full_offset(a->vd), tcg_gen_gvec_3_ptr(vec_full_offset(a->vd),
vec_full_offset(a->vj), vec_full_offset(a->vj),
vec_full_offset(a->vk), vec_full_offset(a->vk),
cpu_env, tcg_env,
oprsz, ctx->vl / 8, 0, fn); oprsz, ctx->vl / 8, 0, fn);
return true; return true;
} }
@ -144,7 +144,7 @@ static bool gen_vv_ptr_vl(DisasContext *ctx, arg_vv *a, uint32_t oprsz,
tcg_gen_gvec_2_ptr(vec_full_offset(a->vd), tcg_gen_gvec_2_ptr(vec_full_offset(a->vd),
vec_full_offset(a->vj), vec_full_offset(a->vj),
cpu_env, tcg_env,
oprsz, ctx->vl / 8, 0, fn); oprsz, ctx->vl / 8, 0, fn);
return true; return true;
} }
@ -219,7 +219,7 @@ static bool gen_cv_vl(DisasContext *ctx, arg_cv *a, uint32_t sz,
TCGv_i32 cd = tcg_constant_i32(a->cd); TCGv_i32 cd = tcg_constant_i32(a->cd);
TCGv_i32 oprsz = tcg_constant_i32(sz); TCGv_i32 oprsz = tcg_constant_i32(sz);
func(cpu_env, oprsz, cd, vj); func(tcg_env, oprsz, cd, vj);
return true; return true;
} }
@ -4679,7 +4679,7 @@ static bool do_vfcmp_cond_s(DisasContext *ctx, arg_vvv_fcond *a, uint32_t sz)
fn = (a->fcond & 1 ? gen_helper_vfcmp_s_s : gen_helper_vfcmp_c_s); fn = (a->fcond & 1 ? gen_helper_vfcmp_s_s : gen_helper_vfcmp_c_s);
flags = get_fcmp_flags(a->fcond >> 1); flags = get_fcmp_flags(a->fcond >> 1);
fn(cpu_env, oprsz, vd, vj, vk, tcg_constant_i32(flags)); fn(tcg_env, oprsz, vd, vj, vk, tcg_constant_i32(flags));
return true; return true;
} }
@ -4699,7 +4699,7 @@ static bool do_vfcmp_cond_d(DisasContext *ctx, arg_vvv_fcond *a, uint32_t sz)
fn = (a->fcond & 1 ? gen_helper_vfcmp_s_d : gen_helper_vfcmp_c_d); fn = (a->fcond & 1 ? gen_helper_vfcmp_s_d : gen_helper_vfcmp_c_d);
flags = get_fcmp_flags(a->fcond >> 1); flags = get_fcmp_flags(a->fcond >> 1);
fn(cpu_env, oprsz, vd, vj, vk, tcg_constant_i32(flags)); fn(tcg_env, oprsz, vd, vj, vk, tcg_constant_i32(flags));
return true; return true;
} }
@ -4772,7 +4772,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_cv *a) \
\ \
tcg_gen_or_i64(t1, al, ah); \ tcg_gen_or_i64(t1, al, ah); \
tcg_gen_setcondi_i64(COND, t1, t1, 0); \ tcg_gen_setcondi_i64(COND, t1, t1, 0); \
tcg_gen_st8_tl(t1, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \ tcg_gen_st8_tl(t1, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \
\ \
return true; \ return true; \
} }
@ -4818,7 +4818,7 @@ static bool trans_## NAME(DisasContext *ctx, arg_cv * a) \
tcg_gen_or_i64(t2, d[2], d[3]); \ tcg_gen_or_i64(t2, d[2], d[3]); \
tcg_gen_or_i64(t1, t2, t1); \ tcg_gen_or_i64(t1, t2, t1); \
tcg_gen_setcondi_i64(COND, t1, t1, 0); \ tcg_gen_setcondi_i64(COND, t1, t1, 0); \
tcg_gen_st8_tl(t1, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \ tcg_gen_st8_tl(t1, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \
\ \
return true; \ return true; \
} }
@ -4844,7 +4844,7 @@ static bool gen_g2v_vl(DisasContext *ctx, arg_vr_i *a, uint32_t oprsz, MemOp mop
return true; return true;
} }
func(src, cpu_env, vec_reg_offset(a->vd, a->imm, mop)); func(src, tcg_env, vec_reg_offset(a->vd, a->imm, mop));
return true; return true;
} }
@ -4877,7 +4877,7 @@ static bool gen_v2g_vl(DisasContext *ctx, arg_rv_i *a, uint32_t oprsz, MemOp mop
return true; return true;
} }
func(dst, cpu_env, vec_reg_offset(a->vj, a->imm, mop)); func(dst, tcg_env, vec_reg_offset(a->vj, a->imm, mop));
return true; return true;
} }
@ -5026,7 +5026,7 @@ static bool gen_vreplve_vl(DisasContext *ctx, arg_vvr *a,
} }
tcg_gen_trunc_i64_ptr(t1, t0); tcg_gen_trunc_i64_ptr(t1, t0);
tcg_gen_add_ptr(t1, t1, cpu_env); tcg_gen_add_ptr(t1, t1, tcg_env);
for (i = 0; i < oprsz; i += 16) { for (i = 0; i < oprsz; i += 16) {
func(t2, t1, vec_full_offset(a->vj) + i); func(t2, t1, vec_full_offset(a->vj) + i);
@ -5422,7 +5422,7 @@ static bool do_vstelm_vl(DisasContext *ctx,
val = tcg_temp_new_i64(); val = tcg_temp_new_i64();
addr = make_address_i(ctx, addr, a->imm); addr = make_address_i(ctx, addr, a->imm);
tcg_gen_ld_i64(val, cpu_env, vec_reg_offset(a->vd, a->imm2, mop)); tcg_gen_ld_i64(val, tcg_env, vec_reg_offset(a->vd, a->imm2, mop));
tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, mop); tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, mop);
return true; return true;
} }

18
target/loongarch/translate.c
View File

@ -51,13 +51,13 @@ static inline int vec_reg_offset(int regno, int index, MemOp mop)
static inline void get_vreg64(TCGv_i64 dest, int regno, int index) static inline void get_vreg64(TCGv_i64 dest, int regno, int index)
{ {
tcg_gen_ld_i64(dest, cpu_env, tcg_gen_ld_i64(dest, tcg_env,
offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); offsetof(CPULoongArchState, fpr[regno].vreg.D(index)));
} }
static inline void set_vreg64(TCGv_i64 src, int regno, int index) static inline void set_vreg64(TCGv_i64 src, int regno, int index)
{ {
tcg_gen_st_i64(src, cpu_env, tcg_gen_st_i64(src, tcg_env,
offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); offsetof(CPULoongArchState, fpr[regno].vreg.D(index)));
} }
@ -93,7 +93,7 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
void generate_exception(DisasContext *ctx, int excp) void generate_exception(DisasContext *ctx, int excp)
{ {
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
} }
@ -221,14 +221,14 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
static TCGv get_fpr(DisasContext *ctx, int reg_num) static TCGv get_fpr(DisasContext *ctx, int reg_num)
{ {
TCGv t = tcg_temp_new(); TCGv t = tcg_temp_new();
tcg_gen_ld_i64(t, cpu_env, tcg_gen_ld_i64(t, tcg_env,
offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));
return t; return t;
} }
static void set_fpr(int reg_num, TCGv val) static void set_fpr(int reg_num, TCGv val)
{ {
tcg_gen_st_i64(val, cpu_env, tcg_gen_st_i64(val, tcg_env,
offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));
} }
@ -357,14 +357,14 @@ void loongarch_translate_init(void)
cpu_gpr[0] = NULL; cpu_gpr[0] = NULL;
for (i = 1; i < 32; i++) { for (i = 1; i < 32; i++) {
cpu_gpr[i] = tcg_global_mem_new(cpu_env, cpu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPULoongArchState, gpr[i]), offsetof(CPULoongArchState, gpr[i]),
regnames[i]); regnames[i]);
} }
cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, pc), "pc"); cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPULoongArchState, pc), "pc");
cpu_lladdr = tcg_global_mem_new(cpu_env, cpu_lladdr = tcg_global_mem_new(tcg_env,
offsetof(CPULoongArchState, lladdr), "lladdr"); offsetof(CPULoongArchState, lladdr), "lladdr");
cpu_llval = tcg_global_mem_new(cpu_env, cpu_llval = tcg_global_mem_new(tcg_env,
offsetof(CPULoongArchState, llval), "llval"); offsetof(CPULoongArchState, llval), "llval");
} }

302
target/m68k/translate.c
View File

@ -70,19 +70,19 @@ void m68k_tcg_init(void)
int i; int i;
#define DEFO32(name, offset) \ #define DEFO32(name, offset) \
QREG_##name = tcg_global_mem_new_i32(cpu_env, \ QREG_##name = tcg_global_mem_new_i32(tcg_env, \
offsetof(CPUM68KState, offset), #name); offsetof(CPUM68KState, offset), #name);
#define DEFO64(name, offset) \ #define DEFO64(name, offset) \
QREG_##name = tcg_global_mem_new_i64(cpu_env, \ QREG_##name = tcg_global_mem_new_i64(tcg_env, \
offsetof(CPUM68KState, offset), #name); offsetof(CPUM68KState, offset), #name);
#include "qregs.h.inc" #include "qregs.h.inc"
#undef DEFO32 #undef DEFO32
#undef DEFO64 #undef DEFO64
cpu_halted = tcg_global_mem_new_i32(cpu_env, cpu_halted = tcg_global_mem_new_i32(tcg_env,
-offsetof(M68kCPU, env) + -offsetof(M68kCPU, env) +
offsetof(CPUState, halted), "HALTED"); offsetof(CPUState, halted), "HALTED");
cpu_exception_index = tcg_global_mem_new_i32(cpu_env, cpu_exception_index = tcg_global_mem_new_i32(tcg_env,
-offsetof(M68kCPU, env) + -offsetof(M68kCPU, env) +
offsetof(CPUState, exception_index), offsetof(CPUState, exception_index),
"EXCEPTION"); "EXCEPTION");
@ -90,23 +90,23 @@ void m68k_tcg_init(void)
p = cpu_reg_names; p = cpu_reg_names;
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
sprintf(p, "D%d", i); sprintf(p, "D%d", i);
cpu_dregs[i] = tcg_global_mem_new(cpu_env, cpu_dregs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUM68KState, dregs[i]), p); offsetof(CPUM68KState, dregs[i]), p);
p += 3; p += 3;
sprintf(p, "A%d", i); sprintf(p, "A%d", i);
cpu_aregs[i] = tcg_global_mem_new(cpu_env, cpu_aregs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUM68KState, aregs[i]), p); offsetof(CPUM68KState, aregs[i]), p);
p += 3; p += 3;
} }
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
sprintf(p, "ACC%d", i); sprintf(p, "ACC%d", i);
cpu_macc[i] = tcg_global_mem_new_i64(cpu_env, cpu_macc[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUM68KState, macc[i]), p); offsetof(CPUM68KState, macc[i]), p);
p += 5; p += 5;
} }
NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL"); NULL_QREG = tcg_global_mem_new(tcg_env, -4, "NULL");
store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL"); store_dummy = tcg_global_mem_new(tcg_env, -8, "NULL");
} }
/* internal defines */ /* internal defines */
@ -264,7 +264,7 @@ static void gen_jmp(DisasContext *s, TCGv dest)
static void gen_raise_exception(int nr) static void gen_raise_exception(int nr)
{ {
gen_helper_raise_exception(cpu_env, tcg_constant_i32(nr)); gen_helper_raise_exception(tcg_env, tcg_constant_i32(nr));
} }
static void gen_raise_exception_format2(DisasContext *s, int nr, static void gen_raise_exception_format2(DisasContext *s, int nr,
@ -276,7 +276,7 @@ static void gen_raise_exception_format2(DisasContext *s, int nr,
* Re-use mmu.ar for the purpose, since that's only valid * Re-use mmu.ar for the purpose, since that's only valid
* after tlb_fill. * after tlb_fill.
*/ */
tcg_gen_st_i32(tcg_constant_i32(this_pc), cpu_env, tcg_gen_st_i32(tcg_constant_i32(this_pc), tcg_env,
offsetof(CPUM68KState, mmu.ar)); offsetof(CPUM68KState, mmu.ar));
gen_raise_exception(nr); gen_raise_exception(nr);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
@ -602,12 +602,12 @@ static void gen_flush_flags(DisasContext *s)
break; break;
case CC_OP_DYNAMIC: case CC_OP_DYNAMIC:
gen_helper_flush_flags(cpu_env, QREG_CC_OP); gen_helper_flush_flags(tcg_env, QREG_CC_OP);
s->cc_op_synced = 1; s->cc_op_synced = 1;
break; break;
default: default:
gen_helper_flush_flags(cpu_env, tcg_constant_i32(s->cc_op)); gen_helper_flush_flags(tcg_env, tcg_constant_i32(s->cc_op));
s->cc_op_synced = 1; s->cc_op_synced = 1;
break; break;
} }
@ -916,14 +916,14 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
static TCGv_ptr gen_fp_ptr(int freg) static TCGv_ptr gen_fp_ptr(int freg)
{ {
TCGv_ptr fp = tcg_temp_new_ptr(); TCGv_ptr fp = tcg_temp_new_ptr();
tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg])); tcg_gen_addi_ptr(fp, tcg_env, offsetof(CPUM68KState, fregs[freg]));
return fp; return fp;
} }
static TCGv_ptr gen_fp_result_ptr(void) static TCGv_ptr gen_fp_result_ptr(void)
{ {
TCGv_ptr fp = tcg_temp_new_ptr(); TCGv_ptr fp = tcg_temp_new_ptr();
tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result)); tcg_gen_addi_ptr(fp, tcg_env, offsetof(CPUM68KState, fp_result));
return fp; return fp;
} }
@ -954,15 +954,15 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
case OS_WORD: case OS_WORD:
case OS_LONG: case OS_LONG:
tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE); tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE);
gen_helper_exts32(cpu_env, fp, tmp); gen_helper_exts32(tcg_env, fp, tmp);
break; break;
case OS_SINGLE: case OS_SINGLE:
tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL); tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
gen_helper_extf32(cpu_env, fp, tmp); gen_helper_extf32(tcg_env, fp, tmp);
break; break;
case OS_DOUBLE: case OS_DOUBLE:
tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ); tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ);
gen_helper_extf64(cpu_env, fp, t64); gen_helper_extf64(tcg_env, fp, t64);
break; break;
case OS_EXTENDED: case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) { if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
@ -1000,15 +1000,15 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
case OS_BYTE: case OS_BYTE:
case OS_WORD: case OS_WORD:
case OS_LONG: case OS_LONG:
gen_helper_reds32(tmp, cpu_env, fp); gen_helper_reds32(tmp, tcg_env, fp);
tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE); tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE);
break; break;
case OS_SINGLE: case OS_SINGLE:
gen_helper_redf32(tmp, cpu_env, fp); gen_helper_redf32(tmp, tcg_env, fp);
tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL); tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
break; break;
case OS_DOUBLE: case OS_DOUBLE:
gen_helper_redf64(t64, cpu_env, fp); gen_helper_redf64(t64, tcg_env, fp);
tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ); tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ);
break; break;
case OS_EXTENDED: case OS_EXTENDED:
@ -1060,10 +1060,10 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
case OS_BYTE: case OS_BYTE:
case OS_WORD: case OS_WORD:
case OS_LONG: case OS_LONG:
gen_helper_reds32(reg, cpu_env, fp); gen_helper_reds32(reg, tcg_env, fp);
break; break;
case OS_SINGLE: case OS_SINGLE:
gen_helper_redf32(reg, cpu_env, fp); gen_helper_redf32(reg, tcg_env, fp);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -1073,17 +1073,17 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
switch (opsize) { switch (opsize) {
case OS_BYTE: case OS_BYTE:
tcg_gen_ext8s_i32(tmp, reg); tcg_gen_ext8s_i32(tmp, reg);
gen_helper_exts32(cpu_env, fp, tmp); gen_helper_exts32(tcg_env, fp, tmp);
break; break;
case OS_WORD: case OS_WORD:
tcg_gen_ext16s_i32(tmp, reg); tcg_gen_ext16s_i32(tmp, reg);
gen_helper_exts32(cpu_env, fp, tmp); gen_helper_exts32(tcg_env, fp, tmp);
break; break;
case OS_LONG: case OS_LONG:
gen_helper_exts32(cpu_env, fp, reg); gen_helper_exts32(tcg_env, fp, reg);
break; break;
case OS_SINGLE: case OS_SINGLE:
gen_helper_extf32(cpu_env, fp, reg); gen_helper_extf32(tcg_env, fp, reg);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -1132,23 +1132,23 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
switch (opsize) { switch (opsize) {
case OS_BYTE: case OS_BYTE:
tmp = tcg_constant_i32((int8_t)read_im8(env, s)); tmp = tcg_constant_i32((int8_t)read_im8(env, s));
gen_helper_exts32(cpu_env, fp, tmp); gen_helper_exts32(tcg_env, fp, tmp);
break; break;
case OS_WORD: case OS_WORD:
tmp = tcg_constant_i32((int16_t)read_im16(env, s)); tmp = tcg_constant_i32((int16_t)read_im16(env, s));
gen_helper_exts32(cpu_env, fp, tmp); gen_helper_exts32(tcg_env, fp, tmp);
break; break;
case OS_LONG: case OS_LONG:
tmp = tcg_constant_i32(read_im32(env, s)); tmp = tcg_constant_i32(read_im32(env, s));
gen_helper_exts32(cpu_env, fp, tmp); gen_helper_exts32(tcg_env, fp, tmp);
break; break;
case OS_SINGLE: case OS_SINGLE:
tmp = tcg_constant_i32(read_im32(env, s)); tmp = tcg_constant_i32(read_im32(env, s));
gen_helper_extf32(cpu_env, fp, tmp); gen_helper_extf32(tcg_env, fp, tmp);
break; break;
case OS_DOUBLE: case OS_DOUBLE:
t64 = tcg_constant_i64(read_im64(env, s)); t64 = tcg_constant_i64(read_im64(env, s));
gen_helper_extf64(cpu_env, fp, t64); gen_helper_extf64(tcg_env, fp, t64);
break; break;
case OS_EXTENDED: case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) { if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
@ -1516,9 +1516,9 @@ DISAS_INSN(divw)
destr = tcg_constant_i32(REG(insn, 9)); destr = tcg_constant_i32(REG(insn, 9));
ilen = tcg_constant_i32(s->pc - s->base.pc_next); ilen = tcg_constant_i32(s->pc - s->base.pc_next);
if (sign) { if (sign) {
gen_helper_divsw(cpu_env, destr, src, ilen); gen_helper_divsw(tcg_env, destr, src, ilen);
} else { } else {
gen_helper_divuw(cpu_env, destr, src, ilen); gen_helper_divuw(tcg_env, destr, src, ilen);
} }
set_cc_op(s, CC_OP_FLAGS); set_cc_op(s, CC_OP_FLAGS);
@ -1547,9 +1547,9 @@ DISAS_INSN(divl)
reg = tcg_constant_i32(REG(ext, 0)); reg = tcg_constant_i32(REG(ext, 0));
ilen = tcg_constant_i32(s->pc - s->base.pc_next); ilen = tcg_constant_i32(s->pc - s->base.pc_next);
if (sign) { if (sign) {
gen_helper_divsll(cpu_env, num, reg, den, ilen); gen_helper_divsll(tcg_env, num, reg, den, ilen);
} else { } else {
gen_helper_divull(cpu_env, num, reg, den, ilen); gen_helper_divull(tcg_env, num, reg, den, ilen);
} }
set_cc_op(s, CC_OP_FLAGS); set_cc_op(s, CC_OP_FLAGS);
return; return;
@ -1563,9 +1563,9 @@ DISAS_INSN(divl)
reg = tcg_constant_i32(REG(ext, 0)); reg = tcg_constant_i32(REG(ext, 0));
ilen = tcg_constant_i32(s->pc - s->base.pc_next); ilen = tcg_constant_i32(s->pc - s->base.pc_next);
if (sign) { if (sign) {
gen_helper_divsl(cpu_env, num, reg, den, ilen); gen_helper_divsl(tcg_env, num, reg, den, ilen);
} else { } else {
gen_helper_divul(cpu_env, num, reg, den, ilen); gen_helper_divul(tcg_env, num, reg, den, ilen);
} }
set_cc_op(s, CC_OP_FLAGS); set_cc_op(s, CC_OP_FLAGS);
@ -2126,7 +2126,7 @@ static TCGv gen_get_ccr(DisasContext *s)
update_cc_op(s); update_cc_op(s);
dest = tcg_temp_new(); dest = tcg_temp_new();
gen_helper_get_ccr(dest, cpu_env); gen_helper_get_ccr(dest, tcg_env);
return dest; return dest;
} }
@ -2153,7 +2153,7 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
} else { } else {
/* Must writeback before changing security state. */ /* Must writeback before changing security state. */
do_writebacks(s); do_writebacks(s);
gen_helper_set_sr(cpu_env, tcg_constant_i32(val)); gen_helper_set_sr(tcg_env, tcg_constant_i32(val));
} }
set_cc_op(s, CC_OP_FLAGS); set_cc_op(s, CC_OP_FLAGS);
} }
@ -2161,11 +2161,11 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only) static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
{ {
if (ccr_only) { if (ccr_only) {
gen_helper_set_ccr(cpu_env, val); gen_helper_set_ccr(tcg_env, val);
} else { } else {
/* Must writeback before changing security state. */ /* Must writeback before changing security state. */
do_writebacks(s); do_writebacks(s);
gen_helper_set_sr(cpu_env, val); gen_helper_set_sr(tcg_env, val);
} }
set_cc_op(s, CC_OP_FLAGS); set_cc_op(s, CC_OP_FLAGS);
} }
@ -2388,13 +2388,13 @@ DISAS_INSN(cas2w)
*/ */
if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env); gen_helper_exit_atomic(tcg_env);
} else { } else {
TCGv regs = tcg_constant_i32(REG(ext2, 6) | TCGv regs = tcg_constant_i32(REG(ext2, 6) |
(REG(ext1, 6) << 3) | (REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) | (REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9)); (REG(ext1, 0) << 9));
gen_helper_cas2w(cpu_env, regs, addr1, addr2); gen_helper_cas2w(tcg_env, regs, addr1, addr2);
} }
/* Note that cas2w also assigned to env->cc_op. */ /* Note that cas2w also assigned to env->cc_op. */
@ -2442,9 +2442,9 @@ DISAS_INSN(cas2l)
(REG(ext2, 0) << 6) | (REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9)); (REG(ext1, 0) << 9));
if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2); gen_helper_cas2l_parallel(tcg_env, regs, addr1, addr2);
} else { } else {
gen_helper_cas2l(cpu_env, regs, addr1, addr2); gen_helper_cas2l(tcg_env, regs, addr1, addr2);
} }
/* Note that cas2l also assigned to env->cc_op. */ /* Note that cas2l also assigned to env->cc_op. */
@ -2837,7 +2837,7 @@ DISAS_INSN(reset)
return; return;
} }
gen_helper_reset(cpu_env); gen_helper_reset(tcg_env);
} }
#endif #endif
@ -3971,11 +3971,11 @@ DISAS_INSN(bfext_mem)
} }
if (is_sign) { if (is_sign) {
gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len); gen_helper_bfexts_mem(dest, tcg_env, addr, ofs, len);
tcg_gen_mov_i32(QREG_CC_N, dest); tcg_gen_mov_i32(QREG_CC_N, dest);
} else { } else {
TCGv_i64 tmp = tcg_temp_new_i64(); TCGv_i64 tmp = tcg_temp_new_i64();
gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len); gen_helper_bfextu_mem(tmp, tcg_env, addr, ofs, len);
tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp); tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
} }
set_cc_op(s, CC_OP_LOGIC); set_cc_op(s, CC_OP_LOGIC);
@ -4093,21 +4093,21 @@ DISAS_INSN(bfop_mem)
switch (insn & 0x0f00) { switch (insn & 0x0f00) {
case 0x0a00: /* bfchg */ case 0x0a00: /* bfchg */
gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len); gen_helper_bfchg_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break; break;
case 0x0c00: /* bfclr */ case 0x0c00: /* bfclr */
gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len); gen_helper_bfclr_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break; break;
case 0x0d00: /* bfffo */ case 0x0d00: /* bfffo */
t64 = tcg_temp_new_i64(); t64 = tcg_temp_new_i64();
gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len); gen_helper_bfffo_mem(t64, tcg_env, addr, ofs, len);
tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64); tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
break; break;
case 0x0e00: /* bfset */ case 0x0e00: /* bfset */
gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len); gen_helper_bfset_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break; break;
case 0x0800: /* bftst */ case 0x0800: /* bftst */
gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len); gen_helper_bfexts_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -4208,7 +4208,7 @@ DISAS_INSN(bfins_mem)
ofs = tcg_constant_i32(extract32(ext, 6, 5)); ofs = tcg_constant_i32(extract32(ext, 6, 5));
} }
gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len); gen_helper_bfins_mem(QREG_CC_N, tcg_env, addr, src, ofs, len);
set_cc_op(s, CC_OP_LOGIC); set_cc_op(s, CC_OP_LOGIC);
} }
@ -4243,7 +4243,7 @@ DISAS_INSN(chk)
reg = gen_extend(s, DREG(insn, 9), opsize, 1); reg = gen_extend(s, DREG(insn, 9), opsize, 1);
gen_flush_flags(s); gen_flush_flags(s);
gen_helper_chk(cpu_env, reg, src); gen_helper_chk(tcg_env, reg, src);
} }
DISAS_INSN(chk2) DISAS_INSN(chk2)
@ -4288,7 +4288,7 @@ DISAS_INSN(chk2)
} }
gen_flush_flags(s); gen_flush_flags(s);
gen_helper_chk2(cpu_env, reg, bound1, bound2); gen_helper_chk2(tcg_env, reg, bound1, bound2);
} }
static void m68k_copy_line(TCGv dst, TCGv src, int index) static void m68k_copy_line(TCGv dst, TCGv src, int index)
@ -4462,7 +4462,7 @@ DISAS_INSN(move_from_usp)
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return; return;
} }
tcg_gen_ld_i32(AREG(insn, 0), cpu_env, tcg_gen_ld_i32(AREG(insn, 0), tcg_env,
offsetof(CPUM68KState, sp[M68K_USP])); offsetof(CPUM68KState, sp[M68K_USP]));
} }
@ -4472,7 +4472,7 @@ DISAS_INSN(move_to_usp)
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return; return;
} }
tcg_gen_st_i32(AREG(insn, 0), cpu_env, tcg_gen_st_i32(AREG(insn, 0), tcg_env,
offsetof(CPUM68KState, sp[M68K_USP])); offsetof(CPUM68KState, sp[M68K_USP]));
} }
@ -4528,7 +4528,7 @@ DISAS_INSN(cf_movec)
} else { } else {
reg = DREG(ext, 12); reg = DREG(ext, 12);
} }
gen_helper_cf_movec_to(cpu_env, tcg_constant_i32(ext & 0xfff), reg); gen_helper_cf_movec_to(tcg_env, tcg_constant_i32(ext & 0xfff), reg);
gen_exit_tb(s); gen_exit_tb(s);
} }
@ -4551,9 +4551,9 @@ DISAS_INSN(m68k_movec)
} }
creg = tcg_constant_i32(ext & 0xfff); creg = tcg_constant_i32(ext & 0xfff);
if (insn & 1) { if (insn & 1) {
gen_helper_m68k_movec_to(cpu_env, creg, reg); gen_helper_m68k_movec_to(tcg_env, creg, reg);
} else { } else {
gen_helper_m68k_movec_from(reg, cpu_env, creg); gen_helper_m68k_movec_from(reg, tcg_env, creg);
} }
gen_exit_tb(s); gen_exit_tb(s);
} }
@ -4605,7 +4605,7 @@ DISAS_INSN(pflush)
} }
opmode = tcg_constant_i32((insn >> 3) & 3); opmode = tcg_constant_i32((insn >> 3) & 3);
gen_helper_pflush(cpu_env, AREG(insn, 0), opmode); gen_helper_pflush(tcg_env, AREG(insn, 0), opmode);
} }
DISAS_INSN(ptest) DISAS_INSN(ptest)
@ -4617,7 +4617,7 @@ DISAS_INSN(ptest)
return; return;
} }
is_read = tcg_constant_i32((insn >> 5) & 1); is_read = tcg_constant_i32((insn >> 5) & 1);
gen_helper_ptest(cpu_env, AREG(insn, 0), is_read); gen_helper_ptest(tcg_env, AREG(insn, 0), is_read);
} }
#endif #endif
@ -4703,10 +4703,10 @@ static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
tcg_gen_movi_i32(res, 0); tcg_gen_movi_i32(res, 0);
break; break;
case M68K_FPSR: case M68K_FPSR:
tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr)); tcg_gen_ld_i32(res, tcg_env, offsetof(CPUM68KState, fpsr));
break; break;
case M68K_FPCR: case M68K_FPCR:
tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr)); tcg_gen_ld_i32(res, tcg_env, offsetof(CPUM68KState, fpcr));
break; break;
} }
} }
@ -4717,10 +4717,10 @@ static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
case M68K_FPIAR: case M68K_FPIAR:
break; break;
case M68K_FPSR: case M68K_FPSR:
tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr)); tcg_gen_st_i32(val, tcg_env, offsetof(CPUM68KState, fpsr));
break; break;
case M68K_FPCR: case M68K_FPCR:
gen_helper_set_fpcr(cpu_env, val); gen_helper_set_fpcr(tcg_env, val);
break; break;
} }
} }
@ -4877,23 +4877,23 @@ static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
* only available to store register to memory * only available to store register to memory
*/ */
if (opsize == OS_EXTENDED) { if (opsize == OS_EXTENDED) {
gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp); gen_helper_fmovemx_st_predec(tmp, tcg_env, addr, tmp);
} else { } else {
gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp); gen_helper_fmovemd_st_predec(tmp, tcg_env, addr, tmp);
} }
} else { } else {
/* postincrement addressing mode */ /* postincrement addressing mode */
if (opsize == OS_EXTENDED) { if (opsize == OS_EXTENDED) {
if (is_load) { if (is_load) {
gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp); gen_helper_fmovemx_ld_postinc(tmp, tcg_env, addr, tmp);
} else { } else {
gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp); gen_helper_fmovemx_st_postinc(tmp, tcg_env, addr, tmp);
} }
} else { } else {
if (is_load) { if (is_load) {
gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp); gen_helper_fmovemd_ld_postinc(tmp, tcg_env, addr, tmp);
} else { } else {
gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp); gen_helper_fmovemd_st_postinc(tmp, tcg_env, addr, tmp);
} }
} }
} }
@ -4925,7 +4925,7 @@ DISAS_INSN(fpu)
/* fmovecr */ /* fmovecr */
TCGv rom_offset = tcg_constant_i32(opmode); TCGv rom_offset = tcg_constant_i32(opmode);
cpu_dest = gen_fp_ptr(REG(ext, 7)); cpu_dest = gen_fp_ptr(REG(ext, 7));
gen_helper_fconst(cpu_env, cpu_dest, rom_offset); gen_helper_fconst(tcg_env, cpu_dest, rom_offset);
return; return;
} }
break; break;
@ -4936,7 +4936,7 @@ DISAS_INSN(fpu)
EA_STORE, IS_USER(s)) == -1) { EA_STORE, IS_USER(s)) == -1) {
gen_addr_fault(s); gen_addr_fault(s);
} }
gen_helper_ftst(cpu_env, cpu_src); gen_helper_ftst(tcg_env, cpu_src);
return; return;
case 4: /* fmove to control register. */ case 4: /* fmove to control register. */
case 5: /* fmove from control register. */ case 5: /* fmove from control register. */
@ -4970,172 +4970,172 @@ DISAS_INSN(fpu)
gen_fp_move(cpu_dest, cpu_src); gen_fp_move(cpu_dest, cpu_src);
break; break;
case 0x40: /* fsmove */ case 0x40: /* fsmove */
gen_helper_fsround(cpu_env, cpu_dest, cpu_src); gen_helper_fsround(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x44: /* fdmove */ case 0x44: /* fdmove */
gen_helper_fdround(cpu_env, cpu_dest, cpu_src); gen_helper_fdround(tcg_env, cpu_dest, cpu_src);
break; break;
case 1: /* fint */ case 1: /* fint */
gen_helper_firound(cpu_env, cpu_dest, cpu_src); gen_helper_firound(tcg_env, cpu_dest, cpu_src);
break; break;
case 2: /* fsinh */ case 2: /* fsinh */
gen_helper_fsinh(cpu_env, cpu_dest, cpu_src); gen_helper_fsinh(tcg_env, cpu_dest, cpu_src);
break; break;
case 3: /* fintrz */ case 3: /* fintrz */
gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src); gen_helper_fitrunc(tcg_env, cpu_dest, cpu_src);
break; break;
case 4: /* fsqrt */ case 4: /* fsqrt */
gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src); gen_helper_fsqrt(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x41: /* fssqrt */ case 0x41: /* fssqrt */
gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src); gen_helper_fssqrt(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x45: /* fdsqrt */ case 0x45: /* fdsqrt */
gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src); gen_helper_fdsqrt(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x06: /* flognp1 */ case 0x06: /* flognp1 */
gen_helper_flognp1(cpu_env, cpu_dest, cpu_src); gen_helper_flognp1(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x08: /* fetoxm1 */ case 0x08: /* fetoxm1 */
gen_helper_fetoxm1(cpu_env, cpu_dest, cpu_src); gen_helper_fetoxm1(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x09: /* ftanh */ case 0x09: /* ftanh */
gen_helper_ftanh(cpu_env, cpu_dest, cpu_src); gen_helper_ftanh(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x0a: /* fatan */ case 0x0a: /* fatan */
gen_helper_fatan(cpu_env, cpu_dest, cpu_src); gen_helper_fatan(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x0c: /* fasin */ case 0x0c: /* fasin */
gen_helper_fasin(cpu_env, cpu_dest, cpu_src); gen_helper_fasin(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x0d: /* fatanh */ case 0x0d: /* fatanh */
gen_helper_fatanh(cpu_env, cpu_dest, cpu_src); gen_helper_fatanh(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x0e: /* fsin */ case 0x0e: /* fsin */
gen_helper_fsin(cpu_env, cpu_dest, cpu_src); gen_helper_fsin(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x0f: /* ftan */ case 0x0f: /* ftan */
gen_helper_ftan(cpu_env, cpu_dest, cpu_src); gen_helper_ftan(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x10: /* fetox */ case 0x10: /* fetox */
gen_helper_fetox(cpu_env, cpu_dest, cpu_src); gen_helper_fetox(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x11: /* ftwotox */ case 0x11: /* ftwotox */
gen_helper_ftwotox(cpu_env, cpu_dest, cpu_src); gen_helper_ftwotox(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x12: /* ftentox */ case 0x12: /* ftentox */
gen_helper_ftentox(cpu_env, cpu_dest, cpu_src); gen_helper_ftentox(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x14: /* flogn */ case 0x14: /* flogn */
gen_helper_flogn(cpu_env, cpu_dest, cpu_src); gen_helper_flogn(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x15: /* flog10 */ case 0x15: /* flog10 */
gen_helper_flog10(cpu_env, cpu_dest, cpu_src); gen_helper_flog10(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x16: /* flog2 */ case 0x16: /* flog2 */
gen_helper_flog2(cpu_env, cpu_dest, cpu_src); gen_helper_flog2(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x18: /* fabs */ case 0x18: /* fabs */
gen_helper_fabs(cpu_env, cpu_dest, cpu_src); gen_helper_fabs(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x58: /* fsabs */ case 0x58: /* fsabs */
gen_helper_fsabs(cpu_env, cpu_dest, cpu_src); gen_helper_fsabs(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x5c: /* fdabs */ case 0x5c: /* fdabs */
gen_helper_fdabs(cpu_env, cpu_dest, cpu_src); gen_helper_fdabs(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x19: /* fcosh */ case 0x19: /* fcosh */
gen_helper_fcosh(cpu_env, cpu_dest, cpu_src); gen_helper_fcosh(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x1a: /* fneg */ case 0x1a: /* fneg */
gen_helper_fneg(cpu_env, cpu_dest, cpu_src); gen_helper_fneg(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x5a: /* fsneg */ case 0x5a: /* fsneg */
gen_helper_fsneg(cpu_env, cpu_dest, cpu_src); gen_helper_fsneg(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x5e: /* fdneg */ case 0x5e: /* fdneg */
gen_helper_fdneg(cpu_env, cpu_dest, cpu_src); gen_helper_fdneg(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x1c: /* facos */ case 0x1c: /* facos */
gen_helper_facos(cpu_env, cpu_dest, cpu_src); gen_helper_facos(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x1d: /* fcos */ case 0x1d: /* fcos */
gen_helper_fcos(cpu_env, cpu_dest, cpu_src); gen_helper_fcos(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x1e: /* fgetexp */ case 0x1e: /* fgetexp */
gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src); gen_helper_fgetexp(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x1f: /* fgetman */ case 0x1f: /* fgetman */
gen_helper_fgetman(cpu_env, cpu_dest, cpu_src); gen_helper_fgetman(tcg_env, cpu_dest, cpu_src);
break; break;
case 0x20: /* fdiv */ case 0x20: /* fdiv */
gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fdiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x60: /* fsdiv */ case 0x60: /* fsdiv */
gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fsdiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x64: /* fddiv */ case 0x64: /* fddiv */
gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fddiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x21: /* fmod */ case 0x21: /* fmod */
gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fmod(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x22: /* fadd */ case 0x22: /* fadd */
gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fadd(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x62: /* fsadd */ case 0x62: /* fsadd */
gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fsadd(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x66: /* fdadd */ case 0x66: /* fdadd */
gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fdadd(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x23: /* fmul */ case 0x23: /* fmul */
gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x63: /* fsmul */ case 0x63: /* fsmul */
gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fsmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x67: /* fdmul */ case 0x67: /* fdmul */
gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fdmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x24: /* fsgldiv */ case 0x24: /* fsgldiv */
gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fsgldiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x25: /* frem */ case 0x25: /* frem */
gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_frem(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x26: /* fscale */ case 0x26: /* fscale */
gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fscale(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x27: /* fsglmul */ case 0x27: /* fsglmul */
gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fsglmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x28: /* fsub */ case 0x28: /* fsub */
gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fsub(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x68: /* fssub */ case 0x68: /* fssub */
gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fssub(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x6c: /* fdsub */ case 0x6c: /* fdsub */
gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest); gen_helper_fdsub(tcg_env, cpu_dest, cpu_src, cpu_dest);
break; break;
case 0x30: case 0x31: case 0x32: case 0x30: case 0x31: case 0x32:
case 0x33: case 0x34: case 0x35: case 0x33: case 0x34: case 0x35:
case 0x36: case 0x37: { case 0x36: case 0x37: {
TCGv_ptr cpu_dest2 = gen_fp_ptr(REG(ext, 0)); TCGv_ptr cpu_dest2 = gen_fp_ptr(REG(ext, 0));
gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src); gen_helper_fsincos(tcg_env, cpu_dest, cpu_dest2, cpu_src);
} }
break; break;
case 0x38: /* fcmp */ case 0x38: /* fcmp */
gen_helper_fcmp(cpu_env, cpu_src, cpu_dest); gen_helper_fcmp(tcg_env, cpu_src, cpu_dest);
return; return;
case 0x3a: /* ftst */ case 0x3a: /* ftst */
gen_helper_ftst(cpu_env, cpu_src); gen_helper_ftst(tcg_env, cpu_src);
return; return;
default: default:
goto undef; goto undef;
} }
gen_helper_ftst(cpu_env, cpu_dest); gen_helper_ftst(tcg_env, cpu_dest);
return; return;
undef: undef:
/* FIXME: Is this right for offset addressing modes? */ /* FIXME: Is this right for offset addressing modes? */
@ -5466,12 +5466,12 @@ DISAS_INSN(mac)
ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
} }
if (s->env->macsr & MACSR_FI) { if (s->env->macsr & MACSR_FI) {
gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); gen_helper_macmulf(s->mactmp, tcg_env, rx, ry);
} else { } else {
if (s->env->macsr & MACSR_SU) if (s->env->macsr & MACSR_SU)
gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); gen_helper_macmuls(s->mactmp, tcg_env, rx, ry);
else else
gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); gen_helper_macmulu(s->mactmp, tcg_env, rx, ry);
switch ((ext >> 9) & 3) { switch ((ext >> 9) & 3) {
case 1: case 1:
tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
@ -5507,11 +5507,11 @@ DISAS_INSN(mac)
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
if (s->env->macsr & MACSR_FI) if (s->env->macsr & MACSR_FI)
gen_helper_macsatf(cpu_env, tcg_constant_i32(acc)); gen_helper_macsatf(tcg_env, tcg_constant_i32(acc));
else if (s->env->macsr & MACSR_SU) else if (s->env->macsr & MACSR_SU)
gen_helper_macsats(cpu_env, tcg_constant_i32(acc)); gen_helper_macsats(tcg_env, tcg_constant_i32(acc));
else else
gen_helper_macsatu(cpu_env, tcg_constant_i32(acc)); gen_helper_macsatu(tcg_env, tcg_constant_i32(acc));
#if 0 #if 0
/* Disabled because conditional branches clobber temporary vars. */ /* Disabled because conditional branches clobber temporary vars. */
@ -5539,18 +5539,18 @@ DISAS_INSN(mac)
else else
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
if (s->env->macsr & MACSR_FI) if (s->env->macsr & MACSR_FI)
gen_helper_macsatf(cpu_env, tcg_constant_i32(acc)); gen_helper_macsatf(tcg_env, tcg_constant_i32(acc));
else if (s->env->macsr & MACSR_SU) else if (s->env->macsr & MACSR_SU)
gen_helper_macsats(cpu_env, tcg_constant_i32(acc)); gen_helper_macsats(tcg_env, tcg_constant_i32(acc));
else else
gen_helper_macsatu(cpu_env, tcg_constant_i32(acc)); gen_helper_macsatu(tcg_env, tcg_constant_i32(acc));
#if 0 #if 0
/* Disabled because conditional branches clobber temporary vars. */ /* Disabled because conditional branches clobber temporary vars. */
if (l1 != -1) if (l1 != -1)
gen_set_label(l1); gen_set_label(l1);
#endif #endif
} }
gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(acc)); gen_helper_mac_set_flags(tcg_env, tcg_constant_i32(acc));
if (insn & 0x30) { if (insn & 0x30) {
TCGv rw; TCGv rw;
@ -5580,7 +5580,7 @@ DISAS_INSN(from_mac)
accnum = (insn >> 9) & 3; accnum = (insn >> 9) & 3;
acc = MACREG(accnum); acc = MACREG(accnum);
if (s->env->macsr & MACSR_FI) { if (s->env->macsr & MACSR_FI) {
gen_helper_get_macf(rx, cpu_env, acc); gen_helper_get_macf(rx, tcg_env, acc);
} else if ((s->env->macsr & MACSR_OMC) == 0) { } else if ((s->env->macsr & MACSR_OMC) == 0) {
tcg_gen_extrl_i64_i32(rx, acc); tcg_gen_extrl_i64_i32(rx, acc);
} else if (s->env->macsr & MACSR_SU) { } else if (s->env->macsr & MACSR_SU) {
@ -5601,9 +5601,9 @@ DISAS_INSN(move_mac)
TCGv dest; TCGv dest;
src = insn & 3; src = insn & 3;
dest = tcg_constant_i32((insn >> 9) & 3); dest = tcg_constant_i32((insn >> 9) & 3);
gen_helper_mac_move(cpu_env, dest, tcg_constant_i32(src)); gen_helper_mac_move(tcg_env, dest, tcg_constant_i32(src));
gen_mac_clear_flags(); gen_mac_clear_flags();
gen_helper_mac_set_flags(cpu_env, dest); gen_helper_mac_set_flags(tcg_env, dest);
} }
DISAS_INSN(from_macsr) DISAS_INSN(from_macsr)
@ -5628,9 +5628,9 @@ DISAS_INSN(from_mext)
reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
acc = tcg_constant_i32((insn & 0x400) ? 2 : 0); acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI) if (s->env->macsr & MACSR_FI)
gen_helper_get_mac_extf(reg, cpu_env, acc); gen_helper_get_mac_extf(reg, tcg_env, acc);
else else
gen_helper_get_mac_exti(reg, cpu_env, acc); gen_helper_get_mac_exti(reg, tcg_env, acc);
} }
DISAS_INSN(macsr_to_ccr) DISAS_INSN(macsr_to_ccr)
@ -5639,7 +5639,7 @@ DISAS_INSN(macsr_to_ccr)
/* Note that X and C are always cleared. */ /* Note that X and C are always cleared. */
tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V); tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V);
gen_helper_set_ccr(cpu_env, tmp); gen_helper_set_ccr(tcg_env, tmp);
set_cc_op(s, CC_OP_FLAGS); set_cc_op(s, CC_OP_FLAGS);
} }
@ -5661,14 +5661,14 @@ DISAS_INSN(to_mac)
} }
tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
gen_mac_clear_flags(); gen_mac_clear_flags();
gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(accnum)); gen_helper_mac_set_flags(tcg_env, tcg_constant_i32(accnum));
} }
DISAS_INSN(to_macsr) DISAS_INSN(to_macsr)
{ {
TCGv val; TCGv val;
SRC_EA(env, val, OS_LONG, 0, NULL); SRC_EA(env, val, OS_LONG, 0, NULL);
gen_helper_set_macsr(cpu_env, val); gen_helper_set_macsr(tcg_env, val);
gen_exit_tb(s); gen_exit_tb(s);
} }
@ -5686,11 +5686,11 @@ DISAS_INSN(to_mext)
SRC_EA(env, val, OS_LONG, 0, NULL); SRC_EA(env, val, OS_LONG, 0, NULL);
acc = tcg_constant_i32((insn & 0x400) ? 2 : 0); acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI) if (s->env->macsr & MACSR_FI)
gen_helper_set_mac_extf(cpu_env, val, acc); gen_helper_set_mac_extf(tcg_env, val, acc);
else if (s->env->macsr & MACSR_SU) else if (s->env->macsr & MACSR_SU)
gen_helper_set_mac_exts(cpu_env, val, acc); gen_helper_set_mac_exts(tcg_env, val, acc);
else else
gen_helper_set_mac_extu(cpu_env, val, acc); gen_helper_set_mac_extu(tcg_env, val, acc);
} }
static disas_proc opcode_table[65536]; static disas_proc opcode_table[65536];

50
target/microblaze/translate.c
View File

@ -102,7 +102,7 @@ static void t_sync_flags(DisasContext *dc)
static void gen_raise_exception(DisasContext *dc, uint32_t index) static void gen_raise_exception(DisasContext *dc, uint32_t index)
{ {
gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); gen_helper_raise_exception(tcg_env, tcg_constant_i32(index));
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
} }
@ -116,7 +116,7 @@ static void gen_raise_exception_sync(DisasContext *dc, uint32_t index)
static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
{ {
TCGv_i32 tmp = tcg_constant_i32(esr_ec); TCGv_i32 tmp = tcg_constant_i32(esr_ec);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr)); tcg_gen_st_i32(tmp, tcg_env, offsetof(CPUMBState, esr));
gen_raise_exception_sync(dc, EXCP_HW_EXCP); gen_raise_exception_sync(dc, EXCP_HW_EXCP);
} }
@ -295,11 +295,11 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects,
#define ENV_WRAPPER2(NAME, HELPER) \ #define ENV_WRAPPER2(NAME, HELPER) \
static void NAME(TCGv_i32 out, TCGv_i32 ina) \ static void NAME(TCGv_i32 out, TCGv_i32 ina) \
{ HELPER(out, cpu_env, ina); } { HELPER(out, tcg_env, ina); }
#define ENV_WRAPPER3(NAME, HELPER) \ #define ENV_WRAPPER3(NAME, HELPER) \
static void NAME(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) \ static void NAME(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) \
{ HELPER(out, cpu_env, ina, inb); } { HELPER(out, tcg_env, ina, inb); }
/* No input carry, but output carry. */ /* No input carry, but output carry. */
static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
@ -472,12 +472,12 @@ DO_TYPEA0_CFG(fsqrt, use_fpu >= 2, true, gen_fsqrt)
/* Does not use ENV_WRAPPER3, because arguments are swapped as well. */ /* Does not use ENV_WRAPPER3, because arguments are swapped as well. */
static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{ {
gen_helper_divs(out, cpu_env, inb, ina); gen_helper_divs(out, tcg_env, inb, ina);
} }
static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{ {
gen_helper_divu(out, cpu_env, inb, ina); gen_helper_divu(out, tcg_env, inb, ina);
} }
DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) DO_TYPEA_CFG(idiv, use_div, true, gen_idiv)
@ -643,7 +643,7 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
} }
if ((ra == 1 || rb == 1) && dc->cfg->stackprot) { if ((ra == 1 || rb == 1) && dc->cfg->stackprot) {
gen_helper_stackprot(cpu_env, ret); gen_helper_stackprot(tcg_env, ret);
} }
return ret; return ret;
} }
@ -662,7 +662,7 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
} }
if (ra == 1 && dc->cfg->stackprot) { if (ra == 1 && dc->cfg->stackprot) {
gen_helper_stackprot(cpu_env, ret); gen_helper_stackprot(tcg_env, ret);
} }
return ret; return ret;
} }
@ -1232,7 +1232,7 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg)
t_sync_flags(dc); t_sync_flags(dc);
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(MicroBlazeCPU, env) -offsetof(MicroBlazeCPU, env)
+offsetof(CPUState, halted)); +offsetof(CPUState, halted));
@ -1381,13 +1381,13 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
tcg_gen_andi_i32(cpu_msr, src, ~(MSR_C | MSR_CC | MSR_PVR)); tcg_gen_andi_i32(cpu_msr, src, ~(MSR_C | MSR_CC | MSR_PVR));
break; break;
case SR_FSR: case SR_FSR:
tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr)); tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, fsr));
break; break;
case 0x800: case 0x800:
tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, slr)); tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, slr));
break; break;
case 0x802: case 0x802:
tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, shr)); tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, shr));
break; break;
case 0x1000: /* PID */ case 0x1000: /* PID */
@ -1400,7 +1400,7 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
TCGv_i32 tmp_ext = tcg_constant_i32(arg->e); TCGv_i32 tmp_ext = tcg_constant_i32(arg->e);
TCGv_i32 tmp_reg = tcg_constant_i32(arg->rs & 7); TCGv_i32 tmp_reg = tcg_constant_i32(arg->rs & 7);
gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src); gen_helper_mmu_write(tcg_env, tmp_ext, tmp_reg, src);
} }
break; break;
@ -1422,7 +1422,7 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
case SR_EAR: case SR_EAR:
{ {
TCGv_i64 t64 = tcg_temp_new_i64(); TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); tcg_gen_ld_i64(t64, tcg_env, offsetof(CPUMBState, ear));
tcg_gen_extrh_i64_i32(dest, t64); tcg_gen_extrh_i64_i32(dest, t64);
} }
return true; return true;
@ -1452,27 +1452,27 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
case SR_EAR: case SR_EAR:
{ {
TCGv_i64 t64 = tcg_temp_new_i64(); TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); tcg_gen_ld_i64(t64, tcg_env, offsetof(CPUMBState, ear));
tcg_gen_extrl_i64_i32(dest, t64); tcg_gen_extrl_i64_i32(dest, t64);
} }
break; break;
case SR_ESR: case SR_ESR:
tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, esr)); tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, esr));
break; break;
case SR_FSR: case SR_FSR:
tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, fsr)); tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, fsr));
break; break;
case SR_BTR: case SR_BTR:
tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, btr)); tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, btr));
break; break;
case SR_EDR: case SR_EDR:
tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, edr)); tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, edr));
break; break;
case 0x800: case 0x800:
tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, slr)); tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, slr));
break; break;
case 0x802: case 0x802:
tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, shr)); tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, shr));
break; break;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -1486,13 +1486,13 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
TCGv_i32 tmp_ext = tcg_constant_i32(arg->e); TCGv_i32 tmp_ext = tcg_constant_i32(arg->e);
TCGv_i32 tmp_reg = tcg_constant_i32(arg->rs & 7); TCGv_i32 tmp_reg = tcg_constant_i32(arg->rs & 7);
gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg); gen_helper_mmu_read(dest, tcg_env, tmp_ext, tmp_reg);
} }
break; break;
#endif #endif
case 0x2000 ... 0x200c: case 0x2000 ... 0x200c:
tcg_gen_ld_i32(dest, cpu_env, tcg_gen_ld_i32(dest, tcg_env,
offsetof(MicroBlazeCPU, cfg.pvr_regs[arg->rs - 0x2000]) offsetof(MicroBlazeCPU, cfg.pvr_regs[arg->rs - 0x2000])
- offsetof(MicroBlazeCPU, env)); - offsetof(MicroBlazeCPU, env));
break; break;
@ -1882,9 +1882,9 @@ void mb_tcg_init(void)
for (int i = 0; i < ARRAY_SIZE(i32s); ++i) { for (int i = 0; i < ARRAY_SIZE(i32s); ++i) {
*i32s[i].var = *i32s[i].var =
tcg_global_mem_new_i32(cpu_env, i32s[i].ofs, i32s[i].name); tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name);
} }
cpu_res_addr = cpu_res_addr =
tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr), "res_addr");
} }

6
target/mips/tcg/lcsr_translate.c
View File

@ -22,7 +22,7 @@ static bool trans_CPUCFG(DisasContext *ctx, arg_CPUCFG *a)
TCGv src1 = tcg_temp_new(); TCGv src1 = tcg_temp_new();
gen_load_gpr(src1, a->rs); gen_load_gpr(src1, a->rs);
gen_helper_lcsr_cpucfg(dest, cpu_env, src1); gen_helper_lcsr_cpucfg(dest, tcg_env, src1);
gen_store_gpr(dest, a->rd); gen_store_gpr(dest, a->rd);
return true; return true;
@ -37,7 +37,7 @@ static bool gen_rdcsr(DisasContext *ctx, arg_r *a,
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
gen_load_gpr(src1, a->rs); gen_load_gpr(src1, a->rs);
func(dest, cpu_env, src1); func(dest, tcg_env, src1);
gen_store_gpr(dest, a->rd); gen_store_gpr(dest, a->rd);
return true; return true;
@ -52,7 +52,7 @@ static bool gen_wrcsr(DisasContext *ctx, arg_r *a,
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
gen_load_gpr(addr, a->rs); gen_load_gpr(addr, a->rs);
gen_load_gpr(val, a->rd); gen_load_gpr(val, a->rd);
func(cpu_env, addr, val); func(tcg_env, addr, val);
return true; return true;
} }

12
target/mips/tcg/micromips_translate.c.inc
View File

@ -710,17 +710,17 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
switch (opc) { switch (opc) {
case LWM32: case LWM32:
gen_helper_lwm(cpu_env, t0, t1, t2); gen_helper_lwm(tcg_env, t0, t1, t2);
break; break;
case SWM32: case SWM32:
gen_helper_swm(cpu_env, t0, t1, t2); gen_helper_swm(tcg_env, t0, t1, t2);
break; break;
#ifdef TARGET_MIPS64 #ifdef TARGET_MIPS64
case LDM: case LDM:
gen_helper_ldm(cpu_env, t0, t1, t2); gen_helper_ldm(tcg_env, t0, t1, t2);
break; break;
case SDM: case SDM:
gen_helper_sdm(cpu_env, t0, t1, t2); gen_helper_sdm(tcg_env, t0, t1, t2);
break; break;
#endif #endif
} }
@ -1271,7 +1271,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_di(t0, cpu_env); gen_helper_di(t0, tcg_env);
gen_store_gpr(t0, rs); gen_store_gpr(t0, rs);
/* /*
* Stop translation as we may have switched the execution * Stop translation as we may have switched the execution
@ -1286,7 +1286,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_ei(t0, cpu_env); gen_helper_ei(t0, tcg_env);
gen_store_gpr(t0, rs); gen_store_gpr(t0, rs);
/* /*
* DISAS_STOP isn't sufficient, we need to ensure we break out * DISAS_STOP isn't sufficient, we need to ensure we break out

34
target/mips/tcg/msa_translate.c
View File

@ -140,7 +140,7 @@ void msa_translate_init(void)
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] = msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); tcg_global_mem_new_i64(tcg_env, off, msaregnames[i * 2 + 1]);
} }
} }
@ -288,7 +288,7 @@ static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *a,
return true; return true;
} }
gen_msa_i8(cpu_env, gen_msa_i8(tcg_env,
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws), tcg_constant_i32(a->ws),
tcg_constant_i32(a->sa)); tcg_constant_i32(a->sa));
@ -314,7 +314,7 @@ static bool trans_SHF(DisasContext *ctx, arg_msa_i *a)
return true; return true;
} }
gen_helper_msa_shf_df(cpu_env, gen_helper_msa_shf_df(tcg_env,
tcg_constant_i32(a->df), tcg_constant_i32(a->df),
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws), tcg_constant_i32(a->ws),
@ -330,7 +330,7 @@ static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a,
return true; return true;
} }
gen_msa_i5(cpu_env, gen_msa_i5(tcg_env,
tcg_constant_i32(a->df), tcg_constant_i32(a->df),
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws), tcg_constant_i32(a->ws),
@ -357,7 +357,7 @@ static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a)
return true; return true;
} }
gen_helper_msa_ldi_df(cpu_env, gen_helper_msa_ldi_df(tcg_env,
tcg_constant_i32(a->df), tcg_constant_i32(a->df),
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->sa)); tcg_constant_i32(a->sa));
@ -376,7 +376,7 @@ static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a,
return true; return true;
} }
gen_msa_bit(cpu_env, gen_msa_bit(tcg_env,
tcg_constant_i32(a->df), tcg_constant_i32(a->df),
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws), tcg_constant_i32(a->ws),
@ -405,7 +405,7 @@ static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
return true; return true;
} }
gen_msa_3rf(cpu_env, gen_msa_3rf(tcg_env,
tcg_constant_i32(a->df), tcg_constant_i32(a->df),
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws), tcg_constant_i32(a->ws),
@ -425,7 +425,7 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
return true; return true;
} }
gen_msa_3r(cpu_env, gen_msa_3r(tcg_env,
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws), tcg_constant_i32(a->ws),
tcg_constant_i32(a->wt)); tcg_constant_i32(a->wt));
@ -519,7 +519,7 @@ static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
return true; return true;
} }
gen_helper_msa_move_v(cpu_env, gen_helper_msa_move_v(tcg_env,
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws)); tcg_constant_i32(a->ws));
@ -537,7 +537,7 @@ static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
telm = tcg_temp_new(); telm = tcg_temp_new();
gen_load_gpr(telm, a->ws); gen_load_gpr(telm, a->ws);
gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd)); gen_helper_msa_ctcmsa(tcg_env, telm, tcg_constant_i32(a->wd));
return true; return true;
} }
@ -552,7 +552,7 @@ static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
telm = tcg_temp_new(); telm = tcg_temp_new();
gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws)); gen_helper_msa_cfcmsa(telm, tcg_env, tcg_constant_i32(a->ws));
gen_store_gpr(telm, a->wd); gen_store_gpr(telm, a->wd);
return true; return true;
@ -569,7 +569,7 @@ static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a,
return true; return true;
} }
gen_msa_elm_df(cpu_env, gen_msa_elm_df(tcg_env,
tcg_constant_i32(a->df), tcg_constant_i32(a->df),
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws), tcg_constant_i32(a->ws),
@ -593,7 +593,7 @@ static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a,
return true; return true;
} }
gen_msa_elm[a->df](cpu_env, gen_msa_elm[a->df](tcg_env,
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws), tcg_constant_i32(a->ws),
tcg_constant_i32(a->n)); tcg_constant_i32(a->n));
@ -698,7 +698,7 @@ static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
return true; return true;
} }
gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); gen_msa_2r(tcg_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws));
return true; return true;
} }
@ -718,7 +718,7 @@ static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
return true; return true;
} }
gen_helper_msa_fill_df(cpu_env, gen_helper_msa_fill_df(tcg_env,
tcg_constant_i32(a->df), tcg_constant_i32(a->df),
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws)); tcg_constant_i32(a->ws));
@ -733,7 +733,7 @@ static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
return true; return true;
} }
gen_msa_2rf(cpu_env, gen_msa_2rf(tcg_env,
tcg_constant_i32(a->df), tcg_constant_i32(a->df),
tcg_constant_i32(a->wd), tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws)); tcg_constant_i32(a->ws));
@ -770,7 +770,7 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,
taddr = tcg_temp_new(); taddr = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); gen_msa_ldst(tcg_env, tcg_constant_i32(a->wd), taddr);
return true; return true;
} }

4
target/mips/tcg/mxu_translate.c
View File

@ -617,12 +617,12 @@ static const char mxuregnames[NUMBER_OF_MXU_REGISTERS][4] = {
void mxu_translate_init(void) void mxu_translate_init(void)
{ {
for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
mxu_gpr[i] = tcg_global_mem_new(cpu_env, mxu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.mxu_gpr[i]), offsetof(CPUMIPSState, active_tc.mxu_gpr[i]),
mxuregnames[i]); mxuregnames[i]);
} }
mxu_CR = tcg_global_mem_new(cpu_env, mxu_CR = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.mxu_cr), offsetof(CPUMIPSState, active_tc.mxu_cr),
mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
} }

200
target/mips/tcg/nanomips_translate.c.inc
View File

@ -1006,8 +1006,8 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
} }
gen_store_gpr(tmp1, reg1); gen_store_gpr(tmp1, reg1);
gen_store_gpr(tmp2, reg2); gen_store_gpr(tmp2, reg2);
tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp)); tcg_gen_st_i64(tval, tcg_env, offsetof(CPUMIPSState, llval_wp));
tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr)); tcg_gen_st_tl(taddr, tcg_env, offsetof(CPUMIPSState, lladdr));
} }
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
@ -1025,7 +1025,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
gen_base_offset_addr(ctx, taddr, base, offset); gen_base_offset_addr(ctx, taddr, base, offset);
tcg_gen_ld_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr)); tcg_gen_ld_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr));
tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail); tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail);
gen_load_gpr(tmp1, reg1); gen_load_gpr(tmp1, reg1);
@ -1037,7 +1037,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
tcg_gen_concat_tl_i64(tval, tmp1, tmp2); tcg_gen_concat_tl_i64(tval, tmp1, tmp2);
} }
tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp)); tcg_gen_ld_i64(llval, tcg_env, offsetof(CPUMIPSState, llval_wp));
tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval, tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
eva ? MIPS_HFLAG_UM : ctx->mem_idx, eva ? MIPS_HFLAG_UM : ctx->mem_idx,
MO_64 | MO_ALIGN); MO_64 | MO_ALIGN);
@ -1053,7 +1053,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
} }
gen_set_label(lab_done); gen_set_label(lab_done);
tcg_gen_movi_tl(lladdr, -1); tcg_gen_movi_tl(lladdr, -1);
tcg_gen_st_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr)); tcg_gen_st_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr));
} }
static void gen_adjust_sp(DisasContext *ctx, int u) static void gen_adjust_sp(DisasContext *ctx, int u)
@ -1335,14 +1335,14 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
case NM_DVP: case NM_DVP:
if (ctx->vp) { if (ctx->vp) {
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
gen_helper_dvp(t0, cpu_env); gen_helper_dvp(t0, tcg_env);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
} }
break; break;
case NM_EVP: case NM_EVP:
if (ctx->vp) { if (ctx->vp) {
check_cp0_enabled(ctx); check_cp0_enabled(ctx);
gen_helper_evp(t0, cpu_env); gen_helper_evp(t0, tcg_env);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
} }
break; break;
@ -1428,7 +1428,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
} else if (rs == 0) { } else if (rs == 0) {
/* DVPE */ /* DVPE */
check_cp0_mt(ctx); check_cp0_mt(ctx);
gen_helper_dvpe(t0, cpu_env); gen_helper_dvpe(t0, tcg_env);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
} else { } else {
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
@ -1443,7 +1443,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
} else if (rs == 0) { } else if (rs == 0) {
/* EVPE */ /* EVPE */
check_cp0_mt(ctx); check_cp0_mt(ctx);
gen_helper_evpe(t0, cpu_env); gen_helper_evpe(t0, tcg_env);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
} else { } else {
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
@ -1485,7 +1485,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rs); gen_load_gpr(t0, rs);
gen_helper_yield(t0, cpu_env, t0); gen_helper_yield(t0, tcg_env, t0);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
} }
break; break;
@ -1517,19 +1517,19 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (opc) { switch (opc) {
case NM_MAQ_S_W_PHR: case NM_MAQ_S_W_PHR:
check_dsp(ctx); check_dsp(ctx);
gen_helper_maq_s_w_phr(t0, v1_t, v0_t, cpu_env); gen_helper_maq_s_w_phr(t0, v1_t, v0_t, tcg_env);
break; break;
case NM_MAQ_S_W_PHL: case NM_MAQ_S_W_PHL:
check_dsp(ctx); check_dsp(ctx);
gen_helper_maq_s_w_phl(t0, v1_t, v0_t, cpu_env); gen_helper_maq_s_w_phl(t0, v1_t, v0_t, tcg_env);
break; break;
case NM_MAQ_SA_W_PHR: case NM_MAQ_SA_W_PHR:
check_dsp(ctx); check_dsp(ctx);
gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, cpu_env); gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, tcg_env);
break; break;
case NM_MAQ_SA_W_PHL: case NM_MAQ_SA_W_PHL:
check_dsp(ctx); check_dsp(ctx);
gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env); gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, tcg_env);
break; break;
default: default:
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
@ -1571,11 +1571,11 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 12, 2)) { switch (extract32(ctx->opcode, 12, 2)) {
case NM_MTHLIP: case NM_MTHLIP:
tcg_gen_movi_tl(t0, v2 >> 3); tcg_gen_movi_tl(t0, v2 >> 3);
gen_helper_mthlip(t0, v0_t, cpu_env); gen_helper_mthlip(t0, v0_t, tcg_env);
break; break;
case NM_SHILOV: case NM_SHILOV:
tcg_gen_movi_tl(t0, v2 >> 3); tcg_gen_movi_tl(t0, v2 >> 3);
gen_helper_shilo(t0, v0_t, cpu_env); gen_helper_shilo(t0, v0_t, tcg_env);
break; break;
default: default:
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
@ -1588,24 +1588,24 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 12, 2)) { switch (extract32(ctx->opcode, 12, 2)) {
case NM_RDDSP: case NM_RDDSP:
tcg_gen_movi_tl(t0, imm); tcg_gen_movi_tl(t0, imm);
gen_helper_rddsp(t0, t0, cpu_env); gen_helper_rddsp(t0, t0, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
case NM_WRDSP: case NM_WRDSP:
gen_load_gpr(t0, ret); gen_load_gpr(t0, ret);
tcg_gen_movi_tl(t1, imm); tcg_gen_movi_tl(t1, imm);
gen_helper_wrdsp(t0, t1, cpu_env); gen_helper_wrdsp(t0, t1, tcg_env);
break; break;
case NM_EXTP: case NM_EXTP:
tcg_gen_movi_tl(t0, v2 >> 3); tcg_gen_movi_tl(t0, v2 >> 3);
tcg_gen_movi_tl(t1, v1); tcg_gen_movi_tl(t1, v1);
gen_helper_extp(t0, t0, t1, cpu_env); gen_helper_extp(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
case NM_EXTPDP: case NM_EXTPDP:
tcg_gen_movi_tl(t0, v2 >> 3); tcg_gen_movi_tl(t0, v2 >> 3);
tcg_gen_movi_tl(t1, v1); tcg_gen_movi_tl(t1, v1);
gen_helper_extpdp(t0, t0, t1, cpu_env); gen_helper_extpdp(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
} }
@ -1615,7 +1615,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_movi_tl(t0, v2 >> 2); tcg_gen_movi_tl(t0, v2 >> 2);
switch (extract32(ctx->opcode, 12, 1)) { switch (extract32(ctx->opcode, 12, 1)) {
case NM_SHLL_QB: case NM_SHLL_QB:
gen_helper_shll_qb(t0, t0, v0_t, cpu_env); gen_helper_shll_qb(t0, t0, v0_t, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
case NM_SHRL_QB: case NM_SHRL_QB:
@ -1634,19 +1634,19 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_movi_tl(t1, v1); tcg_gen_movi_tl(t1, v1);
switch (extract32(ctx->opcode, 12, 2)) { switch (extract32(ctx->opcode, 12, 2)) {
case NM_EXTR_W: case NM_EXTR_W:
gen_helper_extr_w(t0, t0, t1, cpu_env); gen_helper_extr_w(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
case NM_EXTR_R_W: case NM_EXTR_R_W:
gen_helper_extr_r_w(t0, t0, t1, cpu_env); gen_helper_extr_r_w(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
case NM_EXTR_RS_W: case NM_EXTR_RS_W:
gen_helper_extr_rs_w(t0, t0, t1, cpu_env); gen_helper_extr_rs_w(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
case NM_EXTR_S_H: case NM_EXTR_S_H:
gen_helper_extr_s_h(t0, t0, t1, cpu_env); gen_helper_extr_s_h(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
} }
@ -1671,19 +1671,19 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 9, 3)) { switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPA_W_PH: case NM_DPA_W_PH:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_dpa_w_ph(t0, v1, v0, cpu_env); gen_helper_dpa_w_ph(t0, v1, v0, tcg_env);
break; break;
case NM_DPAQ_S_W_PH: case NM_DPAQ_S_W_PH:
check_dsp(ctx); check_dsp(ctx);
gen_helper_dpaq_s_w_ph(t0, v1, v0, cpu_env); gen_helper_dpaq_s_w_ph(t0, v1, v0, tcg_env);
break; break;
case NM_DPS_W_PH: case NM_DPS_W_PH:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_dps_w_ph(t0, v1, v0, cpu_env); gen_helper_dps_w_ph(t0, v1, v0, tcg_env);
break; break;
case NM_DPSQ_S_W_PH: case NM_DPSQ_S_W_PH:
check_dsp(ctx); check_dsp(ctx);
gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env); gen_helper_dpsq_s_w_ph(t0, v1, v0, tcg_env);
break; break;
default: default:
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
@ -1694,19 +1694,19 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 9, 3)) { switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAX_W_PH: case NM_DPAX_W_PH:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_dpax_w_ph(t0, v0, v1, cpu_env); gen_helper_dpax_w_ph(t0, v0, v1, tcg_env);
break; break;
case NM_DPAQ_SA_L_W: case NM_DPAQ_SA_L_W:
check_dsp(ctx); check_dsp(ctx);
gen_helper_dpaq_sa_l_w(t0, v0, v1, cpu_env); gen_helper_dpaq_sa_l_w(t0, v0, v1, tcg_env);
break; break;
case NM_DPSX_W_PH: case NM_DPSX_W_PH:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_dpsx_w_ph(t0, v0, v1, cpu_env); gen_helper_dpsx_w_ph(t0, v0, v1, tcg_env);
break; break;
case NM_DPSQ_SA_L_W: case NM_DPSQ_SA_L_W:
check_dsp(ctx); check_dsp(ctx);
gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env); gen_helper_dpsq_sa_l_w(t0, v0, v1, tcg_env);
break; break;
default: default:
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
@ -1717,23 +1717,23 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 9, 3)) { switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAU_H_QBL: case NM_DPAU_H_QBL:
check_dsp(ctx); check_dsp(ctx);
gen_helper_dpau_h_qbl(t0, v0, v1, cpu_env); gen_helper_dpau_h_qbl(t0, v0, v1, tcg_env);
break; break;
case NM_DPAQX_S_W_PH: case NM_DPAQX_S_W_PH:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_dpaqx_s_w_ph(t0, v0, v1, cpu_env); gen_helper_dpaqx_s_w_ph(t0, v0, v1, tcg_env);
break; break;
case NM_DPSU_H_QBL: case NM_DPSU_H_QBL:
check_dsp(ctx); check_dsp(ctx);
gen_helper_dpsu_h_qbl(t0, v0, v1, cpu_env); gen_helper_dpsu_h_qbl(t0, v0, v1, tcg_env);
break; break;
case NM_DPSQX_S_W_PH: case NM_DPSQX_S_W_PH:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_dpsqx_s_w_ph(t0, v0, v1, cpu_env); gen_helper_dpsqx_s_w_ph(t0, v0, v1, tcg_env);
break; break;
case NM_MULSA_W_PH: case NM_MULSA_W_PH:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env); gen_helper_mulsa_w_ph(t0, v0, v1, tcg_env);
break; break;
default: default:
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
@ -1744,23 +1744,23 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 9, 3)) { switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAU_H_QBR: case NM_DPAU_H_QBR:
check_dsp(ctx); check_dsp(ctx);
gen_helper_dpau_h_qbr(t0, v1, v0, cpu_env); gen_helper_dpau_h_qbr(t0, v1, v0, tcg_env);
break; break;
case NM_DPAQX_SA_W_PH: case NM_DPAQX_SA_W_PH:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_dpaqx_sa_w_ph(t0, v1, v0, cpu_env); gen_helper_dpaqx_sa_w_ph(t0, v1, v0, tcg_env);
break; break;
case NM_DPSU_H_QBR: case NM_DPSU_H_QBR:
check_dsp(ctx); check_dsp(ctx);
gen_helper_dpsu_h_qbr(t0, v1, v0, cpu_env); gen_helper_dpsu_h_qbr(t0, v1, v0, tcg_env);
break; break;
case NM_DPSQX_SA_W_PH: case NM_DPSQX_SA_W_PH:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_dpsqx_sa_w_ph(t0, v1, v0, cpu_env); gen_helper_dpsqx_sa_w_ph(t0, v1, v0, tcg_env);
break; break;
case NM_MULSAQ_S_W_PH: case NM_MULSAQ_S_W_PH:
check_dsp(ctx); check_dsp(ctx);
gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env); gen_helper_mulsaq_s_w_ph(t0, v1, v0, tcg_env);
break; break;
default: default:
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
@ -1849,7 +1849,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
check_dsp(ctx); check_dsp(ctx);
gen_load_gpr(v1_t, rs); gen_load_gpr(v1_t, rs);
tcg_gen_movi_tl(t0, rd >> 3); tcg_gen_movi_tl(t0, rd >> 3);
gen_helper_extr_w(t0, t0, v1_t, cpu_env); gen_helper_extr_w(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
} }
@ -1904,7 +1904,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTRV_R_W: case NM_EXTRV_R_W:
check_dsp(ctx); check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3); tcg_gen_movi_tl(t0, rd >> 3);
gen_helper_extr_r_w(t0, t0, v1_t, cpu_env); gen_helper_extr_r_w(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
default: default:
@ -1924,7 +1924,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTPV: case NM_EXTPV:
check_dsp(ctx); check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3); tcg_gen_movi_tl(t0, rd >> 3);
gen_helper_extp(t0, t0, v1_t, cpu_env); gen_helper_extp(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
case NM_MSUB: case NM_MSUB:
@ -1948,7 +1948,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTRV_RS_W: case NM_EXTRV_RS_W:
check_dsp(ctx); check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3); tcg_gen_movi_tl(t0, rd >> 3);
gen_helper_extr_rs_w(t0, t0, v1_t, cpu_env); gen_helper_extr_rs_w(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
} }
@ -1965,7 +1965,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTPDPV: case NM_EXTPDPV:
check_dsp(ctx); check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3); tcg_gen_movi_tl(t0, rd >> 3);
gen_helper_extpdp(t0, t0, v1_t, cpu_env); gen_helper_extpdp(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
case NM_MSUBU: case NM_MSUBU:
@ -1991,7 +1991,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTRV_S_H: case NM_EXTRV_S_H:
check_dsp(ctx); check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3); tcg_gen_movi_tl(t0, rd >> 3);
gen_helper_extr_s_h(t0, t0, v1_t, cpu_env); gen_helper_extr_s_h(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret); gen_store_gpr(t0, ret);
break; break;
} }
@ -2014,17 +2014,17 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (opc) { switch (opc) {
case NM_ABSQ_S_QB: case NM_ABSQ_S_QB:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_absq_s_qb(v0_t, v0_t, cpu_env); gen_helper_absq_s_qb(v0_t, v0_t, tcg_env);
gen_store_gpr(v0_t, ret); gen_store_gpr(v0_t, ret);
break; break;
case NM_ABSQ_S_PH: case NM_ABSQ_S_PH:
check_dsp(ctx); check_dsp(ctx);
gen_helper_absq_s_ph(v0_t, v0_t, cpu_env); gen_helper_absq_s_ph(v0_t, v0_t, tcg_env);
gen_store_gpr(v0_t, ret); gen_store_gpr(v0_t, ret);
break; break;
case NM_ABSQ_S_W: case NM_ABSQ_S_W:
check_dsp(ctx); check_dsp(ctx);
gen_helper_absq_s_w(v0_t, v0_t, cpu_env); gen_helper_absq_s_w(v0_t, v0_t, tcg_env);
gen_store_gpr(v0_t, ret); gen_store_gpr(v0_t, ret);
break; break;
case NM_PRECEQ_W_PHL: case NM_PRECEQ_W_PHL:
@ -2109,7 +2109,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
TCGv tv0 = tcg_temp_new(); TCGv tv0 = tcg_temp_new();
gen_load_gpr(tv0, rt); gen_load_gpr(tv0, rt);
gen_helper_insv(v0_t, cpu_env, v0_t, tv0); gen_helper_insv(v0_t, tcg_env, v0_t, tv0);
gen_store_gpr(v0_t, ret); gen_store_gpr(v0_t, ret);
} }
break; break;
@ -2243,7 +2243,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_di(t0, cpu_env); gen_helper_di(t0, tcg_env);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */ /* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
@ -2255,7 +2255,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
gen_helper_ei(t0, cpu_env); gen_helper_ei(t0, tcg_env);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */ /* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
@ -3036,27 +3036,27 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (opc) { switch (opc) {
case NM_CMP_EQ_PH: case NM_CMP_EQ_PH:
check_dsp(ctx); check_dsp(ctx);
gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env); gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env);
break; break;
case NM_CMP_LT_PH: case NM_CMP_LT_PH:
check_dsp(ctx); check_dsp(ctx);
gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env); gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env);
break; break;
case NM_CMP_LE_PH: case NM_CMP_LE_PH:
check_dsp(ctx); check_dsp(ctx);
gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env); gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env);
break; break;
case NM_CMPU_EQ_QB: case NM_CMPU_EQ_QB:
check_dsp(ctx); check_dsp(ctx);
gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env); gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env);
break; break;
case NM_CMPU_LT_QB: case NM_CMPU_LT_QB:
check_dsp(ctx); check_dsp(ctx);
gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env); gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env);
break; break;
case NM_CMPU_LE_QB: case NM_CMPU_LE_QB:
check_dsp(ctx); check_dsp(ctx);
gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env); gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env);
break; break;
case NM_CMPGU_EQ_QB: case NM_CMPGU_EQ_QB:
check_dsp(ctx); check_dsp(ctx);
@ -3098,32 +3098,32 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
break; break;
case NM_PICK_QB: case NM_PICK_QB:
check_dsp(ctx); check_dsp(ctx);
gen_helper_pick_qb(v1_t, v1_t, v2_t, cpu_env); gen_helper_pick_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_PICK_PH: case NM_PICK_PH:
check_dsp(ctx); check_dsp(ctx);
gen_helper_pick_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_pick_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_ADDQ_S_W: case NM_ADDQ_S_W:
check_dsp(ctx); check_dsp(ctx);
gen_helper_addq_s_w(v1_t, v1_t, v2_t, cpu_env); gen_helper_addq_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_SUBQ_S_W: case NM_SUBQ_S_W:
check_dsp(ctx); check_dsp(ctx);
gen_helper_subq_s_w(v1_t, v1_t, v2_t, cpu_env); gen_helper_subq_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_ADDSC: case NM_ADDSC:
check_dsp(ctx); check_dsp(ctx);
gen_helper_addsc(v1_t, v1_t, v2_t, cpu_env); gen_helper_addsc(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_ADDWC: case NM_ADDWC:
check_dsp(ctx); check_dsp(ctx);
gen_helper_addwc(v1_t, v1_t, v2_t, cpu_env); gen_helper_addwc(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_ADDQ_S_PH: case NM_ADDQ_S_PH:
@ -3131,12 +3131,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) { switch (extract32(ctx->opcode, 10, 1)) {
case 0: case 0:
/* ADDQ_PH */ /* ADDQ_PH */
gen_helper_addq_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_addq_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case 1: case 1:
/* ADDQ_S_PH */ /* ADDQ_S_PH */
gen_helper_addq_s_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_addq_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
} }
@ -3176,12 +3176,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) { switch (extract32(ctx->opcode, 10, 1)) {
case 0: case 0:
/* ADDU_QB */ /* ADDU_QB */
gen_helper_addu_qb(v1_t, v1_t, v2_t, cpu_env); gen_helper_addu_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case 1: case 1:
/* ADDU_S_QB */ /* ADDU_S_QB */
gen_helper_addu_s_qb(v1_t, v1_t, v2_t, cpu_env); gen_helper_addu_s_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
} }
@ -3191,12 +3191,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) { switch (extract32(ctx->opcode, 10, 1)) {
case 0: case 0:
/* ADDU_PH */ /* ADDU_PH */
gen_helper_addu_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_addu_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case 1: case 1:
/* ADDU_S_PH */ /* ADDU_S_PH */
gen_helper_addu_s_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_addu_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
} }
@ -3251,12 +3251,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) { switch (extract32(ctx->opcode, 10, 1)) {
case 0: case 0:
/* SUBQ_PH */ /* SUBQ_PH */
gen_helper_subq_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_subq_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case 1: case 1:
/* SUBQ_S_PH */ /* SUBQ_S_PH */
gen_helper_subq_s_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_subq_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
} }
@ -3296,12 +3296,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) { switch (extract32(ctx->opcode, 10, 1)) {
case 0: case 0:
/* SUBU_QB */ /* SUBU_QB */
gen_helper_subu_qb(v1_t, v1_t, v2_t, cpu_env); gen_helper_subu_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case 1: case 1:
/* SUBU_S_QB */ /* SUBU_S_QB */
gen_helper_subu_s_qb(v1_t, v1_t, v2_t, cpu_env); gen_helper_subu_s_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
} }
@ -3311,12 +3311,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) { switch (extract32(ctx->opcode, 10, 1)) {
case 0: case 0:
/* SUBU_PH */ /* SUBU_PH */
gen_helper_subu_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_subu_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case 1: case 1:
/* SUBU_S_PH */ /* SUBU_S_PH */
gen_helper_subu_s_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_subu_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
} }
@ -3341,12 +3341,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) { switch (extract32(ctx->opcode, 10, 1)) {
case 0: case 0:
/* SHLLV_PH */ /* SHLLV_PH */
gen_helper_shll_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_shll_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case 1: case 1:
/* SHLLV_S_PH */ /* SHLLV_S_PH */
gen_helper_shll_s_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_shll_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
} }
@ -3376,32 +3376,32 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
break; break;
case NM_MULEU_S_PH_QBL: case NM_MULEU_S_PH_QBL:
check_dsp(ctx); check_dsp(ctx);
gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, cpu_env); gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_MULEU_S_PH_QBR: case NM_MULEU_S_PH_QBR:
check_dsp(ctx); check_dsp(ctx);
gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, cpu_env); gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_MULQ_RS_PH: case NM_MULQ_RS_PH:
check_dsp(ctx); check_dsp(ctx);
gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_MULQ_S_PH: case NM_MULQ_S_PH:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_MULQ_RS_W: case NM_MULQ_RS_W:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, cpu_env); gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_MULQ_S_W: case NM_MULQ_S_W:
check_dsp_r2(ctx); check_dsp_r2(ctx);
gen_helper_mulq_s_w(v1_t, v1_t, v2_t, cpu_env); gen_helper_mulq_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_APPEND: case NM_APPEND:
@ -3434,12 +3434,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
break; break;
case NM_SHLLV_QB: case NM_SHLLV_QB:
check_dsp(ctx); check_dsp(ctx);
gen_helper_shll_qb(v1_t, v1_t, v2_t, cpu_env); gen_helper_shll_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_SHLLV_S_W: case NM_SHLLV_S_W:
check_dsp(ctx); check_dsp(ctx);
gen_helper_shll_s_w(v1_t, v1_t, v2_t, cpu_env); gen_helper_shll_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_SHILO: case NM_SHILO:
@ -3451,17 +3451,17 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
tcg_gen_movi_tl(tv0, rd >> 3); tcg_gen_movi_tl(tv0, rd >> 3);
tcg_gen_movi_tl(tv1, imm); tcg_gen_movi_tl(tv1, imm);
gen_helper_shilo(tv0, tv1, cpu_env); gen_helper_shilo(tv0, tv1, tcg_env);
} }
break; break;
case NM_MULEQ_S_W_PHL: case NM_MULEQ_S_W_PHL:
check_dsp(ctx); check_dsp(ctx);
gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, cpu_env); gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_MULEQ_S_W_PHR: case NM_MULEQ_S_W_PHR:
check_dsp(ctx); check_dsp(ctx);
gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, cpu_env); gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_MUL_S_PH: case NM_MUL_S_PH:
@ -3469,12 +3469,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) { switch (extract32(ctx->opcode, 10, 1)) {
case 0: case 0:
/* MUL_PH */ /* MUL_PH */
gen_helper_mul_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_mul_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case 1: case 1:
/* MUL_S_PH */ /* MUL_S_PH */
gen_helper_mul_s_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_mul_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
} }
@ -3496,12 +3496,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
break; break;
case NM_PRECRQ_RS_PH_W: case NM_PRECRQ_RS_PH_W:
check_dsp(ctx); check_dsp(ctx);
gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, cpu_env); gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_PRECRQU_S_QB_PH: case NM_PRECRQU_S_QB_PH:
check_dsp(ctx); check_dsp(ctx);
gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, cpu_env); gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret); gen_store_gpr(v1_t, ret);
break; break;
case NM_SHRA_R_W: case NM_SHRA_R_W:
@ -3532,12 +3532,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 2)) { switch (extract32(ctx->opcode, 10, 2)) {
case 0: case 0:
/* SHLL_PH */ /* SHLL_PH */
gen_helper_shll_ph(v1_t, t0, v1_t, cpu_env); gen_helper_shll_ph(v1_t, t0, v1_t, tcg_env);
gen_store_gpr(v1_t, rt); gen_store_gpr(v1_t, rt);
break; break;
case 2: case 2:
/* SHLL_S_PH */ /* SHLL_S_PH */
gen_helper_shll_s_ph(v1_t, t0, v1_t, cpu_env); gen_helper_shll_s_ph(v1_t, t0, v1_t, tcg_env);
gen_store_gpr(v1_t, rt); gen_store_gpr(v1_t, rt);
break; break;
default: default:
@ -3548,7 +3548,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
case NM_SHLL_S_W: case NM_SHLL_S_W:
check_dsp(ctx); check_dsp(ctx);
tcg_gen_movi_tl(t0, rd); tcg_gen_movi_tl(t0, rd);
gen_helper_shll_s_w(v1_t, t0, v1_t, cpu_env); gen_helper_shll_s_w(v1_t, t0, v1_t, tcg_env);
gen_store_gpr(v1_t, rt); gen_store_gpr(v1_t, rt);
break; break;
case NM_REPL_PH: case NM_REPL_PH:
@ -4503,7 +4503,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
/* make sure instructions are on a halfword boundary */ /* make sure instructions are on a halfword boundary */
if (ctx->base.pc_next & 0x1) { if (ctx->base.pc_next & 0x1) {
TCGv tmp = tcg_constant_tl(ctx->base.pc_next); TCGv tmp = tcg_constant_tl(ctx->base.pc_next);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); tcg_gen_st_tl(tmp, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr));
generate_exception_end(ctx, EXCP_AdEL); generate_exception_end(ctx, EXCP_AdEL);
return 2; return 2;
} }

1284
target/mips/tcg/translate.c
View File

File diff suppressed because it is too large Load Diff

6
target/mips/tcg/translate.h
View File

@ -123,15 +123,15 @@ enum {
}; };
#define gen_helper_0e1i(name, arg1, arg2) do { \ #define gen_helper_0e1i(name, arg1, arg2) do { \
gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \ gen_helper_##name(tcg_env, arg1, tcg_constant_i32(arg2)); \
} while (0) } while (0)
#define gen_helper_1e0i(name, ret, arg1) do { \ #define gen_helper_1e0i(name, ret, arg1) do { \
gen_helper_##name(ret, cpu_env, tcg_constant_i32(arg1)); \ gen_helper_##name(ret, tcg_env, tcg_constant_i32(arg1)); \
} while (0) } while (0)
#define gen_helper_0e2i(name, arg1, arg2, arg3) do { \ #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
gen_helper_##name(cpu_env, arg1, arg2, tcg_constant_i32(arg3));\ gen_helper_##name(tcg_env, arg1, arg2, tcg_constant_i32(arg3));\
} while (0) } while (0)
void generate_exception(DisasContext *ctx, int excp); void generate_exception(DisasContext *ctx, int excp);

2
target/mips/tcg/vr54xx_translate.c
View File

@ -43,7 +43,7 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
gen_load_gpr(t0, a->rs); gen_load_gpr(t0, a->rs);
gen_load_gpr(t1, a->rt); gen_load_gpr(t1, a->rt);
gen_helper_mult_acc(t0, cpu_env, t0, t1); gen_helper_mult_acc(t0, tcg_env, t0, t1);
gen_store_gpr(t0, a->rd); gen_store_gpr(t0, a->rd);
return true; return true;

48
target/nios2/translate.c
View File

@ -209,7 +209,7 @@ static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index)
{ {
/* Note that PC is advanced for all hardware exceptions. */ /* Note that PC is advanced for all hardware exceptions. */
tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); gen_helper_raise_exception(tcg_env, tcg_constant_i32(index));
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
} }
@ -244,7 +244,7 @@ static void gen_jumpr(DisasContext *dc, int regno, bool is_call)
tcg_gen_lookup_and_goto_ptr(); tcg_gen_lookup_and_goto_ptr();
gen_set_label(l); gen_set_label(l);
tcg_gen_st_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[CR_BADADDR])); tcg_gen_st_tl(dest, tcg_env, offsetof(CPUNios2State, ctrl[CR_BADADDR]));
t_gen_helper_raise_exception(dc, EXCP_UNALIGND); t_gen_helper_raise_exception(dc, EXCP_UNALIGND);
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
@ -414,7 +414,7 @@ static void rdprs(DisasContext *dc, uint32_t code, uint32_t flags)
#else #else
I_TYPE(instr, code); I_TYPE(instr, code);
TCGv dest = dest_gpr(dc, instr.b); TCGv dest = dest_gpr(dc, instr.b);
gen_helper_rdprs(dest, cpu_env, tcg_constant_i32(instr.a)); gen_helper_rdprs(dest, tcg_env, tcg_constant_i32(instr.a));
tcg_gen_addi_tl(dest, dest, instr.imm16.s); tcg_gen_addi_tl(dest, dest, instr.imm16.s);
#endif #endif
} }
@ -508,10 +508,10 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
#else #else
if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) { if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) {
TCGv tmp = tcg_temp_new(); TCGv tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); gen_helper_eret(tcg_env, tmp, load_gpr(dc, R_EA));
} else { } else {
gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA)); gen_helper_eret(tcg_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA));
} }
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
#endif #endif
@ -537,8 +537,8 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags)
g_assert_not_reached(); g_assert_not_reached();
#else #else
TCGv tmp = tcg_temp_new(); TCGv tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS]));
gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA)); gen_helper_eret(tcg_env, tmp, load_gpr(dc, R_BA));
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
#endif #endif
@ -602,12 +602,12 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
*/ */
t1 = tcg_temp_new(); t1 = tcg_temp_new();
t2 = tcg_temp_new(); t2 = tcg_temp_new();
tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING])); tcg_gen_ld_tl(t1, tcg_env, offsetof(CPUNios2State, ctrl[CR_IPENDING]));
tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE])); tcg_gen_ld_tl(t2, tcg_env, offsetof(CPUNios2State, ctrl[CR_IENABLE]));
tcg_gen_and_tl(dest, t1, t2); tcg_gen_and_tl(dest, t1, t2);
break; break;
default: default:
tcg_gen_ld_tl(dest, cpu_env, tcg_gen_ld_tl(dest, tcg_env,
offsetof(CPUNios2State, ctrl[instr.imm5])); offsetof(CPUNios2State, ctrl[instr.imm5]));
break; break;
} }
@ -637,13 +637,13 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
switch (instr.imm5) { switch (instr.imm5) {
case CR_PTEADDR: case CR_PTEADDR:
gen_helper_mmu_write_pteaddr(cpu_env, v); gen_helper_mmu_write_pteaddr(tcg_env, v);
break; break;
case CR_TLBACC: case CR_TLBACC:
gen_helper_mmu_write_tlbacc(cpu_env, v); gen_helper_mmu_write_tlbacc(tcg_env, v);
break; break;
case CR_TLBMISC: case CR_TLBMISC:
gen_helper_mmu_write_tlbmisc(cpu_env, v); gen_helper_mmu_write_tlbmisc(tcg_env, v);
break; break;
case CR_STATUS: case CR_STATUS:
case CR_IENABLE: case CR_IENABLE:
@ -653,7 +653,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
default: default:
if (wr == -1) { if (wr == -1) {
/* The register is entirely writable. */ /* The register is entirely writable. */
tcg_gen_st_tl(v, cpu_env, ofs); tcg_gen_st_tl(v, tcg_env, ofs);
} else { } else {
/* /*
* The register is partially read-only or reserved: * The register is partially read-only or reserved:
@ -665,12 +665,12 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
if (ro != 0) { if (ro != 0) {
TCGv o = tcg_temp_new(); TCGv o = tcg_temp_new();
tcg_gen_ld_tl(o, cpu_env, ofs); tcg_gen_ld_tl(o, tcg_env, ofs);
tcg_gen_andi_tl(o, o, ro); tcg_gen_andi_tl(o, o, ro);
tcg_gen_or_tl(n, n, o); tcg_gen_or_tl(n, n, o);
} }
tcg_gen_st_tl(n, cpu_env, ofs); tcg_gen_st_tl(n, tcg_env, ofs);
} }
break; break;
} }
@ -692,7 +692,7 @@ static void wrprs(DisasContext *dc, uint32_t code, uint32_t flags)
g_assert_not_reached(); g_assert_not_reached();
#else #else
R_TYPE(instr, code); R_TYPE(instr, code);
gen_helper_wrprs(cpu_env, tcg_constant_i32(instr.c), gen_helper_wrprs(tcg_env, tcg_constant_i32(instr.c),
load_gpr(dc, instr.a)); load_gpr(dc, instr.a));
/* /*
* The expected write to PRS[r0] is 0, from CRS[r0]. * The expected write to PRS[r0] is 0, from CRS[r0].
@ -789,14 +789,14 @@ gen_rr_shift(ror, rotr)
static void divs(DisasContext *dc, uint32_t code, uint32_t flags) static void divs(DisasContext *dc, uint32_t code, uint32_t flags)
{ {
R_TYPE(instr, (code)); R_TYPE(instr, (code));
gen_helper_divs(dest_gpr(dc, instr.c), cpu_env, gen_helper_divs(dest_gpr(dc, instr.c), tcg_env,
load_gpr(dc, instr.a), load_gpr(dc, instr.b)); load_gpr(dc, instr.a), load_gpr(dc, instr.b));
} }
static void divu(DisasContext *dc, uint32_t code, uint32_t flags) static void divu(DisasContext *dc, uint32_t code, uint32_t flags)
{ {
R_TYPE(instr, (code)); R_TYPE(instr, (code));
gen_helper_divu(dest_gpr(dc, instr.c), cpu_env, gen_helper_divu(dest_gpr(dc, instr.c), tcg_env,
load_gpr(dc, instr.a), load_gpr(dc, instr.b)); load_gpr(dc, instr.a), load_gpr(dc, instr.b));
} }
@ -809,7 +809,7 @@ static void trap(DisasContext *dc, uint32_t code, uint32_t flags)
* things easier for cpu_loop if we pop this into env->error_code. * things easier for cpu_loop if we pop this into env->error_code.
*/ */
R_TYPE(instr, code); R_TYPE(instr, code);
tcg_gen_st_i32(tcg_constant_i32(instr.imm5), cpu_env, tcg_gen_st_i32(tcg_constant_i32(instr.imm5), tcg_env,
offsetof(CPUNios2State, error_code)); offsetof(CPUNios2State, error_code));
#endif #endif
t_gen_helper_raise_exception(dc, EXCP_TRAP); t_gen_helper_raise_exception(dc, EXCP_TRAP);
@ -1084,7 +1084,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
void nios2_tcg_init(void) void nios2_tcg_init(void)
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
TCGv_ptr crs = tcg_global_mem_new_ptr(cpu_env, TCGv_ptr crs = tcg_global_mem_new_ptr(tcg_env,
offsetof(CPUNios2State, regs), "crs"); offsetof(CPUNios2State, regs), "crs");
for (int i = 0; i < NUM_GP_REGS; i++) { for (int i = 0; i < NUM_GP_REGS; i++) {
@ -1097,12 +1097,12 @@ void nios2_tcg_init(void)
#endif #endif
for (int i = 0; i < NUM_GP_REGS; i++) { for (int i = 0; i < NUM_GP_REGS; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof_regs0(i), cpu_R[i] = tcg_global_mem_new(tcg_env, offsetof_regs0(i),
gr_regnames[i]); gr_regnames[i]);
} }
#undef offsetof_regs0 #undef offsetof_regs0
cpu_pc = tcg_global_mem_new(cpu_env, cpu_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUNios2State, pc), "pc"); offsetof(CPUNios2State, pc), "pc");
} }

84
target/openrisc/translate.c
View File

@ -95,37 +95,37 @@ void openrisc_translate_init(void)
}; };
int i; int i;
cpu_sr = tcg_global_mem_new(cpu_env, cpu_sr = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, sr), "sr"); offsetof(CPUOpenRISCState, sr), "sr");
cpu_dflag = tcg_global_mem_new_i32(cpu_env, cpu_dflag = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUOpenRISCState, dflag), offsetof(CPUOpenRISCState, dflag),
"dflag"); "dflag");
cpu_pc = tcg_global_mem_new(cpu_env, cpu_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, pc), "pc"); offsetof(CPUOpenRISCState, pc), "pc");
cpu_ppc = tcg_global_mem_new(cpu_env, cpu_ppc = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, ppc), "ppc"); offsetof(CPUOpenRISCState, ppc), "ppc");
jmp_pc = tcg_global_mem_new(cpu_env, jmp_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc"); offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
cpu_sr_f = tcg_global_mem_new(cpu_env, cpu_sr_f = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, sr_f), "sr_f"); offsetof(CPUOpenRISCState, sr_f), "sr_f");
cpu_sr_cy = tcg_global_mem_new(cpu_env, cpu_sr_cy = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, sr_cy), "sr_cy"); offsetof(CPUOpenRISCState, sr_cy), "sr_cy");
cpu_sr_ov = tcg_global_mem_new(cpu_env, cpu_sr_ov = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, sr_ov), "sr_ov"); offsetof(CPUOpenRISCState, sr_ov), "sr_ov");
cpu_lock_addr = tcg_global_mem_new(cpu_env, cpu_lock_addr = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, lock_addr), offsetof(CPUOpenRISCState, lock_addr),
"lock_addr"); "lock_addr");
cpu_lock_value = tcg_global_mem_new(cpu_env, cpu_lock_value = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, lock_value), offsetof(CPUOpenRISCState, lock_value),
"lock_value"); "lock_value");
fpcsr = tcg_global_mem_new_i32(cpu_env, fpcsr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUOpenRISCState, fpcsr), offsetof(CPUOpenRISCState, fpcsr),
"fpcsr"); "fpcsr");
cpu_mac = tcg_global_mem_new_i64(cpu_env, cpu_mac = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUOpenRISCState, mac), offsetof(CPUOpenRISCState, mac),
"mac"); "mac");
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
cpu_regs[i] = tcg_global_mem_new(cpu_env, cpu_regs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, offsetof(CPUOpenRISCState,
shadow_gpr[0][i]), shadow_gpr[0][i]),
regnames[i]); regnames[i]);
@ -134,7 +134,7 @@ void openrisc_translate_init(void)
static void gen_exception(DisasContext *dc, unsigned int excp) static void gen_exception(DisasContext *dc, unsigned int excp)
{ {
gen_helper_exception(cpu_env, tcg_constant_i32(excp)); gen_helper_exception(tcg_env, tcg_constant_i32(excp));
} }
static void gen_illegal_exception(DisasContext *dc) static void gen_illegal_exception(DisasContext *dc)
@ -182,21 +182,21 @@ static void check_r0_write(DisasContext *dc, int reg)
static void gen_ove_cy(DisasContext *dc) static void gen_ove_cy(DisasContext *dc)
{ {
if (dc->tb_flags & SR_OVE) { if (dc->tb_flags & SR_OVE) {
gen_helper_ove_cy(cpu_env); gen_helper_ove_cy(tcg_env);
} }
} }
static void gen_ove_ov(DisasContext *dc) static void gen_ove_ov(DisasContext *dc)
{ {
if (dc->tb_flags & SR_OVE) { if (dc->tb_flags & SR_OVE) {
gen_helper_ove_ov(cpu_env); gen_helper_ove_ov(tcg_env);
} }
} }
static void gen_ove_cyov(DisasContext *dc) static void gen_ove_cyov(DisasContext *dc)
{ {
if (dc->tb_flags & SR_OVE) { if (dc->tb_flags & SR_OVE) {
gen_helper_ove_cyov(cpu_env); gen_helper_ove_cyov(tcg_env);
} }
} }
@ -835,7 +835,7 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a)
} }
tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); gen_helper_mfspr(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d), spr);
return true; return true;
} }
@ -860,7 +860,7 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a)
dc->base.is_jmp = DISAS_EXIT; dc->base.is_jmp = DISAS_EXIT;
tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); gen_helper_mtspr(tcg_env, spr, cpu_R(dc, a->b));
return true; return true;
} }
@ -1102,7 +1102,7 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a)
if (is_user(dc)) { if (is_user(dc)) {
gen_illegal_exception(dc); gen_illegal_exception(dc);
} else { } else {
gen_helper_rfe(cpu_env); gen_helper_rfe(tcg_env);
dc->base.is_jmp = DISAS_EXIT; dc->base.is_jmp = DISAS_EXIT;
} }
return true; return true;
@ -1115,8 +1115,8 @@ static bool do_fp2(DisasContext *dc, arg_da *a,
return false; return false;
} }
check_r0_write(dc, a->d); check_r0_write(dc, a->d);
fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a)); fn(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->a));
gen_helper_update_fpcsr(cpu_env); gen_helper_update_fpcsr(tcg_env);
return true; return true;
} }
@ -1127,8 +1127,8 @@ static bool do_fp3(DisasContext *dc, arg_dab *a,
return false; return false;
} }
check_r0_write(dc, a->d); check_r0_write(dc, a->d);
fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); fn(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b));
gen_helper_update_fpcsr(cpu_env); gen_helper_update_fpcsr(tcg_env);
return true; return true;
} }
@ -1140,14 +1140,14 @@ static bool do_fpcmp(DisasContext *dc, arg_ab *a,
return false; return false;
} }
if (swap) { if (swap) {
fn(cpu_sr_f, cpu_env, cpu_R(dc, a->b), cpu_R(dc, a->a)); fn(cpu_sr_f, tcg_env, cpu_R(dc, a->b), cpu_R(dc, a->a));
} else { } else {
fn(cpu_sr_f, cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); fn(cpu_sr_f, tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b));
} }
if (inv) { if (inv) {
tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
} }
gen_helper_update_fpcsr(cpu_env); gen_helper_update_fpcsr(tcg_env);
return true; return true;
} }
@ -1193,9 +1193,9 @@ static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a)
return false; return false;
} }
check_r0_write(dc, a->d); check_r0_write(dc, a->d);
gen_helper_float_madd_s(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), gen_helper_float_madd_s(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d),
cpu_R(dc, a->a), cpu_R(dc, a->b)); cpu_R(dc, a->a), cpu_R(dc, a->b));
gen_helper_update_fpcsr(cpu_env); gen_helper_update_fpcsr(tcg_env);
return true; return true;
} }
@ -1309,10 +1309,10 @@ static bool do_dp3(DisasContext *dc, arg_dab_pair *a,
t1 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64();
load_pair(dc, t0, a->a, a->ap); load_pair(dc, t0, a->a, a->ap);
load_pair(dc, t1, a->b, a->bp); load_pair(dc, t1, a->b, a->bp);
fn(t0, cpu_env, t0, t1); fn(t0, tcg_env, t0, t1);
save_pair(dc, t0, a->d, a->dp); save_pair(dc, t0, a->d, a->dp);
gen_helper_update_fpcsr(cpu_env); gen_helper_update_fpcsr(tcg_env);
return true; return true;
} }
@ -1330,10 +1330,10 @@ static bool do_dp2(DisasContext *dc, arg_da_pair *a,
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
load_pair(dc, t0, a->a, a->ap); load_pair(dc, t0, a->a, a->ap);
fn(t0, cpu_env, t0); fn(t0, tcg_env, t0);
save_pair(dc, t0, a->d, a->dp); save_pair(dc, t0, a->d, a->dp);
gen_helper_update_fpcsr(cpu_env); gen_helper_update_fpcsr(tcg_env);
return true; return true;
} }
@ -1354,15 +1354,15 @@ static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a,
load_pair(dc, t0, a->a, a->ap); load_pair(dc, t0, a->a, a->ap);
load_pair(dc, t1, a->b, a->bp); load_pair(dc, t1, a->b, a->bp);
if (swap) { if (swap) {
fn(cpu_sr_f, cpu_env, t1, t0); fn(cpu_sr_f, tcg_env, t1, t0);
} else { } else {
fn(cpu_sr_f, cpu_env, t0, t1); fn(cpu_sr_f, tcg_env, t0, t1);
} }
if (inv) { if (inv) {
tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
} }
gen_helper_update_fpcsr(cpu_env); gen_helper_update_fpcsr(tcg_env);
return true; return true;
} }
@ -1412,10 +1412,10 @@ static bool trans_lf_stod_d(DisasContext *dc, arg_lf_stod_d *a)
check_r0_write(dc, a->d); check_r0_write(dc, a->d);
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
gen_helper_stod(t0, cpu_env, cpu_R(dc, a->a)); gen_helper_stod(t0, tcg_env, cpu_R(dc, a->a));
save_pair(dc, t0, a->d, a->dp); save_pair(dc, t0, a->d, a->dp);
gen_helper_update_fpcsr(cpu_env); gen_helper_update_fpcsr(tcg_env);
return true; return true;
} }
@ -1431,9 +1431,9 @@ static bool trans_lf_dtos_d(DisasContext *dc, arg_lf_dtos_d *a)
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
load_pair(dc, t0, a->a, a->ap); load_pair(dc, t0, a->a, a->ap);
gen_helper_dtos(cpu_R(dc, a->d), cpu_env, t0); gen_helper_dtos(cpu_R(dc, a->d), tcg_env, t0);
gen_helper_update_fpcsr(cpu_env); gen_helper_update_fpcsr(tcg_env);
return true; return true;
} }
@ -1455,10 +1455,10 @@ static bool trans_lf_madd_d(DisasContext *dc, arg_dab_pair *a)
load_pair(dc, t0, a->d, a->dp); load_pair(dc, t0, a->d, a->dp);
load_pair(dc, t1, a->a, a->ap); load_pair(dc, t1, a->a, a->ap);
load_pair(dc, t2, a->b, a->bp); load_pair(dc, t2, a->b, a->bp);
gen_helper_float_madd_d(t0, cpu_env, t0, t1, t2); gen_helper_float_madd_d(t0, tcg_env, t0, t1, t2);
save_pair(dc, t0, a->d, a->dp); save_pair(dc, t0, a->d, a->dp);
gen_helper_update_fpcsr(cpu_env); gen_helper_update_fpcsr(tcg_env);
return true; return true;
} }

8
target/ppc/power8-pmu-regs.c.inc
View File

@ -106,7 +106,7 @@ static void write_MMCR0_common(DisasContext *ctx, TCGv val)
* translator_io_start() beforehand. * translator_io_start() beforehand.
*/ */
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_store_mmcr0(cpu_env, val); gen_helper_store_mmcr0(tcg_env, val);
/* /*
* End the translation block because MMCR0 writes can change * End the translation block because MMCR0 writes can change
@ -180,7 +180,7 @@ void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
TCGv_i32 t_sprn = tcg_constant_i32(sprn); TCGv_i32 t_sprn = tcg_constant_i32(sprn);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn); gen_helper_read_pmc(cpu_gpr[gprn], tcg_env, t_sprn);
} }
void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn) void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn)
@ -213,7 +213,7 @@ void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
TCGv_i32 t_sprn = tcg_constant_i32(sprn); TCGv_i32 t_sprn = tcg_constant_i32(sprn);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); gen_helper_store_pmc(tcg_env, t_sprn, cpu_gpr[gprn]);
} }
void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn) void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn)
@ -249,7 +249,7 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn) void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn)
{ {
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]); gen_helper_store_mmcr1(tcg_env, cpu_gpr[gprn]);
} }
#else #else
void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn) void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn)

362
target/ppc/translate.c
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File diff suppressed because it is too large Load Diff

2
target/ppc/translate/branch-impl.c.inc
View File

@ -18,7 +18,7 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_update_cfar(ctx, ctx->cia); gen_update_cfar(ctx, ctx->cia);
gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]); gen_helper_rfebb(tcg_env, cpu_gpr[arg->s]);
ctx->base.is_jmp = DISAS_CHAIN; ctx->base.is_jmp = DISAS_CHAIN;

22
target/ppc/translate/dfp-impl.c.inc
View File

@ -3,7 +3,7 @@
static inline TCGv_ptr gen_fprp_ptr(int reg) static inline TCGv_ptr gen_fprp_ptr(int reg)
{ {
TCGv_ptr r = tcg_temp_new_ptr(); TCGv_ptr r = tcg_temp_new_ptr();
tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0])); tcg_gen_addi_ptr(r, tcg_env, offsetof(CPUPPCState, vsr[reg].u64[0]));
return r; return r;
} }
@ -16,7 +16,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
rt = gen_fprp_ptr(a->rt); \ rt = gen_fprp_ptr(a->rt); \
ra = gen_fprp_ptr(a->ra); \ ra = gen_fprp_ptr(a->ra); \
rb = gen_fprp_ptr(a->rb); \ rb = gen_fprp_ptr(a->rb); \
gen_helper_##NAME(cpu_env, rt, ra, rb); \ gen_helper_##NAME(tcg_env, rt, ra, rb); \
if (unlikely(a->rc)) { \ if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \ gen_set_cr1_from_fpscr(ctx); \
} \ } \
@ -32,7 +32,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
ra = gen_fprp_ptr(a->ra); \ ra = gen_fprp_ptr(a->ra); \
rb = gen_fprp_ptr(a->rb); \ rb = gen_fprp_ptr(a->rb); \
gen_helper_##NAME(cpu_crf[a->bf], \ gen_helper_##NAME(cpu_crf[a->bf], \
cpu_env, ra, rb); \ tcg_env, ra, rb); \
return true; \ return true; \
} }
@ -44,7 +44,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
REQUIRE_FPU(ctx); \ REQUIRE_FPU(ctx); \
rb = gen_fprp_ptr(a->rb); \ rb = gen_fprp_ptr(a->rb); \
gen_helper_##NAME(cpu_crf[a->bf], \ gen_helper_##NAME(cpu_crf[a->bf], \
cpu_env, tcg_constant_i32(a->uim), rb);\ tcg_env, tcg_constant_i32(a->uim), rb);\
return true; \ return true; \
} }
@ -56,7 +56,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
REQUIRE_FPU(ctx); \ REQUIRE_FPU(ctx); \
ra = gen_fprp_ptr(a->fra); \ ra = gen_fprp_ptr(a->fra); \
gen_helper_##NAME(cpu_crf[a->bf], \ gen_helper_##NAME(cpu_crf[a->bf], \
cpu_env, ra, tcg_constant_i32(a->dm)); \ tcg_env, ra, tcg_constant_i32(a->dm)); \
return true; \ return true; \
} }
@ -68,7 +68,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
REQUIRE_FPU(ctx); \ REQUIRE_FPU(ctx); \
rt = gen_fprp_ptr(a->frt); \ rt = gen_fprp_ptr(a->frt); \
rb = gen_fprp_ptr(a->frb); \ rb = gen_fprp_ptr(a->frb); \
gen_helper_##NAME(cpu_env, rt, rb, \ gen_helper_##NAME(tcg_env, rt, rb, \
tcg_constant_i32(a->U32F1), \ tcg_constant_i32(a->U32F1), \
tcg_constant_i32(a->U32F2)); \ tcg_constant_i32(a->U32F2)); \
if (unlikely(a->rc)) { \ if (unlikely(a->rc)) { \
@ -86,7 +86,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
rt = gen_fprp_ptr(a->frt); \ rt = gen_fprp_ptr(a->frt); \
ra = gen_fprp_ptr(a->fra); \ ra = gen_fprp_ptr(a->fra); \
rb = gen_fprp_ptr(a->frb); \ rb = gen_fprp_ptr(a->frb); \
gen_helper_##NAME(cpu_env, rt, ra, rb, \ gen_helper_##NAME(tcg_env, rt, ra, rb, \
tcg_constant_i32(a->I32FLD)); \ tcg_constant_i32(a->I32FLD)); \
if (unlikely(a->rc)) { \ if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \ gen_set_cr1_from_fpscr(ctx); \
@ -102,7 +102,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
REQUIRE_FPU(ctx); \ REQUIRE_FPU(ctx); \
rt = gen_fprp_ptr(a->rt); \ rt = gen_fprp_ptr(a->rt); \
rb = gen_fprp_ptr(a->rb); \ rb = gen_fprp_ptr(a->rb); \
gen_helper_##NAME(cpu_env, rt, rb); \ gen_helper_##NAME(tcg_env, rt, rb); \
if (unlikely(a->rc)) { \ if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \ gen_set_cr1_from_fpscr(ctx); \
} \ } \
@ -117,7 +117,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
REQUIRE_FPU(ctx); \ REQUIRE_FPU(ctx); \
rt = gen_fprp_ptr(a->rt); \ rt = gen_fprp_ptr(a->rt); \
rx = gen_fprp_ptr(a->FPRFLD); \ rx = gen_fprp_ptr(a->FPRFLD); \
gen_helper_##NAME(cpu_env, rt, rx, \ gen_helper_##NAME(tcg_env, rt, rx, \
tcg_constant_i32(a->I32FLD)); \ tcg_constant_i32(a->I32FLD)); \
if (unlikely(a->rc)) { \ if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \ gen_set_cr1_from_fpscr(ctx); \
@ -188,7 +188,7 @@ static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
rt = gen_fprp_ptr(a->frtp); rt = gen_fprp_ptr(a->frtp);
rb = gen_avr_ptr(a->vrb); rb = gen_avr_ptr(a->vrb);
gen_helper_DCFFIXQQ(cpu_env, rt, rb); gen_helper_DCFFIXQQ(tcg_env, rt, rb);
return true; return true;
} }
@ -203,7 +203,7 @@ static bool trans_DCTFIXQQ(DisasContext *ctx, arg_DCTFIXQQ *a)
rt = gen_avr_ptr(a->vrt); rt = gen_avr_ptr(a->vrt);
rb = gen_fprp_ptr(a->frbp); rb = gen_fprp_ptr(a->frbp);
gen_helper_DCTFIXQQ(cpu_env, rt, rb); gen_helper_DCTFIXQQ(tcg_env, rt, rb);
return true; return true;
} }

2
target/ppc/translate/fixedpoint-impl.c.inc
View File

@ -517,7 +517,7 @@ static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
} }
ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt)); ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt));
helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]); helper(tcg_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);
return true; return true;
} }

50
target/ppc/translate/fp-impl.c.inc
View File

@ -6,13 +6,13 @@
static inline void gen_reset_fpstatus(void) static inline void gen_reset_fpstatus(void)
{ {
gen_helper_reset_fpstatus(cpu_env); gen_helper_reset_fpstatus(tcg_env);
} }
static inline void gen_compute_fprf_float64(TCGv_i64 arg) static inline void gen_compute_fprf_float64(TCGv_i64 arg)
{ {
gen_helper_compute_fprf_float64(cpu_env, arg); gen_helper_compute_fprf_float64(tcg_env, arg);
gen_helper_float_check_status(cpu_env); gen_helper_float_check_status(tcg_env);
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
@ -49,7 +49,7 @@ static void gen_f##name(DisasContext *ctx) \
get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rC(ctx->opcode)); \ get_fpr(t1, rC(ctx->opcode)); \
get_fpr(t2, rB(ctx->opcode)); \ get_fpr(t2, rB(ctx->opcode)); \
gen_helper_f##name(t3, cpu_env, t0, t1, t2); \ gen_helper_f##name(t3, tcg_env, t0, t1, t2); \
set_fpr(rD(ctx->opcode), t3); \ set_fpr(rD(ctx->opcode), t3); \
if (set_fprf) { \ if (set_fprf) { \
gen_compute_fprf_float64(t3); \ gen_compute_fprf_float64(t3); \
@ -79,7 +79,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \ gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rB(ctx->opcode)); \ get_fpr(t1, rB(ctx->opcode)); \
gen_helper_f##name(t2, cpu_env, t0, t1); \ gen_helper_f##name(t2, tcg_env, t0, t1); \
set_fpr(rD(ctx->opcode), t2); \ set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \ if (set_fprf) { \
gen_compute_fprf_float64(t2); \ gen_compute_fprf_float64(t2); \
@ -108,7 +108,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \ gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rC(ctx->opcode)); \ get_fpr(t1, rC(ctx->opcode)); \
gen_helper_f##name(t2, cpu_env, t0, t1); \ gen_helper_f##name(t2, tcg_env, t0, t1); \
set_fpr(rD(ctx->opcode), t2); \ set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \ if (set_fprf) { \
gen_compute_fprf_float64(t2); \ gen_compute_fprf_float64(t2); \
@ -134,12 +134,12 @@ static void gen_f##name(DisasContext *ctx) \
t1 = tcg_temp_new_i64(); \ t1 = tcg_temp_new_i64(); \
gen_reset_fpstatus(); \ gen_reset_fpstatus(); \
get_fpr(t0, rB(ctx->opcode)); \ get_fpr(t0, rB(ctx->opcode)); \
gen_helper_f##name(t1, cpu_env, t0); \ gen_helper_f##name(t1, tcg_env, t0); \
set_fpr(rD(ctx->opcode), t1); \ set_fpr(rD(ctx->opcode), t1); \
if (set_fprf) { \ if (set_fprf) { \
gen_helper_compute_fprf_float64(cpu_env, t1); \ gen_helper_compute_fprf_float64(tcg_env, t1); \
} \ } \
gen_helper_float_check_status(cpu_env); \ gen_helper_float_check_status(tcg_env); \
if (unlikely(Rc(ctx->opcode) != 0)) { \ if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \ gen_set_cr1_from_fpscr(ctx); \
} \ } \
@ -158,7 +158,7 @@ static void gen_f##name(DisasContext *ctx) \
t1 = tcg_temp_new_i64(); \ t1 = tcg_temp_new_i64(); \
gen_reset_fpstatus(); \ gen_reset_fpstatus(); \
get_fpr(t0, rB(ctx->opcode)); \ get_fpr(t0, rB(ctx->opcode)); \
gen_helper_f##name(t1, cpu_env, t0); \ gen_helper_f##name(t1, tcg_env, t0); \
set_fpr(rD(ctx->opcode), t1); \ set_fpr(rD(ctx->opcode), t1); \
if (set_fprf) { \ if (set_fprf) { \
gen_compute_fprf_float64(t1); \ gen_compute_fprf_float64(t1); \
@ -197,7 +197,7 @@ static void gen_frsqrtes(DisasContext *ctx)
t1 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64();
gen_reset_fpstatus(); gen_reset_fpstatus();
get_fpr(t0, rB(ctx->opcode)); get_fpr(t0, rB(ctx->opcode));
gen_helper_frsqrtes(t1, cpu_env, t0); gen_helper_frsqrtes(t1, tcg_env, t0);
set_fpr(rD(ctx->opcode), t1); set_fpr(rD(ctx->opcode), t1);
gen_compute_fprf_float64(t1); gen_compute_fprf_float64(t1);
if (unlikely(Rc(ctx->opcode) != 0)) { if (unlikely(Rc(ctx->opcode) != 0)) {
@ -245,7 +245,7 @@ static bool do_helper_fsqrt(DisasContext *ctx, arg_A_tb *a,
gen_reset_fpstatus(); gen_reset_fpstatus();
get_fpr(t0, a->frb); get_fpr(t0, a->frb);
helper(t1, cpu_env, t0); helper(t1, tcg_env, t0);
set_fpr(a->frt, t1); set_fpr(a->frt, t1);
gen_compute_fprf_float64(t1); gen_compute_fprf_float64(t1);
if (unlikely(a->rc != 0)) { if (unlikely(a->rc != 0)) {
@ -351,8 +351,8 @@ static void gen_fcmpo(DisasContext *ctx)
crf = tcg_constant_i32(crfD(ctx->opcode)); crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode)); get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode)); get_fpr(t1, rB(ctx->opcode));
gen_helper_fcmpo(cpu_env, t0, t1, crf); gen_helper_fcmpo(tcg_env, t0, t1, crf);
gen_helper_float_check_status(cpu_env); gen_helper_float_check_status(tcg_env);
} }
/* fcmpu */ /* fcmpu */
@ -371,8 +371,8 @@ static void gen_fcmpu(DisasContext *ctx)
crf = tcg_constant_i32(crfD(ctx->opcode)); crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode)); get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode)); get_fpr(t1, rB(ctx->opcode));
gen_helper_fcmpu(cpu_env, t0, t1, crf); gen_helper_fcmpu(tcg_env, t0, t1, crf);
gen_helper_float_check_status(cpu_env); gen_helper_float_check_status(tcg_env);
} }
/*** Floating-point move ***/ /*** Floating-point move ***/
@ -542,7 +542,7 @@ static void gen_mcrfs(DisasContext *ctx)
~((0xF << shift) & FP_EX_CLEAR_BITS)); ~((0xF << shift) & FP_EX_CLEAR_BITS));
/* FEX and VX need to be updated, so don't set fpscr directly */ /* FEX and VX need to be updated, so don't set fpscr directly */
tmask = tcg_constant_i32(1 << nibble); tmask = tcg_constant_i32(1 << nibble);
gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask); gen_helper_store_fpscr(tcg_env, tnew_fpscr, tmask);
} }
static TCGv_i64 place_from_fpscr(int rt, uint64_t mask) static TCGv_i64 place_from_fpscr(int rt, uint64_t mask)
@ -565,7 +565,7 @@ static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t clear_mask,
tcg_gen_andi_i64(fpscr_masked, fpscr, ~clear_mask); tcg_gen_andi_i64(fpscr_masked, fpscr, ~clear_mask);
tcg_gen_or_i64(fpscr_masked, fpscr_masked, set_mask); tcg_gen_or_i64(fpscr_masked, fpscr_masked, set_mask);
gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask); gen_helper_store_fpscr(tcg_env, fpscr_masked, st_mask);
} }
static bool trans_MFFS_ISA207(DisasContext *ctx, arg_X_t_rc *a) static bool trans_MFFS_ISA207(DisasContext *ctx, arg_X_t_rc *a)
@ -691,7 +691,7 @@ static void gen_mtfsb0(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode); crb = 31 - crbD(ctx->opcode);
gen_reset_fpstatus(); gen_reset_fpstatus();
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb)); gen_helper_fpscr_clrbit(tcg_env, tcg_constant_i32(crb));
} }
if (unlikely(Rc(ctx->opcode) != 0)) { if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
@ -711,14 +711,14 @@ static void gen_mtfsb1(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode); crb = 31 - crbD(ctx->opcode);
/* XXX: we pretend we can only do IEEE floating-point computations */ /* XXX: we pretend we can only do IEEE floating-point computations */
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb)); gen_helper_fpscr_setbit(tcg_env, tcg_constant_i32(crb));
} }
if (unlikely(Rc(ctx->opcode) != 0)) { if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
} }
/* We can raise a deferred exception */ /* We can raise a deferred exception */
gen_helper_fpscr_check_status(cpu_env); gen_helper_fpscr_check_status(tcg_env);
} }
/* mtfsf */ /* mtfsf */
@ -748,13 +748,13 @@ static void gen_mtfsf(DisasContext *ctx)
} }
t1 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64();
get_fpr(t1, rB(ctx->opcode)); get_fpr(t1, rB(ctx->opcode));
gen_helper_store_fpscr(cpu_env, t1, t0); gen_helper_store_fpscr(tcg_env, t1, t0);
if (unlikely(Rc(ctx->opcode) != 0)) { if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
} }
/* We can raise a deferred exception */ /* We can raise a deferred exception */
gen_helper_fpscr_check_status(cpu_env); gen_helper_fpscr_check_status(tcg_env);
} }
/* mtfsfi */ /* mtfsfi */
@ -777,13 +777,13 @@ static void gen_mtfsfi(DisasContext *ctx)
sh = (8 * w) + 7 - bf; sh = (8 * w) + 7 - bf;
t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
t1 = tcg_constant_i32(1 << sh); t1 = tcg_constant_i32(1 << sh);
gen_helper_store_fpscr(cpu_env, t0, t1); gen_helper_store_fpscr(tcg_env, t0, t1);
if (unlikely(Rc(ctx->opcode) != 0)) { if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
} }
/* We can raise a deferred exception */ /* We can raise a deferred exception */
gen_helper_fpscr_check_status(cpu_env); gen_helper_fpscr_check_status(tcg_env);
} }
static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr) static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)

8
target/ppc/translate/processor-ctrl-impl.c.inc
View File

@ -35,9 +35,9 @@ static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a)
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
if (is_book3s_arch2x(ctx)) { if (is_book3s_arch2x(ctx)) {
gen_helper_book3s_msgclr(cpu_env, cpu_gpr[a->rb]); gen_helper_book3s_msgclr(tcg_env, cpu_gpr[a->rb]);
} else { } else {
gen_helper_msgclr(cpu_env, cpu_gpr[a->rb]); gen_helper_msgclr(tcg_env, cpu_gpr[a->rb]);
} }
#else #else
qemu_build_not_reached(); qemu_build_not_reached();
@ -75,7 +75,7 @@ static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a)
REQUIRE_INSNS_FLAGS2(ctx, ISA207S); REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
REQUIRE_SV(ctx); REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[a->rb]); gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]);
#else #else
qemu_build_not_reached(); qemu_build_not_reached();
#endif #endif
@ -88,7 +88,7 @@ static bool trans_MSGSNDP(DisasContext *ctx, arg_X_rb *a)
REQUIRE_INSNS_FLAGS2(ctx, ISA207S); REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
REQUIRE_SV(ctx); REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[a->rb]); gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]);
#else #else
qemu_build_not_reached(); qemu_build_not_reached();
#endif #endif

30
target/ppc/translate/spe-impl.c.inc
View File

@ -22,7 +22,7 @@ static inline void gen_evmra(DisasContext *ctx)
cpu_gprh[rA(ctx->opcode)]); cpu_gprh[rA(ctx->opcode)]);
/* spe_acc := tmp */ /* spe_acc := tmp */
tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc));
/* rD := rA */ /* rD := rA */
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
@ -457,7 +457,7 @@ static inline void gen_evmwumia(DisasContext *ctx)
/* acc := rD */ /* acc := rD */
gen_load_gpr64(tmp, rD(ctx->opcode)); gen_load_gpr64(tmp, rD(ctx->opcode));
tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc));
} }
static inline void gen_evmwumiaa(DisasContext *ctx) static inline void gen_evmwumiaa(DisasContext *ctx)
@ -479,13 +479,13 @@ static inline void gen_evmwumiaa(DisasContext *ctx)
gen_load_gpr64(tmp, rD(ctx->opcode)); gen_load_gpr64(tmp, rD(ctx->opcode));
/* Load acc */ /* Load acc */
tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); tcg_gen_ld_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* acc := tmp + acc */ /* acc := tmp + acc */
tcg_gen_add_i64(acc, acc, tmp); tcg_gen_add_i64(acc, acc, tmp);
/* Store acc */ /* Store acc */
tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); tcg_gen_st_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* rD := acc */ /* rD := acc */
gen_store_gpr64(rD(ctx->opcode), acc); gen_store_gpr64(rD(ctx->opcode), acc);
@ -529,7 +529,7 @@ static inline void gen_evmwsmia(DisasContext *ctx)
/* acc := rD */ /* acc := rD */
gen_load_gpr64(tmp, rD(ctx->opcode)); gen_load_gpr64(tmp, rD(ctx->opcode));
tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc));
} }
static inline void gen_evmwsmiaa(DisasContext *ctx) static inline void gen_evmwsmiaa(DisasContext *ctx)
@ -551,13 +551,13 @@ static inline void gen_evmwsmiaa(DisasContext *ctx)
gen_load_gpr64(tmp, rD(ctx->opcode)); gen_load_gpr64(tmp, rD(ctx->opcode));
/* Load acc */ /* Load acc */
tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); tcg_gen_ld_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* acc := tmp + acc */ /* acc := tmp + acc */
tcg_gen_add_i64(acc, acc, tmp); tcg_gen_add_i64(acc, acc, tmp);
/* Store acc */ /* Store acc */
tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); tcg_gen_st_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* rD := acc */ /* rD := acc */
gen_store_gpr64(rD(ctx->opcode), acc); gen_store_gpr64(rD(ctx->opcode), acc);
@ -878,7 +878,7 @@ static inline void gen_##name(DisasContext *ctx) \
{ \ { \
TCGv_i32 t0 = tcg_temp_new_i32(); \ TCGv_i32 t0 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
gen_helper_##name(t0, cpu_env, t0); \ gen_helper_##name(t0, tcg_env, t0); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
} }
#define GEN_SPEFPUOP_CONV_32_64(name) \ #define GEN_SPEFPUOP_CONV_32_64(name) \
@ -893,7 +893,7 @@ static inline void gen_##name(DisasContext *ctx) \
t0 = tcg_temp_new_i64(); \ t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i32(); \ t1 = tcg_temp_new_i32(); \
gen_load_gpr64(t0, rB(ctx->opcode)); \ gen_load_gpr64(t0, rB(ctx->opcode)); \
gen_helper_##name(t1, cpu_env, t0); \ gen_helper_##name(t1, tcg_env, t0); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
} }
#define GEN_SPEFPUOP_CONV_64_32(name) \ #define GEN_SPEFPUOP_CONV_64_32(name) \
@ -908,7 +908,7 @@ static inline void gen_##name(DisasContext *ctx) \
t0 = tcg_temp_new_i64(); \ t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i32(); \ t1 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
gen_helper_##name(t0, cpu_env, t1); \ gen_helper_##name(t0, tcg_env, t1); \
gen_store_gpr64(rD(ctx->opcode), t0); \ gen_store_gpr64(rD(ctx->opcode), t0); \
} }
#define GEN_SPEFPUOP_CONV_64_64(name) \ #define GEN_SPEFPUOP_CONV_64_64(name) \
@ -921,7 +921,7 @@ static inline void gen_##name(DisasContext *ctx) \
} \ } \
t0 = tcg_temp_new_i64(); \ t0 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rB(ctx->opcode)); \ gen_load_gpr64(t0, rB(ctx->opcode)); \
gen_helper_##name(t0, cpu_env, t0); \ gen_helper_##name(t0, tcg_env, t0); \
gen_store_gpr64(rD(ctx->opcode), t0); \ gen_store_gpr64(rD(ctx->opcode), t0); \
} }
#define GEN_SPEFPUOP_ARITH2_32_32(name) \ #define GEN_SPEFPUOP_ARITH2_32_32(name) \
@ -931,7 +931,7 @@ static inline void gen_##name(DisasContext *ctx) \
TCGv_i32 t1 = tcg_temp_new_i32(); \ TCGv_i32 t1 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
gen_helper_##name(t0, cpu_env, t0, t1); \ gen_helper_##name(t0, tcg_env, t0, t1); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
} }
#define GEN_SPEFPUOP_ARITH2_64_64(name) \ #define GEN_SPEFPUOP_ARITH2_64_64(name) \
@ -946,7 +946,7 @@ static inline void gen_##name(DisasContext *ctx) \
t1 = tcg_temp_new_i64(); \ t1 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rA(ctx->opcode)); \ gen_load_gpr64(t0, rA(ctx->opcode)); \
gen_load_gpr64(t1, rB(ctx->opcode)); \ gen_load_gpr64(t1, rB(ctx->opcode)); \
gen_helper_##name(t0, cpu_env, t0, t1); \ gen_helper_##name(t0, tcg_env, t0, t1); \
gen_store_gpr64(rD(ctx->opcode), t0); \ gen_store_gpr64(rD(ctx->opcode), t0); \
} }
#define GEN_SPEFPUOP_COMP_32(name) \ #define GEN_SPEFPUOP_COMP_32(name) \
@ -957,7 +957,7 @@ static inline void gen_##name(DisasContext *ctx) \
\ \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], tcg_env, t0, t1); \
} }
#define GEN_SPEFPUOP_COMP_64(name) \ #define GEN_SPEFPUOP_COMP_64(name) \
static inline void gen_##name(DisasContext *ctx) \ static inline void gen_##name(DisasContext *ctx) \
@ -971,7 +971,7 @@ static inline void gen_##name(DisasContext *ctx) \
t1 = tcg_temp_new_i64(); \ t1 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rA(ctx->opcode)); \ gen_load_gpr64(t0, rA(ctx->opcode)); \
gen_load_gpr64(t1, rB(ctx->opcode)); \ gen_load_gpr64(t1, rB(ctx->opcode)); \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], tcg_env, t0, t1); \
} }
/* Single precision floating-point vectors operations */ /* Single precision floating-point vectors operations */

26
target/ppc/translate/storage-ctrl-impl.c.inc
View File

@ -30,7 +30,7 @@ static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
REQUIRE_SV(ctx); REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
gen_helper_SLBIE(cpu_env, cpu_gpr[a->rb]); gen_helper_SLBIE(tcg_env, cpu_gpr[a->rb]);
#else #else
qemu_build_not_reached(); qemu_build_not_reached();
#endif #endif
@ -44,7 +44,7 @@ static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
REQUIRE_SV(ctx); REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
gen_helper_SLBIEG(cpu_env, cpu_gpr[a->rb]); gen_helper_SLBIEG(tcg_env, cpu_gpr[a->rb]);
#else #else
qemu_build_not_reached(); qemu_build_not_reached();
#endif #endif
@ -58,7 +58,7 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
REQUIRE_SV(ctx); REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
gen_helper_SLBIA(cpu_env, tcg_constant_i32(a->ih)); gen_helper_SLBIA(tcg_env, tcg_constant_i32(a->ih));
#else #else
qemu_build_not_reached(); qemu_build_not_reached();
#endif #endif
@ -72,7 +72,7 @@ static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a)
REQUIRE_SV(ctx); REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l)); gen_helper_SLBIAG(tcg_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
#else #else
qemu_build_not_reached(); qemu_build_not_reached();
#endif #endif
@ -86,7 +86,7 @@ static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
REQUIRE_SV(ctx); REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
gen_helper_SLBMTE(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]); gen_helper_SLBMTE(tcg_env, cpu_gpr[a->rb], cpu_gpr[a->rt]);
#else #else
qemu_build_not_reached(); qemu_build_not_reached();
#endif #endif
@ -100,7 +100,7 @@ static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
REQUIRE_SV(ctx); REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
gen_helper_SLBMFEV(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]); gen_helper_SLBMFEV(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]);
#else #else
qemu_build_not_reached(); qemu_build_not_reached();
#endif #endif
@ -114,7 +114,7 @@ static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a)
REQUIRE_SV(ctx); REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
gen_helper_SLBMFEE(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]); gen_helper_SLBMFEE(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]);
#else #else
qemu_build_not_reached(); qemu_build_not_reached();
#endif #endif
@ -137,7 +137,7 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
return true; return true;
} }
gen_helper_SLBFEE(cpu_gpr[a->rt], cpu_env, gen_helper_SLBFEE(cpu_gpr[a->rt], tcg_env,
cpu_gpr[a->rb]); cpu_gpr[a->rb]);
l1 = gen_new_label(); l1 = gen_new_label();
l2 = gen_new_label(); l2 = gen_new_label();
@ -211,7 +211,7 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
if (!local && NARROW_MODE(ctx)) { if (!local && NARROW_MODE(ctx)) {
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
tcg_gen_ext32u_tl(t0, cpu_gpr[rb]); tcg_gen_ext32u_tl(t0, cpu_gpr[rb]);
gen_helper_tlbie(cpu_env, t0); gen_helper_tlbie(tcg_env, t0);
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
/* /*
@ -219,7 +219,7 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
* otherwise the results are undefined. * otherwise the results are undefined.
*/ */
} else if (a->r) { } else if (a->r) {
gen_helper_tlbie_isa300(cpu_env, cpu_gpr[rb], cpu_gpr[a->rs], gen_helper_tlbie_isa300(tcg_env, cpu_gpr[rb], cpu_gpr[a->rs],
tcg_constant_i32(a->ric << TLBIE_F_RIC_SHIFT | tcg_constant_i32(a->ric << TLBIE_F_RIC_SHIFT |
a->prs << TLBIE_F_PRS_SHIFT | a->prs << TLBIE_F_PRS_SHIFT |
a->r << TLBIE_F_R_SHIFT | a->r << TLBIE_F_R_SHIFT |
@ -228,7 +228,7 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
#endif #endif
} else { } else {
gen_helper_tlbie(cpu_env, cpu_gpr[rb]); gen_helper_tlbie(tcg_env, cpu_gpr[rb]);
} }
if (local) { if (local) {
@ -236,9 +236,9 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
} }
t1 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32();
tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); tcg_gen_ld_i32(t1, tcg_env, offsetof(CPUPPCState, tlb_need_flush));
tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); tcg_gen_st_i32(t1, tcg_env, offsetof(CPUPPCState, tlb_need_flush));
return true; return true;
#endif #endif

34
target/ppc/translate/vmx-impl.c.inc
View File

@ -10,7 +10,7 @@
static inline TCGv_ptr gen_avr_ptr(int reg) static inline TCGv_ptr gen_avr_ptr(int reg)
{ {
TCGv_ptr r = tcg_temp_new_ptr(); TCGv_ptr r = tcg_temp_new_ptr();
tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg)); tcg_gen_addi_ptr(r, tcg_env, avr_full_offset(reg));
return r; return r;
} }
@ -96,7 +96,7 @@ static void gen_lve##name(DisasContext *ctx) \
tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
} \ } \
rs = gen_avr_ptr(rS(ctx->opcode)); \ rs = gen_avr_ptr(rS(ctx->opcode)); \
gen_helper_lve##name(cpu_env, rs, EA); \ gen_helper_lve##name(tcg_env, rs, EA); \
} }
#define GEN_VR_STVE(name, opc2, opc3, size) \ #define GEN_VR_STVE(name, opc2, opc3, size) \
@ -115,7 +115,7 @@ static void gen_stve##name(DisasContext *ctx) \
tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
} \ } \
rs = gen_avr_ptr(rS(ctx->opcode)); \ rs = gen_avr_ptr(rS(ctx->opcode)); \
gen_helper_stve##name(cpu_env, rs, EA); \ gen_helper_stve##name(tcg_env, rs, EA); \
} }
GEN_VR_LDX(lvx, 0x07, 0x03); GEN_VR_LDX(lvx, 0x07, 0x03);
@ -146,7 +146,7 @@ static void gen_mfvscr(DisasContext *ctx)
tcg_gen_movi_i64(avr, 0); tcg_gen_movi_i64(avr, 0);
set_avr64(rD(ctx->opcode), avr, true); set_avr64(rD(ctx->opcode), avr, true);
t = tcg_temp_new_i32(); t = tcg_temp_new_i32();
gen_helper_mfvscr(t, cpu_env); gen_helper_mfvscr(t, tcg_env);
tcg_gen_extu_i32_i64(avr, t); tcg_gen_extu_i32_i64(avr, t);
set_avr64(rD(ctx->opcode), avr, false); set_avr64(rD(ctx->opcode), avr, false);
} }
@ -167,8 +167,8 @@ static void gen_mtvscr(DisasContext *ctx)
bofs += 3 * 4; bofs += 3 * 4;
#endif #endif
tcg_gen_ld_i32(val, cpu_env, bofs); tcg_gen_ld_i32(val, tcg_env, bofs);
gen_helper_mtvscr(cpu_env, val); gen_helper_mtvscr(tcg_env, val);
} }
static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry) static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry)
@ -287,7 +287,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
ra = gen_avr_ptr(rA(ctx->opcode)); \ ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \ rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \ rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, ra, rb); \ gen_helper_##name(tcg_env, rd, ra, rb); \
} }
#define GEN_VXFORM3(name, opc2, opc3) \ #define GEN_VXFORM3(name, opc2, opc3) \
@ -689,10 +689,10 @@ static void trans_vclzw(DisasContext *ctx)
/* Perform count for every word element using tcg_gen_clzi_i32. */ /* Perform count for every word element using tcg_gen_clzi_i32. */
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
tcg_gen_ld_i32(tmp, cpu_env, tcg_gen_ld_i32(tmp, tcg_env,
offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4); offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
tcg_gen_clzi_i32(tmp, tmp, 32); tcg_gen_clzi_i32(tmp, tmp, 32);
tcg_gen_st_i32(tmp, cpu_env, tcg_gen_st_i32(tmp, tcg_env,
offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4); offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
} }
} }
@ -1174,7 +1174,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
ra = gen_avr_ptr(rA(ctx->opcode)); \ ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \ rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \ rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##opname(cpu_env, rd, ra, rb); \ gen_helper_##opname(tcg_env, rd, ra, rb); \
} }
#define GEN_VXRFORM(name, opc2, opc3) \ #define GEN_VXRFORM(name, opc2, opc3) \
@ -1478,7 +1478,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
} \ } \
rb = gen_avr_ptr(rB(ctx->opcode)); \ rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \ rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, rb); \ gen_helper_##name(tcg_env, rd, rb); \
} }
#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \ #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
@ -1625,7 +1625,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
uimm = tcg_constant_i32(UIMM5(ctx->opcode)); \ uimm = tcg_constant_i32(UIMM5(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \ rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \ rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, rb, uimm); \ gen_helper_##name(tcg_env, rd, rb, uimm); \
} }
#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \ #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
@ -1813,7 +1813,7 @@ static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
if (right) { if (right) {
tcg_gen_subfi_tl(rc, 32 - size, rc); tcg_gen_subfi_tl(rc, 32 - size, rc);
} }
gen_helper(cpu_env, vrt, vra, vrb, rc); gen_helper(tcg_env, vrt, vra, vrb, rc);
return true; return true;
} }
@ -1841,7 +1841,7 @@ static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
tcg_gen_subfi_tl(idx, 16 - size, idx); tcg_gen_subfi_tl(idx, 16 - size, idx);
} }
gen_helper(cpu_env, t, rb, idx); gen_helper(tcg_env, t, rb, idx);
return true; return true;
} }
@ -2349,9 +2349,9 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
rc = gen_avr_ptr(rC(ctx->opcode)); \ rc = gen_avr_ptr(rC(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \ rd = gen_avr_ptr(rD(ctx->opcode)); \
if (Rc(ctx->opcode)) { \ if (Rc(ctx->opcode)) { \
gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ gen_helper_##name1(tcg_env, rd, ra, rb, rc); \
} else { \ } else { \
gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ gen_helper_##name0(tcg_env, rd, ra, rb, rc); \
} \ } \
} }
@ -2437,7 +2437,7 @@ static bool do_va_env_helper(DisasContext *ctx, arg_VA *a,
vra = gen_avr_ptr(a->vra); vra = gen_avr_ptr(a->vra);
vrb = gen_avr_ptr(a->vrb); vrb = gen_avr_ptr(a->vrb);
vrc = gen_avr_ptr(a->rc); vrc = gen_avr_ptr(a->rc);
gen_helper(cpu_env, vrt, vra, vrb, vrc); gen_helper(tcg_env, vrt, vra, vrb, vrc);
return true; return true;
} }

54
target/ppc/translate/vsx-impl.c.inc
View File

@ -2,25 +2,25 @@
static inline void get_cpu_vsr(TCGv_i64 dst, int n, bool high) static inline void get_cpu_vsr(TCGv_i64 dst, int n, bool high)
{ {
tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, high)); tcg_gen_ld_i64(dst, tcg_env, vsr64_offset(n, high));
} }
static inline void set_cpu_vsr(int n, TCGv_i64 src, bool high) static inline void set_cpu_vsr(int n, TCGv_i64 src, bool high)
{ {
tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, high)); tcg_gen_st_i64(src, tcg_env, vsr64_offset(n, high));
} }
static inline TCGv_ptr gen_vsr_ptr(int reg) static inline TCGv_ptr gen_vsr_ptr(int reg)
{ {
TCGv_ptr r = tcg_temp_new_ptr(); TCGv_ptr r = tcg_temp_new_ptr();
tcg_gen_addi_ptr(r, cpu_env, vsr_full_offset(reg)); tcg_gen_addi_ptr(r, tcg_env, vsr_full_offset(reg));
return r; return r;
} }
static inline TCGv_ptr gen_acc_ptr(int reg) static inline TCGv_ptr gen_acc_ptr(int reg)
{ {
TCGv_ptr r = tcg_temp_new_ptr(); TCGv_ptr r = tcg_temp_new_ptr();
tcg_gen_addi_ptr(r, cpu_env, acc_full_offset(reg)); tcg_gen_addi_ptr(r, tcg_env, acc_full_offset(reg));
return r; return r;
} }
@ -257,7 +257,7 @@ static void gen_##name(DisasContext *ctx) \
xt = gen_vsr_ptr(xT(ctx->opcode)); \ xt = gen_vsr_ptr(xT(ctx->opcode)); \
gen_set_access_type(ctx, ACCESS_INT); \ gen_set_access_type(ctx, ACCESS_INT); \
gen_addr_register(ctx, EA); \ gen_addr_register(ctx, EA); \
gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \ gen_helper_##name(tcg_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
} }
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl) VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
@ -801,10 +801,10 @@ static void gen_##name(DisasContext *ctx) \
xa = gen_vsr_ptr(xA(ctx->opcode)); \ xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \ xb = gen_vsr_ptr(xB(ctx->opcode)); \
if ((ctx->opcode >> (31 - 21)) & 1) { \ if ((ctx->opcode >> (31 - 21)) & 1) { \
gen_helper_##name(cpu_crf[6], cpu_env, xt, xa, xb); \ gen_helper_##name(cpu_crf[6], tcg_env, xt, xa, xb); \
} else { \ } else { \
ignored = tcg_temp_new_i32(); \ ignored = tcg_temp_new_i32(); \
gen_helper_##name(ignored, cpu_env, xt, xa, xb); \ gen_helper_##name(ignored, tcg_env, xt, xa, xb); \
} \ } \
} }
@ -829,7 +829,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
xt = gen_avr_ptr(a->rt); xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb); xb = gen_avr_ptr(a->rb);
gen_helper_XSCVQPDP(cpu_env, ro, xt, xb); gen_helper_XSCVQPDP(tcg_env, ro, xt, xb);
return true; return true;
} }
@ -843,7 +843,7 @@ static bool do_helper_env_X_tb(DisasContext *ctx, arg_X_tb *a,
xt = gen_avr_ptr(a->rt); xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb); xb = gen_avr_ptr(a->rb);
gen_helper(cpu_env, xt, xb); gen_helper(tcg_env, xt, xb);
return true; return true;
} }
@ -861,7 +861,7 @@ static void gen_##name(DisasContext *ctx) \
return; \ return; \
} \ } \
opc = tcg_constant_i32(ctx->opcode); \ opc = tcg_constant_i32(ctx->opcode); \
gen_helper_##name(cpu_env, opc); \ gen_helper_##name(tcg_env, opc); \
} }
#define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) \ #define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) \
@ -875,7 +875,7 @@ static void gen_##name(DisasContext *ctx) \
xt = gen_vsr_ptr(xT(ctx->opcode)); \ xt = gen_vsr_ptr(xT(ctx->opcode)); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \ xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \ xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, xt, xa, xb); \ gen_helper_##name(tcg_env, xt, xa, xb); \
} }
#define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) \ #define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) \
@ -888,7 +888,7 @@ static void gen_##name(DisasContext *ctx) \
} \ } \
xt = gen_vsr_ptr(xT(ctx->opcode)); \ xt = gen_vsr_ptr(xT(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \ xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, xt, xb); \ gen_helper_##name(tcg_env, xt, xb); \
} }
#define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) \ #define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) \
@ -903,7 +903,7 @@ static void gen_##name(DisasContext *ctx) \
opc = tcg_constant_i32(ctx->opcode); \ opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \ xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \ xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xa, xb); \ gen_helper_##name(tcg_env, opc, xa, xb); \
} }
#define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) \ #define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) \
@ -917,7 +917,7 @@ static void gen_##name(DisasContext *ctx) \
} \ } \
opc = tcg_constant_i32(ctx->opcode); \ opc = tcg_constant_i32(ctx->opcode); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \ xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xb); \ gen_helper_##name(tcg_env, opc, xb); \
} }
#define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) \ #define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) \
@ -933,7 +933,7 @@ static void gen_##name(DisasContext *ctx) \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \ xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xt, xa, xb); \ gen_helper_##name(tcg_env, opc, xt, xa, xb); \
} }
#define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) \ #define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) \
@ -948,7 +948,7 @@ static void gen_##name(DisasContext *ctx) \
opc = tcg_constant_i32(ctx->opcode); \ opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xt, xb); \ gen_helper_##name(tcg_env, opc, xt, xb); \
} }
#define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) \ #define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) \
@ -963,7 +963,7 @@ static void gen_##name(DisasContext *ctx) \
opc = tcg_constant_i32(ctx->opcode); \ opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \ xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xa, xb); \ gen_helper_##name(tcg_env, opc, xa, xb); \
} }
#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
@ -978,7 +978,7 @@ static void gen_##name(DisasContext *ctx) \
t0 = tcg_temp_new_i64(); \ t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i64(); \ t1 = tcg_temp_new_i64(); \
get_cpu_vsr(t0, xB(ctx->opcode), true); \ get_cpu_vsr(t0, xB(ctx->opcode), true); \
gen_helper_##name(t1, cpu_env, t0); \ gen_helper_##name(t1, tcg_env, t0); \
set_cpu_vsr(xT(ctx->opcode), t1, true); \ set_cpu_vsr(xT(ctx->opcode), t1, true); \
set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \ set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \
} }
@ -1191,7 +1191,7 @@ static bool do_XX2_bf_uim(DisasContext *ctx, arg_XX2_bf_uim *a, bool vsr,
REQUIRE_VSX(ctx); REQUIRE_VSX(ctx);
xb = vsr ? gen_vsr_ptr(a->xb) : gen_avr_ptr(a->xb); xb = vsr ? gen_vsr_ptr(a->xb) : gen_avr_ptr(a->xb);
gen_helper(cpu_env, tcg_constant_i32(a->bf), tcg_constant_i32(a->uim), xb); gen_helper(tcg_env, tcg_constant_i32(a->bf), tcg_constant_i32(a->uim), xb);
return true; return true;
} }
@ -1420,7 +1420,7 @@ static bool do_xsmadd(DisasContext *ctx, int tgt, int src1, int src2, int src3,
s2 = gen_vsr_ptr(src2); s2 = gen_vsr_ptr(src2);
s3 = gen_vsr_ptr(src3); s3 = gen_vsr_ptr(src3);
gen_helper(cpu_env, t, s1, s2, s3); gen_helper(tcg_env, t, s1, s2, s3);
return true; return true;
} }
@ -1500,7 +1500,7 @@ static void gen_##name(DisasContext *ctx) \
s2 = gen_vsr_ptr(xT(ctx->opcode)); \ s2 = gen_vsr_ptr(xT(ctx->opcode)); \
s3 = gen_vsr_ptr(xB(ctx->opcode)); \ s3 = gen_vsr_ptr(xB(ctx->opcode)); \
} \ } \
gen_helper_##name(cpu_env, xt, s1, s2, s3); \ gen_helper_##name(tcg_env, xt, s1, s2, s3); \
} }
GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
@ -1728,9 +1728,9 @@ static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
imm = tcg_constant_i32(a->si); imm = tcg_constant_i32(a->si);
tcg_gen_st_i32(imm, cpu_env, tcg_gen_st_i32(imm, tcg_env,
offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix))); offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix)));
tcg_gen_st_i32(imm, cpu_env, tcg_gen_st_i32(imm, tcg_env,
offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix))); offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix)));
return true; return true;
@ -2720,7 +2720,7 @@ static bool do_helper_XX3(DisasContext *ctx, arg_XX3 *a,
xa = gen_vsr_ptr(a->xa); xa = gen_vsr_ptr(a->xa);
xb = gen_vsr_ptr(a->xb); xb = gen_vsr_ptr(a->xb);
helper(cpu_env, xt, xa, xb); helper(tcg_env, xt, xa, xb);
return true; return true;
} }
@ -2741,7 +2741,7 @@ static bool do_helper_X(arg_X *a,
ra = gen_avr_ptr(a->ra); ra = gen_avr_ptr(a->ra);
rb = gen_avr_ptr(a->rb); rb = gen_avr_ptr(a->rb);
helper(cpu_env, rt, ra, rb); helper(tcg_env, rt, ra, rb);
return true; return true;
} }
@ -2770,7 +2770,7 @@ static bool trans_XVCVSPBF16(DisasContext *ctx, arg_XX2 *a)
xt = gen_vsr_ptr(a->xt); xt = gen_vsr_ptr(a->xt);
xb = gen_vsr_ptr(a->xb); xb = gen_vsr_ptr(a->xb);
gen_helper_XVCVSPBF16(cpu_env, xt, xb); gen_helper_XVCVSPBF16(tcg_env, xt, xb);
return true; return true;
} }
@ -2833,7 +2833,7 @@ static bool do_ger(DisasContext *ctx, arg_MMIRR_XX3 *a,
xb = gen_vsr_ptr(a->xb); xb = gen_vsr_ptr(a->xb);
mask = ger_pack_masks(a->pmsk, a->ymsk, a->xmsk); mask = ger_pack_masks(a->pmsk, a->ymsk, a->xmsk);
helper(cpu_env, xa, xb, xt, tcg_constant_i32(mask)); helper(tcg_env, xa, xb, xt, tcg_constant_i32(mask));
return true; return true;
} }

8
target/riscv/insn_trans/trans_privileged.c.inc
View File

@ -78,7 +78,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
if (has_ext(ctx, RVS)) { if (has_ext(ctx, RVS)) {
decode_save_opc(ctx); decode_save_opc(ctx);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_sret(cpu_pc, cpu_env); gen_helper_sret(cpu_pc, tcg_env);
exit_tb(ctx); /* no chaining */ exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
} else { } else {
@ -95,7 +95,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
decode_save_opc(ctx); decode_save_opc(ctx);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_mret(cpu_pc, cpu_env); gen_helper_mret(cpu_pc, tcg_env);
exit_tb(ctx); /* no chaining */ exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return true; return true;
@ -109,7 +109,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
decode_save_opc(ctx); decode_save_opc(ctx);
gen_update_pc(ctx, ctx->cur_insn_len); gen_update_pc(ctx, ctx->cur_insn_len);
gen_helper_wfi(cpu_env); gen_helper_wfi(tcg_env);
return true; return true;
#else #else
return false; return false;
@ -120,7 +120,7 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
decode_save_opc(ctx); decode_save_opc(ctx);
gen_helper_tlb_flush(cpu_env); gen_helper_tlb_flush(tcg_env);
return true; return true;
#endif #endif
return false; return false;

10
target/riscv/insn_trans/trans_rvbf16.c.inc
View File

@ -43,7 +43,7 @@ static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_bf16_s(dest, cpu_env, src1); gen_helper_fcvt_bf16_s(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -58,7 +58,7 @@ static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fcvt_s_bf16 *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_bf16(dest, cpu_env, src1); gen_helper_fcvt_s_bf16(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -82,7 +82,7 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
data = FIELD_DP32(data, VDATA, VTA, ctx->vta); data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
data = FIELD_DP32(data, VDATA, VMA, ctx->vma); data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
vreg_ofs(ctx, a->rs2), cpu_env, vreg_ofs(ctx, a->rs2), tcg_env,
ctx->cfg_ptr->vlen / 8, ctx->cfg_ptr->vlen / 8,
ctx->cfg_ptr->vlen / 8, data, ctx->cfg_ptr->vlen / 8, data,
gen_helper_vfncvtbf16_f_f_w); gen_helper_vfncvtbf16_f_f_w);
@ -111,7 +111,7 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
data = FIELD_DP32(data, VDATA, VTA, ctx->vta); data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
data = FIELD_DP32(data, VDATA, VMA, ctx->vma); data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
vreg_ofs(ctx, a->rs2), cpu_env, vreg_ofs(ctx, a->rs2), tcg_env,
ctx->cfg_ptr->vlen / 8, ctx->cfg_ptr->vlen / 8,
ctx->cfg_ptr->vlen / 8, data, ctx->cfg_ptr->vlen / 8, data,
gen_helper_vfwcvtbf16_f_f_v); gen_helper_vfwcvtbf16_f_f_v);
@ -142,7 +142,7 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
data = FIELD_DP32(data, VDATA, VMA, ctx->vma); data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), tcg_gen_gvec_4_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
vreg_ofs(ctx, a->rs1), vreg_ofs(ctx, a->rs1),
vreg_ofs(ctx, a->rs2), cpu_env, vreg_ofs(ctx, a->rs2), tcg_env,
ctx->cfg_ptr->vlen / 8, ctx->cfg_ptr->vlen / 8,
ctx->cfg_ptr->vlen / 8, data, ctx->cfg_ptr->vlen / 8, data,
gen_helper_vfwmaccbf16_vv); gen_helper_vfwmaccbf16_vv);

48
target/riscv/insn_trans/trans_rvd.c.inc
View File

@ -91,7 +91,7 @@ static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
TCGv_i64 src3 = get_fpr_d(ctx, a->rs3); TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fmadd_d(dest, cpu_env, src1, src2, src3); gen_helper_fmadd_d(dest, tcg_env, src1, src2, src3);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -109,7 +109,7 @@ static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
TCGv_i64 src3 = get_fpr_d(ctx, a->rs3); TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fmsub_d(dest, cpu_env, src1, src2, src3); gen_helper_fmsub_d(dest, tcg_env, src1, src2, src3);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -127,7 +127,7 @@ static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
TCGv_i64 src3 = get_fpr_d(ctx, a->rs3); TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fnmsub_d(dest, cpu_env, src1, src2, src3); gen_helper_fnmsub_d(dest, tcg_env, src1, src2, src3);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -145,7 +145,7 @@ static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
TCGv_i64 src3 = get_fpr_d(ctx, a->rs3); TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fnmadd_d(dest, cpu_env, src1, src2, src3); gen_helper_fnmadd_d(dest, tcg_env, src1, src2, src3);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -162,7 +162,7 @@ static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fadd_d(dest, cpu_env, src1, src2); gen_helper_fadd_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -179,7 +179,7 @@ static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fsub_d(dest, cpu_env, src1, src2); gen_helper_fsub_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -196,7 +196,7 @@ static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fmul_d(dest, cpu_env, src1, src2); gen_helper_fmul_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -213,7 +213,7 @@ static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fdiv_d(dest, cpu_env, src1, src2); gen_helper_fdiv_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -229,7 +229,7 @@ static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fsqrt_d(dest, cpu_env, src1); gen_helper_fsqrt_d(dest, tcg_env, src1);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -308,7 +308,7 @@ static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_helper_fmin_d(dest, cpu_env, src1, src2); gen_helper_fmin_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -324,7 +324,7 @@ static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_helper_fmax_d(dest, cpu_env, src1, src2); gen_helper_fmax_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -340,7 +340,7 @@ static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_d(dest, cpu_env, src1); gen_helper_fcvt_s_d(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -356,7 +356,7 @@ static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_s(dest, cpu_env, src1); gen_helper_fcvt_d_s(dest, tcg_env, src1);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -372,7 +372,7 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_helper_feq_d(dest, cpu_env, src1, src2); gen_helper_feq_d(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -387,7 +387,7 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_helper_flt_d(dest, cpu_env, src1, src2); gen_helper_flt_d(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -402,7 +402,7 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_helper_fle_d(dest, cpu_env, src1, src2); gen_helper_fle_d(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -431,7 +431,7 @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_w_d(dest, cpu_env, src1); gen_helper_fcvt_w_d(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -446,7 +446,7 @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_wu_d(dest, cpu_env, src1); gen_helper_fcvt_wu_d(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -461,7 +461,7 @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN); TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_w(dest, cpu_env, src); gen_helper_fcvt_d_w(dest, tcg_env, src);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -478,7 +478,7 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO); TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_wu(dest, cpu_env, src); gen_helper_fcvt_d_wu(dest, tcg_env, src);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -496,7 +496,7 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_l_d(dest, cpu_env, src1); gen_helper_fcvt_l_d(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -512,7 +512,7 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_lu_d(dest, cpu_env, src1); gen_helper_fcvt_lu_d(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -542,7 +542,7 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN); TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_l(dest, cpu_env, src); gen_helper_fcvt_d_l(dest, tcg_env, src);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -560,7 +560,7 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO); TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_lu(dest, cpu_env, src); gen_helper_fcvt_d_lu(dest, tcg_env, src);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);

46
target/riscv/insn_trans/trans_rvf.c.inc
View File

@ -93,7 +93,7 @@ static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3); TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fmadd_s(dest, cpu_env, src1, src2, src3); gen_helper_fmadd_s(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -110,7 +110,7 @@ static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3); TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fmsub_s(dest, cpu_env, src1, src2, src3); gen_helper_fmsub_s(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -127,7 +127,7 @@ static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3); TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fnmsub_s(dest, cpu_env, src1, src2, src3); gen_helper_fnmsub_s(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -144,7 +144,7 @@ static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3); TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fnmadd_s(dest, cpu_env, src1, src2, src3); gen_helper_fnmadd_s(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -160,7 +160,7 @@ static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fadd_s(dest, cpu_env, src1, src2); gen_helper_fadd_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -176,7 +176,7 @@ static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fsub_s(dest, cpu_env, src1, src2); gen_helper_fsub_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -192,7 +192,7 @@ static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fmul_s(dest, cpu_env, src1, src2); gen_helper_fmul_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -208,7 +208,7 @@ static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fdiv_s(dest, cpu_env, src1, src2); gen_helper_fdiv_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -223,7 +223,7 @@ static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fsqrt_s(dest, cpu_env, src1); gen_helper_fsqrt_s(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -363,7 +363,7 @@ static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fmin_s(dest, cpu_env, src1, src2); gen_helper_fmin_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -378,7 +378,7 @@ static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fmax_s(dest, cpu_env, src1, src2); gen_helper_fmax_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -393,7 +393,7 @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_w_s(dest, cpu_env, src1); gen_helper_fcvt_w_s(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -407,7 +407,7 @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_wu_s(dest, cpu_env, src1); gen_helper_fcvt_wu_s(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -439,7 +439,7 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_feq_s(dest, cpu_env, src1, src2); gen_helper_feq_s(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -453,7 +453,7 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_flt_s(dest, cpu_env, src1, src2); gen_helper_flt_s(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -467,7 +467,7 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fle_s(dest, cpu_env, src1, src2); gen_helper_fle_s(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -480,7 +480,7 @@ static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
TCGv dest = dest_gpr(ctx, a->rd); TCGv dest = dest_gpr(ctx, a->rd);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_helper_fclass_s(dest, cpu_env, src1); gen_helper_fclass_s(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -494,7 +494,7 @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN); TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_w(dest, cpu_env, src); gen_helper_fcvt_s_w(dest, tcg_env, src);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -509,7 +509,7 @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO); TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_wu(dest, cpu_env, src); gen_helper_fcvt_s_wu(dest, tcg_env, src);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -541,7 +541,7 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_l_s(dest, cpu_env, src1); gen_helper_fcvt_l_s(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -556,7 +556,7 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_lu_s(dest, cpu_env, src1); gen_helper_fcvt_lu_s(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -571,7 +571,7 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN); TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_l(dest, cpu_env, src); gen_helper_fcvt_s_l(dest, tcg_env, src);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -587,7 +587,7 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO); TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_lu(dest, cpu_env, src); gen_helper_fcvt_s_lu(dest, tcg_env, src);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;

8
target/riscv/insn_trans/trans_rvh.c.inc
View File

@ -45,7 +45,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a,
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
decode_save_opc(ctx); decode_save_opc(ctx);
func(dest, cpu_env, addr); func(dest, tcg_env, addr);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -57,7 +57,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a,
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
decode_save_opc(ctx); decode_save_opc(ctx);
func(cpu_env, addr, data); func(tcg_env, addr, data);
return true; return true;
} }
#endif /* CONFIG_USER_ONLY */ #endif /* CONFIG_USER_ONLY */
@ -148,7 +148,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
REQUIRE_EXT(ctx, RVH); REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
decode_save_opc(ctx); decode_save_opc(ctx);
gen_helper_hyp_gvma_tlb_flush(cpu_env); gen_helper_hyp_gvma_tlb_flush(tcg_env);
return true; return true;
#endif #endif
return false; return false;
@ -159,7 +159,7 @@ static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
REQUIRE_EXT(ctx, RVH); REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
decode_save_opc(ctx); decode_save_opc(ctx);
gen_helper_hyp_tlb_flush(cpu_env); gen_helper_hyp_tlb_flush(tcg_env);
return true; return true;
#endif #endif
return false; return false;

16
target/riscv/insn_trans/trans_rvi.c.inc
View File

@ -830,7 +830,7 @@ static bool do_csrr(DisasContext *ctx, int rd, int rc)
TCGv_i32 csr = tcg_constant_i32(rc); TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_csrr(dest, cpu_env, csr); gen_helper_csrr(dest, tcg_env, csr);
gen_set_gpr(ctx, rd, dest); gen_set_gpr(ctx, rd, dest);
return do_csr_post(ctx); return do_csr_post(ctx);
} }
@ -840,7 +840,7 @@ static bool do_csrw(DisasContext *ctx, int rc, TCGv src)
TCGv_i32 csr = tcg_constant_i32(rc); TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_csrw(cpu_env, csr, src); gen_helper_csrw(tcg_env, csr, src);
return do_csr_post(ctx); return do_csr_post(ctx);
} }
@ -850,7 +850,7 @@ static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask)
TCGv_i32 csr = tcg_constant_i32(rc); TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_csrrw(dest, cpu_env, csr, src, mask); gen_helper_csrrw(dest, tcg_env, csr, src, mask);
gen_set_gpr(ctx, rd, dest); gen_set_gpr(ctx, rd, dest);
return do_csr_post(ctx); return do_csr_post(ctx);
} }
@ -862,8 +862,8 @@ static bool do_csrr_i128(DisasContext *ctx, int rd, int rc)
TCGv_i32 csr = tcg_constant_i32(rc); TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_csrr_i128(destl, cpu_env, csr); gen_helper_csrr_i128(destl, tcg_env, csr);
tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh)); tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh));
gen_set_gpr128(ctx, rd, destl, desth); gen_set_gpr128(ctx, rd, destl, desth);
return do_csr_post(ctx); return do_csr_post(ctx);
} }
@ -873,7 +873,7 @@ static bool do_csrw_i128(DisasContext *ctx, int rc, TCGv srcl, TCGv srch)
TCGv_i32 csr = tcg_constant_i32(rc); TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_csrw_i128(cpu_env, csr, srcl, srch); gen_helper_csrw_i128(tcg_env, csr, srcl, srch);
return do_csr_post(ctx); return do_csr_post(ctx);
} }
@ -885,8 +885,8 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
TCGv_i32 csr = tcg_constant_i32(rc); TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base); translator_io_start(&ctx->base);
gen_helper_csrrw_i128(destl, cpu_env, csr, srcl, srch, maskl, maskh); gen_helper_csrrw_i128(destl, tcg_env, csr, srcl, srch, maskl, maskh);
tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh)); tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh));
gen_set_gpr128(ctx, rd, destl, desth); gen_set_gpr128(ctx, rd, destl, desth);
return do_csr_post(ctx); return do_csr_post(ctx);
} }

16
target/riscv/insn_trans/trans_rvm.c.inc
View File

@ -169,8 +169,8 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
static void gen_div_i128(TCGv rdl, TCGv rdh, static void gen_div_i128(TCGv rdl, TCGv rdh,
TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
{ {
gen_helper_divs_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h); gen_helper_divs_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh)); tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
} }
static void gen_div(TCGv ret, TCGv source1, TCGv source2) static void gen_div(TCGv ret, TCGv source1, TCGv source2)
@ -212,8 +212,8 @@ static bool trans_div(DisasContext *ctx, arg_div *a)
static void gen_divu_i128(TCGv rdl, TCGv rdh, static void gen_divu_i128(TCGv rdl, TCGv rdh,
TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
{ {
gen_helper_divu_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h); gen_helper_divu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh)); tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
} }
static void gen_divu(TCGv ret, TCGv source1, TCGv source2) static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
@ -244,8 +244,8 @@ static bool trans_divu(DisasContext *ctx, arg_divu *a)
static void gen_rem_i128(TCGv rdl, TCGv rdh, static void gen_rem_i128(TCGv rdl, TCGv rdh,
TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
{ {
gen_helper_rems_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h); gen_helper_rems_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh)); tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
} }
static void gen_rem(TCGv ret, TCGv source1, TCGv source2) static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
@ -289,8 +289,8 @@ static bool trans_rem(DisasContext *ctx, arg_rem *a)
static void gen_remu_i128(TCGv rdl, TCGv rdh, static void gen_remu_i128(TCGv rdl, TCGv rdh,
TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
{ {
gen_helper_remu_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h); gen_helper_remu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh)); tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
} }
static void gen_remu(TCGv ret, TCGv source1, TCGv source2) static void gen_remu(TCGv ret, TCGv source1, TCGv source2)

130
target/riscv/insn_trans/trans_rvv.c.inc
View File

@ -165,7 +165,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
s1 = get_gpr(s, rs1, EXT_ZERO); s1 = get_gpr(s, rs1, EXT_ZERO);
} }
gen_helper_vsetvl(dst, cpu_env, s1, s2); gen_helper_vsetvl(dst, tcg_env, s1, s2);
gen_set_gpr(s, rd, dst); gen_set_gpr(s, rd, dst);
mark_vs_dirty(s); mark_vs_dirty(s);
@ -185,7 +185,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
dst = dest_gpr(s, rd); dst = dest_gpr(s, rd);
gen_helper_vsetvl(dst, cpu_env, s1, s2); gen_helper_vsetvl(dst, tcg_env, s1, s2);
gen_set_gpr(s, rd, dst); gen_set_gpr(s, rd, dst);
mark_vs_dirty(s); mark_vs_dirty(s);
gen_update_pc(s, s->cur_insn_len); gen_update_pc(s, s->cur_insn_len);
@ -633,10 +633,10 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
fn(dest, mask, base, cpu_env, desc); fn(dest, mask, base, tcg_env, desc);
if (!is_store) { if (!is_store) {
mark_vs_dirty(s); mark_vs_dirty(s);
@ -794,10 +794,10 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
fn(dest, mask, base, stride, cpu_env, desc); fn(dest, mask, base, stride, tcg_env, desc);
if (!is_store) { if (!is_store) {
mark_vs_dirty(s); mark_vs_dirty(s);
@ -900,11 +900,11 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
fn(dest, mask, base, index, cpu_env, desc); fn(dest, mask, base, index, tcg_env, desc);
if (!is_store) { if (!is_store) {
mark_vs_dirty(s); mark_vs_dirty(s);
@ -1039,10 +1039,10 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
fn(dest, mask, base, cpu_env, desc); fn(dest, mask, base, tcg_env, desc);
mark_vs_dirty(s); mark_vs_dirty(s);
gen_set_label(over); gen_set_label(over);
@ -1100,9 +1100,9 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
base = get_gpr(s, rs1, EXT_NONE); base = get_gpr(s, rs1, EXT_NONE);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
fn(dest, base, cpu_env, desc); fn(dest, base, tcg_env, desc);
if (!is_store) { if (!is_store) {
mark_vs_dirty(s); mark_vs_dirty(s);
@ -1199,7 +1199,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
data = FIELD_DP32(data, VDATA, VMA, s->vma); data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, s->cfg_ptr->vlen / 8, tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fn); s->cfg_ptr->vlen / 8, data, fn);
} }
mark_vs_dirty(s); mark_vs_dirty(s);
@ -1251,11 +1251,11 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
fn(dest, mask, src1, src2, cpu_env, desc); fn(dest, mask, src1, src2, tcg_env, desc);
mark_vs_dirty(s); mark_vs_dirty(s);
gen_set_label(over); gen_set_label(over);
@ -1413,11 +1413,11 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
fn(dest, mask, src1, src2, cpu_env, desc); fn(dest, mask, src1, src2, tcg_env, desc);
mark_vs_dirty(s); mark_vs_dirty(s);
gen_set_label(over); gen_set_label(over);
@ -1492,7 +1492,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs2),
cpu_env, s->cfg_ptr->vlen / 8, tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,
data, fn); data, fn);
mark_vs_dirty(s); mark_vs_dirty(s);
@ -1568,7 +1568,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs2),
cpu_env, s->cfg_ptr->vlen / 8, tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fn); s->cfg_ptr->vlen / 8, data, fn);
mark_vs_dirty(s); mark_vs_dirty(s);
gen_set_label(over); gen_set_label(over);
@ -1639,7 +1639,7 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
data = FIELD_DP32(data, VDATA, VMA, s->vma); data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1), tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8, vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fn); s->cfg_ptr->vlen / 8, data, fn);
mark_vs_dirty(s); mark_vs_dirty(s);
gen_set_label(over); gen_set_label(over);
@ -1830,7 +1830,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \ s->cfg_ptr->vlen / 8, data, \
fns[s->sew]); \ fns[s->sew]); \
@ -2036,7 +2036,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
cpu_env, s->cfg_ptr->vlen / 8, tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, s->cfg_ptr->vlen / 8, data,
fns[s->sew]); fns[s->sew]);
gen_set_label(over); gen_set_label(over);
@ -2084,8 +2084,8 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
tcg_gen_ext_tl_i64(s1_i64, s1); tcg_gen_ext_tl_i64(s1_i64, s1);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1_i64, cpu_env, desc); fns[s->sew](dest, s1_i64, tcg_env, desc);
} }
mark_vs_dirty(s); mark_vs_dirty(s);
@ -2123,8 +2123,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
dest = tcg_temp_new_ptr(); dest = tcg_temp_new_ptr();
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1, cpu_env, desc); fns[s->sew](dest, s1, tcg_env, desc);
mark_vs_dirty(s); mark_vs_dirty(s);
gen_set_label(over); gen_set_label(over);
@ -2274,7 +2274,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \ s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \ fns[s->sew - 1]); \
@ -2306,15 +2306,15 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
/* NaN-box f[rs1] */ /* NaN-box f[rs1] */
t1 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64();
do_nanbox(s, t1, cpu_fpr[rs1]); do_nanbox(s, t1, cpu_fpr[rs1]);
fn(dest, mask, t1, src2, cpu_env, desc); fn(dest, mask, t1, src2, tcg_env, desc);
mark_vs_dirty(s); mark_vs_dirty(s);
gen_set_label(over); gen_set_label(over);
@ -2390,7 +2390,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \ s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \ fns[s->sew - 1]); \
@ -2464,7 +2464,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \ s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \ fns[s->sew - 1]); \
@ -2580,7 +2580,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
data = FIELD_DP32(data, VDATA, VTA, s->vta); data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma); data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env, vreg_ofs(s, a->rs2), tcg_env,
s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fn); s->cfg_ptr->vlen / 8, data, fn);
mark_vs_dirty(s); mark_vs_dirty(s);
@ -2693,9 +2693,9 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
dest = tcg_temp_new_ptr(); dest = tcg_temp_new_ptr();
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew - 1](dest, t1, cpu_env, desc); fns[s->sew - 1](dest, t1, tcg_env, desc);
mark_vs_dirty(s); mark_vs_dirty(s);
gen_set_label(over); gen_set_label(over);
@ -2769,7 +2769,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \ s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \ fns[s->sew - 1]); \
@ -2820,7 +2820,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \ s->cfg_ptr->vlen / 8, data, \
fns[s->sew]); \ fns[s->sew]); \
@ -2887,7 +2887,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \ s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \ fns[s->sew - 1]); \
@ -2936,7 +2936,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \ s->cfg_ptr->vlen / 8, data, \
fns[s->sew]); \ fns[s->sew]); \
@ -3026,7 +3026,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, fn); \ s->cfg_ptr->vlen / 8, data, fn); \
mark_vs_dirty(s); \ mark_vs_dirty(s); \
@ -3064,10 +3064,10 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
gen_helper_vcpop_m(dst, mask, src2, cpu_env, desc); gen_helper_vcpop_m(dst, mask, src2, tcg_env, desc);
gen_set_gpr(s, a->rd, dst); gen_set_gpr(s, a->rd, dst);
return true; return true;
} }
@ -3093,10 +3093,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data)); s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc); gen_helper_vfirst_m(dst, mask, src2, tcg_env, desc);
gen_set_gpr(s, a->rd, dst); gen_set_gpr(s, a->rd, dst);
return true; return true;
} }
@ -3128,7 +3128,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
cpu_env, s->cfg_ptr->vlen / 8, \ tcg_env, s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \
data, fn); \ data, fn); \
mark_vs_dirty(s); \ mark_vs_dirty(s); \
@ -3170,7 +3170,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
gen_helper_viota_m_w, gen_helper_viota_m_d, gen_helper_viota_m_w, gen_helper_viota_m_d,
}; };
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env, vreg_ofs(s, a->rs2), tcg_env,
s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fns[s->sew]); s->cfg_ptr->vlen / 8, data, fns[s->sew]);
mark_vs_dirty(s); mark_vs_dirty(s);
@ -3200,7 +3200,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
gen_helper_vid_v_w, gen_helper_vid_v_d, gen_helper_vid_v_w, gen_helper_vid_v_d,
}; };
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
cpu_env, s->cfg_ptr->vlen / 8, tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,
data, fns[s->sew]); data, fns[s->sew]);
mark_vs_dirty(s); mark_vs_dirty(s);
@ -3288,7 +3288,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
/* Convert the index to a pointer. */ /* Convert the index to a pointer. */
tcg_gen_ext_i32_ptr(base, ofs); tcg_gen_ext_i32_ptr(base, ofs);
tcg_gen_add_ptr(base, base, cpu_env); tcg_gen_add_ptr(base, base, tcg_env);
/* Perform the load. */ /* Perform the load. */
load_element(dest, base, load_element(dest, base,
@ -3306,7 +3306,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
static void vec_element_loadi(DisasContext *s, TCGv_i64 dest, static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
int vreg, int idx, bool sign) int vreg, int idx, bool sign)
{ {
load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign); load_element(dest, tcg_env, endian_ofs(s, vreg, idx), s->sew, sign);
} }
/* Integer Scalar Move Instruction */ /* Integer Scalar Move Instruction */
@ -3340,7 +3340,7 @@ static void store_element(TCGv_i64 val, TCGv_ptr base,
static void vec_element_storei(DisasContext *s, int vreg, static void vec_element_storei(DisasContext *s, int vreg,
int idx, TCGv_i64 val) int idx, TCGv_i64 val)
{ {
store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew); store_element(val, tcg_env, endian_ofs(s, vreg, idx), s->sew);
} }
/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */ /* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
@ -3620,7 +3620,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
data = FIELD_DP32(data, VDATA, VTA, s->vta); data = FIELD_DP32(data, VDATA, VTA, s->vta);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, s->cfg_ptr->vlen / 8, tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, s->cfg_ptr->vlen / 8, data,
fns[s->sew]); fns[s->sew]);
mark_vs_dirty(s); mark_vs_dirty(s);
@ -3650,7 +3650,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
TCGLabel *over = gen_new_label(); \ TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \ tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
cpu_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \ tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
mark_vs_dirty(s); \ mark_vs_dirty(s); \
gen_set_label(over); \ gen_set_label(over); \
} \ } \
@ -3722,7 +3722,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VMA, s->vma); data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env, vreg_ofs(s, a->rs2), tcg_env,
s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fn); s->cfg_ptr->vlen / 8, data, fn);

30
target/riscv/insn_trans/trans_rvvk.c.inc
View File

@ -170,7 +170,7 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check)
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
data, fns[s->sew]); \ data, fns[s->sew]); \
mark_vs_dirty(s); \ mark_vs_dirty(s); \
@ -244,7 +244,7 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
/* save opcode for unwinding in case we throw an exception */ \ /* save opcode for unwinding in case we throw an exception */ \
decode_save_opc(s); \ decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \ egs = tcg_constant_i32(EGS); \
gen_helper_egs_check(egs, cpu_env); \ gen_helper_egs_check(egs, tcg_env); \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \ } \
\ \
@ -257,9 +257,9 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
rs2_v = tcg_temp_new_ptr(); \ rs2_v = tcg_temp_new_ptr(); \
desc = tcg_constant_i32( \ desc = tcg_constant_i32( \
simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \ simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); \ gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
mark_vs_dirty(s); \ mark_vs_dirty(s); \
gen_set_label(over); \ gen_set_label(over); \
return true; \ return true; \
@ -320,7 +320,7 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
/* save opcode for unwinding in case we throw an exception */ \ /* save opcode for unwinding in case we throw an exception */ \
decode_save_opc(s); \ decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \ egs = tcg_constant_i32(EGS); \
gen_helper_egs_check(egs, cpu_env); \ gen_helper_egs_check(egs, tcg_env); \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \ } \
\ \
@ -335,9 +335,9 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
uimm_v = tcg_constant_i32(a->rs1); \ uimm_v = tcg_constant_i32(a->rs1); \
desc = tcg_constant_i32( \ desc = tcg_constant_i32( \
simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \ simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); \ gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
mark_vs_dirty(s); \ mark_vs_dirty(s); \
gen_set_label(over); \ gen_set_label(over); \
return true; \ return true; \
@ -390,7 +390,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
/* save opcode for unwinding in case we throw an exception */ \ /* save opcode for unwinding in case we throw an exception */ \
decode_save_opc(s); \ decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \ egs = tcg_constant_i32(EGS); \
gen_helper_egs_check(egs, cpu_env); \ gen_helper_egs_check(egs, tcg_env); \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \ } \
\ \
@ -401,7 +401,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
data = FIELD_DP32(data, VDATA, VMA, s->vma); \ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
\ \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
data, gen_helper_##NAME); \ data, gen_helper_##NAME); \
\ \
@ -444,7 +444,7 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
/* save opcode for unwinding in case we throw an exception */ /* save opcode for unwinding in case we throw an exception */
decode_save_opc(s); decode_save_opc(s);
egs = tcg_constant_i32(ZVKNH_EGS); egs = tcg_constant_i32(ZVKNH_EGS);
gen_helper_egs_check(egs, cpu_env); gen_helper_egs_check(egs, tcg_env);
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
} }
@ -455,7 +455,7 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
data = FIELD_DP32(data, VDATA, VMA, s->vma); data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, s->cfg_ptr->vlen / 8, data,
s->sew == MO_32 ? s->sew == MO_32 ?
gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv); gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
@ -478,7 +478,7 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
/* save opcode for unwinding in case we throw an exception */ /* save opcode for unwinding in case we throw an exception */
decode_save_opc(s); decode_save_opc(s);
egs = tcg_constant_i32(ZVKNH_EGS); egs = tcg_constant_i32(ZVKNH_EGS);
gen_helper_egs_check(egs, cpu_env); gen_helper_egs_check(egs, tcg_env);
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
} }
@ -489,7 +489,7 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
data = FIELD_DP32(data, VDATA, VMA, s->vma); data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, s->cfg_ptr->vlen / 8, data,
s->sew == MO_32 ? s->sew == MO_32 ?
gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv); gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);

2
target/riscv/insn_trans/trans_rvzce.c.inc
View File

@ -298,7 +298,7 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
* that might come from cpu_ld*_code() in the helper. * that might come from cpu_ld*_code() in the helper.
*/ */
gen_update_pc(ctx, 0); gen_update_pc(ctx, 0);
gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index)); gen_helper_cm_jalt(cpu_pc, tcg_env, tcg_constant_i32(a->index));
/* c.jt vs c.jalt depends on the index. */ /* c.jt vs c.jalt depends on the index. */
if (a->index >= 32) { if (a->index >= 32) {

38
target/riscv/insn_trans/trans_rvzfa.c.inc
View File

@ -187,7 +187,7 @@ static bool trans_fminm_s(DisasContext *ctx, arg_fminm_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fminm_s(dest, cpu_env, src1, src2); gen_helper_fminm_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -204,7 +204,7 @@ static bool trans_fmaxm_s(DisasContext *ctx, arg_fmaxm_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fmaxm_s(dest, cpu_env, src1, src2); gen_helper_fmaxm_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -221,7 +221,7 @@ static bool trans_fminm_d(DisasContext *ctx, arg_fminm_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_helper_fminm_d(dest, cpu_env, src1, src2); gen_helper_fminm_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -238,7 +238,7 @@ static bool trans_fmaxm_d(DisasContext *ctx, arg_fmaxm_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_helper_fmaxm_d(dest, cpu_env, src1, src2); gen_helper_fmaxm_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -255,7 +255,7 @@ static bool trans_fminm_h(DisasContext *ctx, arg_fminm_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fminm_h(dest, cpu_env, src1, src2); gen_helper_fminm_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -272,7 +272,7 @@ static bool trans_fmaxm_h(DisasContext *ctx, arg_fmaxm_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fmaxm_h(dest, cpu_env, src1, src2); gen_helper_fmaxm_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -289,7 +289,7 @@ static bool trans_fround_s(DisasContext *ctx, arg_fround_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fround_s(dest, cpu_env, src1); gen_helper_fround_s(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -306,7 +306,7 @@ static bool trans_froundnx_s(DisasContext *ctx, arg_froundnx_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_froundnx_s(dest, cpu_env, src1); gen_helper_froundnx_s(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -323,7 +323,7 @@ static bool trans_fround_d(DisasContext *ctx, arg_fround_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fround_d(dest, cpu_env, src1); gen_helper_fround_d(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -340,7 +340,7 @@ static bool trans_froundnx_d(DisasContext *ctx, arg_froundnx_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_froundnx_d(dest, cpu_env, src1); gen_helper_froundnx_d(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -357,7 +357,7 @@ static bool trans_fround_h(DisasContext *ctx, arg_fround_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fround_h(dest, cpu_env, src1); gen_helper_fround_h(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -374,7 +374,7 @@ static bool trans_froundnx_h(DisasContext *ctx, arg_froundnx_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_froundnx_h(dest, cpu_env, src1); gen_helper_froundnx_h(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -393,7 +393,7 @@ bool trans_fcvtmod_w_d(DisasContext *ctx, arg_fcvtmod_w_d *a)
/* Rounding mode is RTZ. */ /* Rounding mode is RTZ. */
gen_set_rm(ctx, RISCV_FRM_RTZ); gen_set_rm(ctx, RISCV_FRM_RTZ);
gen_helper_fcvtmod_w_d(t1, cpu_env, src1); gen_helper_fcvtmod_w_d(t1, tcg_env, src1);
tcg_gen_trunc_i64_tl(dst, t1); tcg_gen_trunc_i64_tl(dst, t1);
gen_set_gpr(ctx, a->rd, dst); gen_set_gpr(ctx, a->rd, dst);
@ -440,7 +440,7 @@ bool trans_fleq_s(DisasContext *ctx, arg_fleq_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fleq_s(dest, cpu_env, src1, src2); gen_helper_fleq_s(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -455,7 +455,7 @@ bool trans_fltq_s(DisasContext *ctx, arg_fltq_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fltq_s(dest, cpu_env, src1, src2); gen_helper_fltq_s(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -470,7 +470,7 @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fleq_d(dest, cpu_env, src1, src2); gen_helper_fleq_d(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -485,7 +485,7 @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fltq_d(dest, cpu_env, src1, src2); gen_helper_fltq_d(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -500,7 +500,7 @@ bool trans_fleq_h(DisasContext *ctx, arg_fleq_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fleq_h(dest, cpu_env, src1, src2); gen_helper_fleq_h(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -515,7 +515,7 @@ bool trans_fltq_h(DisasContext *ctx, arg_fltq_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fltq_h(dest, cpu_env, src1, src2); gen_helper_fltq_h(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }

54
target/riscv/insn_trans/trans_rvzfh.c.inc
View File

@ -95,7 +95,7 @@ static bool trans_fmadd_h(DisasContext *ctx, arg_fmadd_h *a)
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3); TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fmadd_h(dest, cpu_env, src1, src2, src3); gen_helper_fmadd_h(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -112,7 +112,7 @@ static bool trans_fmsub_h(DisasContext *ctx, arg_fmsub_h *a)
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3); TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fmsub_h(dest, cpu_env, src1, src2, src3); gen_helper_fmsub_h(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -129,7 +129,7 @@ static bool trans_fnmsub_h(DisasContext *ctx, arg_fnmsub_h *a)
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3); TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fnmsub_h(dest, cpu_env, src1, src2, src3); gen_helper_fnmsub_h(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -146,7 +146,7 @@ static bool trans_fnmadd_h(DisasContext *ctx, arg_fnmadd_h *a)
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3); TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fnmadd_h(dest, cpu_env, src1, src2, src3); gen_helper_fnmadd_h(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -162,7 +162,7 @@ static bool trans_fadd_h(DisasContext *ctx, arg_fadd_h *a)
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fadd_h(dest, cpu_env, src1, src2); gen_helper_fadd_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -178,7 +178,7 @@ static bool trans_fsub_h(DisasContext *ctx, arg_fsub_h *a)
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fsub_h(dest, cpu_env, src1, src2); gen_helper_fsub_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -194,7 +194,7 @@ static bool trans_fmul_h(DisasContext *ctx, arg_fmul_h *a)
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fmul_h(dest, cpu_env, src1, src2); gen_helper_fmul_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -210,7 +210,7 @@ static bool trans_fdiv_h(DisasContext *ctx, arg_fdiv_h *a)
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fdiv_h(dest, cpu_env, src1, src2); gen_helper_fdiv_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -225,7 +225,7 @@ static bool trans_fsqrt_h(DisasContext *ctx, arg_fsqrt_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fsqrt_h(dest, cpu_env, src1); gen_helper_fsqrt_h(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -366,7 +366,7 @@ static bool trans_fmin_h(DisasContext *ctx, arg_fmin_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fmin_h(dest, cpu_env, src1, src2); gen_helper_fmin_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -381,7 +381,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fmax_h(dest, cpu_env, src1, src2); gen_helper_fmax_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
return true; return true;
@ -396,7 +396,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_h(dest, cpu_env, src1); gen_helper_fcvt_s_h(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -414,7 +414,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_h(dest, cpu_env, src1); gen_helper_fcvt_d_h(dest, tcg_env, src1);
gen_set_fpr_d(ctx, a->rd, dest); gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -431,7 +431,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_h_s(dest, cpu_env, src1); gen_helper_fcvt_h_s(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -448,7 +448,7 @@ static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_h_d(dest, cpu_env, src1); gen_helper_fcvt_h_d(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -464,7 +464,7 @@ static bool trans_feq_h(DisasContext *ctx, arg_feq_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_feq_h(dest, cpu_env, src1, src2); gen_helper_feq_h(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -478,7 +478,7 @@ static bool trans_flt_h(DisasContext *ctx, arg_flt_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_flt_h(dest, cpu_env, src1, src2); gen_helper_flt_h(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
@ -493,7 +493,7 @@ static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_helper_fle_h(dest, cpu_env, src1, src2); gen_helper_fle_h(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -506,7 +506,7 @@ static bool trans_fclass_h(DisasContext *ctx, arg_fclass_h *a)
TCGv dest = dest_gpr(ctx, a->rd); TCGv dest = dest_gpr(ctx, a->rd);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_helper_fclass_h(dest, cpu_env, src1); gen_helper_fclass_h(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -520,7 +520,7 @@ static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_w_h(dest, cpu_env, src1); gen_helper_fcvt_w_h(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -534,7 +534,7 @@ static bool trans_fcvt_wu_h(DisasContext *ctx, arg_fcvt_wu_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_wu_h(dest, cpu_env, src1); gen_helper_fcvt_wu_h(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -548,7 +548,7 @@ static bool trans_fcvt_h_w(DisasContext *ctx, arg_fcvt_h_w *a)
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_h_w(dest, cpu_env, t0); gen_helper_fcvt_h_w(dest, tcg_env, t0);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -564,7 +564,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a)
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_h_wu(dest, cpu_env, t0); gen_helper_fcvt_h_wu(dest, tcg_env, t0);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -615,7 +615,7 @@ static bool trans_fcvt_l_h(DisasContext *ctx, arg_fcvt_l_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_l_h(dest, cpu_env, src1); gen_helper_fcvt_l_h(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -630,7 +630,7 @@ static bool trans_fcvt_lu_h(DisasContext *ctx, arg_fcvt_lu_h *a)
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_lu_h(dest, cpu_env, src1); gen_helper_fcvt_lu_h(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest); gen_set_gpr(ctx, a->rd, dest);
return true; return true;
} }
@ -645,7 +645,7 @@ static bool trans_fcvt_h_l(DisasContext *ctx, arg_fcvt_h_l *a)
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_h_l(dest, cpu_env, t0); gen_helper_fcvt_h_l(dest, tcg_env, t0);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);
@ -662,7 +662,7 @@ static bool trans_fcvt_h_lu(DisasContext *ctx, arg_fcvt_h_lu *a)
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm); gen_set_rm(ctx, a->rm);
gen_helper_fcvt_h_lu(dest, cpu_env, t0); gen_helper_fcvt_h_lu(dest, tcg_env, t0);
gen_set_fpr_hs(ctx, a->rd, dest); gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx); mark_fs_dirty(ctx);

8
target/riscv/insn_trans/trans_rvzicbo.c.inc
View File

@ -31,27 +31,27 @@
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a) static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
{ {
REQUIRE_ZICBOM(ctx); REQUIRE_ZICBOM(ctx);
gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]); gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
return true; return true;
} }
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a) static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
{ {
REQUIRE_ZICBOM(ctx); REQUIRE_ZICBOM(ctx);
gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]); gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
return true; return true;
} }
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a) static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
{ {
REQUIRE_ZICBOM(ctx); REQUIRE_ZICBOM(ctx);
gen_helper_cbo_inval(cpu_env, cpu_gpr[a->rs1]); gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
return true; return true;
} }
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a) static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
{ {
REQUIRE_ZICBOZ(ctx); REQUIRE_ZICBOZ(ctx);
gen_helper_cbo_zero(cpu_env, cpu_gpr[a->rs1]); gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
return true; return true;
} }

6
target/riscv/insn_trans/trans_svinval.c.inc
View File

@ -29,7 +29,7 @@ static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
REQUIRE_EXT(ctx, RVS); REQUIRE_EXT(ctx, RVS);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
decode_save_opc(ctx); decode_save_opc(ctx);
gen_helper_tlb_flush(cpu_env); gen_helper_tlb_flush(tcg_env);
return true; return true;
#endif #endif
return false; return false;
@ -58,7 +58,7 @@ static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
REQUIRE_EXT(ctx, RVH); REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
decode_save_opc(ctx); decode_save_opc(ctx);
gen_helper_hyp_tlb_flush(cpu_env); gen_helper_hyp_tlb_flush(tcg_env);
return true; return true;
#endif #endif
return false; return false;
@ -71,7 +71,7 @@ static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
REQUIRE_EXT(ctx, RVH); REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
decode_save_opc(ctx); decode_save_opc(ctx);
gen_helper_hyp_gvma_tlb_flush(cpu_env); gen_helper_hyp_gvma_tlb_flush(tcg_env);
return true; return true;
#endif #endif
return false; return false;

2
target/riscv/insn_trans/trans_xthead.c.inc
View File

@ -985,7 +985,7 @@ static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
REQUIRE_PRIV_MS(ctx); REQUIRE_PRIV_MS(ctx);
gen_helper_tlb_flush_all(cpu_env); gen_helper_tlb_flush_all(tcg_env);
return true; return true;
#else #else
return false; return false;

50
target/riscv/translate.c
View File

@ -238,13 +238,13 @@ static void gen_update_pc(DisasContext *ctx, target_long diff)
static void generate_exception(DisasContext *ctx, int excp) static void generate_exception(DisasContext *ctx, int excp)
{ {
gen_update_pc(ctx, 0); gen_update_pc(ctx, 0);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
} }
static void gen_exception_illegal(DisasContext *ctx) static void gen_exception_illegal(DisasContext *ctx)
{ {
tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env,
offsetof(CPURISCVState, bins)); offsetof(CPURISCVState, bins));
if (ctx->virt_inst_excp) { if (ctx->virt_inst_excp) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
@ -255,7 +255,7 @@ static void gen_exception_illegal(DisasContext *ctx)
static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target)
{ {
tcg_gen_st_tl(target, cpu_env, offsetof(CPURISCVState, badaddr)); tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr));
generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
} }
@ -263,7 +263,7 @@ static void lookup_and_goto_ptr(DisasContext *ctx)
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (ctx->itrigger) { if (ctx->itrigger) {
gen_helper_itrigger_match(cpu_env); gen_helper_itrigger_match(tcg_env);
} }
#endif #endif
tcg_gen_lookup_and_goto_ptr(); tcg_gen_lookup_and_goto_ptr();
@ -273,7 +273,7 @@ static void exit_tb(DisasContext *ctx)
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (ctx->itrigger) { if (ctx->itrigger) {
gen_helper_itrigger_match(cpu_env); gen_helper_itrigger_match(tcg_env);
} }
#endif #endif
tcg_gen_exit_tb(NULL, 0); tcg_gen_exit_tb(NULL, 0);
@ -630,14 +630,14 @@ static void mark_fs_dirty(DisasContext *ctx)
ctx->mstatus_fs = EXT_STATUS_DIRTY; ctx->mstatus_fs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new(); tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) { if (ctx->virt_enabled) {
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
} }
} }
} }
@ -659,14 +659,14 @@ static void mark_vs_dirty(DisasContext *ctx)
ctx->mstatus_vs = EXT_STATUS_DIRTY; ctx->mstatus_vs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new(); tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) { if (ctx->virt_enabled) {
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
} }
} }
} }
@ -688,7 +688,7 @@ static void gen_set_rm(DisasContext *ctx, int rm)
/* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
decode_save_opc(ctx); decode_save_opc(ctx);
gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm));
} }
static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) static void gen_set_rm_chkfrm(DisasContext *ctx, int rm)
@ -701,7 +701,7 @@ static void gen_set_rm_chkfrm(DisasContext *ctx, int rm)
/* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
decode_save_opc(ctx); decode_save_opc(ctx);
gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm));
} }
static int ex_plus_1(DisasContext *ctx, int nf) static int ex_plus_1(DisasContext *ctx, int nf)
@ -1306,28 +1306,28 @@ void riscv_translate_init(void)
cpu_gprh[0] = NULL; cpu_gprh[0] = NULL;
for (i = 1; i < 32; i++) { for (i = 1; i < 32; i++) {
cpu_gpr[i] = tcg_global_mem_new(cpu_env, cpu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
cpu_gprh[i] = tcg_global_mem_new(cpu_env, cpu_gprh[i] = tcg_global_mem_new(tcg_env,
offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]);
} }
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
} }
cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc");
cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl");
cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart),
"vstart"); "vstart");
load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res),
"load_res"); "load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
"load_val"); "load_val");
/* Assign PM CSRs to tcg globals */ /* Assign PM CSRs to tcg globals */
pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask),
"pmmask"); "pmmask");
pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase),
"pmbase"); "pmbase");
} }

56
target/rx/translate.c
View File

@ -237,7 +237,7 @@ static int is_privileged(DisasContext *ctx, int is_exception)
{ {
if (FIELD_EX32(ctx->tb_flags, PSW, PM)) { if (FIELD_EX32(ctx->tb_flags, PSW, PM)) {
if (is_exception) { if (is_exception) {
gen_helper_raise_privilege_violation(cpu_env); gen_helper_raise_privilege_violation(tcg_env);
} }
return 0; return 0;
} else { } else {
@ -318,7 +318,7 @@ static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc)
{ {
switch (cr) { switch (cr) {
case 0: /* PSW */ case 0: /* PSW */
gen_helper_pack_psw(ret, cpu_env); gen_helper_pack_psw(ret, tcg_env);
break; break;
case 1: /* PC */ case 1: /* PC */
tcg_gen_movi_i32(ret, pc); tcg_gen_movi_i32(ret, pc);
@ -370,7 +370,7 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int cr)
} }
switch (cr) { switch (cr) {
case 0: /* PSW */ case 0: /* PSW */
gen_helper_set_psw(cpu_env, val); gen_helper_set_psw(tcg_env, val);
if (is_privileged(ctx, 0)) { if (is_privileged(ctx, 0)) {
/* PSW.{I,U} may be updated here. exit TB. */ /* PSW.{I,U} may be updated here. exit TB. */
ctx->base.is_jmp = DISAS_UPDATE; ctx->base.is_jmp = DISAS_UPDATE;
@ -385,7 +385,7 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int cr)
} }
break; break;
case 3: /* FPSW */ case 3: /* FPSW */
gen_helper_set_fpsw(cpu_env, val); gen_helper_set_fpsw(tcg_env, val);
break; break;
case 8: /* BPSW */ case 8: /* BPSW */
tcg_gen_mov_i32(cpu_bpsw, val); tcg_gen_mov_i32(cpu_bpsw, val);
@ -1244,12 +1244,12 @@ static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a)
static void rx_div(TCGv ret, TCGv arg1, TCGv arg2) static void rx_div(TCGv ret, TCGv arg1, TCGv arg2)
{ {
gen_helper_div(ret, cpu_env, arg1, arg2); gen_helper_div(ret, tcg_env, arg1, arg2);
} }
static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2) static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2)
{ {
gen_helper_divu(ret, cpu_env, arg1, arg2); gen_helper_divu(ret, tcg_env, arg1, arg2);
} }
/* div #imm, rd */ /* div #imm, rd */
@ -1644,35 +1644,35 @@ static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
/* scmpu */ /* scmpu */
static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a)
{ {
gen_helper_scmpu(cpu_env); gen_helper_scmpu(tcg_env);
return true; return true;
} }
/* smovu */ /* smovu */
static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a)
{ {
gen_helper_smovu(cpu_env); gen_helper_smovu(tcg_env);
return true; return true;
} }
/* smovf */ /* smovf */
static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a)
{ {
gen_helper_smovf(cpu_env); gen_helper_smovf(tcg_env);
return true; return true;
} }
/* smovb */ /* smovb */
static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)
{ {
gen_helper_smovb(cpu_env); gen_helper_smovb(tcg_env);
return true; return true;
} }
#define STRING(op) \ #define STRING(op) \
do { \ do { \
TCGv size = tcg_constant_i32(a->sz); \ TCGv size = tcg_constant_i32(a->sz); \
gen_helper_##op(cpu_env, size); \ gen_helper_##op(tcg_env, size); \
} while (0) } while (0)
/* suntile.<bwl> */ /* suntile.<bwl> */
@ -1803,7 +1803,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a)
static bool trans_RACW(DisasContext *ctx, arg_RACW *a) static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
{ {
TCGv imm = tcg_constant_i32(a->imm + 1); TCGv imm = tcg_constant_i32(a->imm + 1);
gen_helper_racw(cpu_env, imm); gen_helper_racw(tcg_env, imm);
return true; return true;
} }
@ -1825,7 +1825,7 @@ static bool trans_SAT(DisasContext *ctx, arg_SAT *a)
/* satr */ /* satr */
static bool trans_SATR(DisasContext *ctx, arg_SATR *a) static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
{ {
gen_helper_satr(cpu_env); gen_helper_satr(tcg_env);
return true; return true;
} }
@ -1835,7 +1835,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
cat3(arg_, name, _ir) * a) \ cat3(arg_, name, _ir) * a) \
{ \ { \
TCGv imm = tcg_constant_i32(li(ctx, 0)); \ TCGv imm = tcg_constant_i32(li(ctx, 0)); \
gen_helper_##op(cpu_regs[a->rd], cpu_env, \ gen_helper_##op(cpu_regs[a->rd], tcg_env, \
cpu_regs[a->rd], imm); \ cpu_regs[a->rd], imm); \
return true; \ return true; \
} \ } \
@ -1845,7 +1845,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
TCGv val, mem; \ TCGv val, mem; \
mem = tcg_temp_new(); \ mem = tcg_temp_new(); \
val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
gen_helper_##op(cpu_regs[a->rd], cpu_env, \ gen_helper_##op(cpu_regs[a->rd], tcg_env, \
cpu_regs[a->rd], val); \ cpu_regs[a->rd], val); \
return true; \ return true; \
} }
@ -1856,7 +1856,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
TCGv val, mem; \ TCGv val, mem; \
mem = tcg_temp_new(); \ mem = tcg_temp_new(); \
val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \ gen_helper_##op(cpu_regs[a->rd], tcg_env, val); \
return true; \ return true; \
} }
@ -1869,7 +1869,7 @@ FOP(FDIV, fdiv)
static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
{ {
TCGv imm = tcg_constant_i32(li(ctx, 0)); TCGv imm = tcg_constant_i32(li(ctx, 0));
gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm); gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm);
return true; return true;
} }
@ -1880,7 +1880,7 @@ static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a)
TCGv val, mem; TCGv val, mem;
mem = tcg_temp_new(); mem = tcg_temp_new();
val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs);
gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val); gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val);
return true; return true;
} }
@ -1894,7 +1894,7 @@ static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a)
TCGv val, mem; TCGv val, mem;
mem = tcg_temp_new(); mem = tcg_temp_new();
val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
gen_helper_itof(cpu_regs[a->rd], cpu_env, val); gen_helper_itof(cpu_regs[a->rd], tcg_env, val);
return true; return true;
} }
@ -2146,7 +2146,7 @@ static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a)
psw = tcg_temp_new(); psw = tcg_temp_new();
tcg_gen_mov_i32(cpu_pc, cpu_bpc); tcg_gen_mov_i32(cpu_pc, cpu_bpc);
tcg_gen_mov_i32(psw, cpu_bpsw); tcg_gen_mov_i32(psw, cpu_bpsw);
gen_helper_set_psw_rte(cpu_env, psw); gen_helper_set_psw_rte(tcg_env, psw);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
} }
return true; return true;
@ -2160,7 +2160,7 @@ static bool trans_RTE(DisasContext *ctx, arg_RTE *a)
psw = tcg_temp_new(); psw = tcg_temp_new();
pop(cpu_pc); pop(cpu_pc);
pop(psw); pop(psw);
gen_helper_set_psw_rte(cpu_env, psw); gen_helper_set_psw_rte(tcg_env, psw);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
} }
return true; return true;
@ -2170,7 +2170,7 @@ static bool trans_RTE(DisasContext *ctx, arg_RTE *a)
static bool trans_BRK(DisasContext *ctx, arg_BRK *a) static bool trans_BRK(DisasContext *ctx, arg_BRK *a)
{ {
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
gen_helper_rxbrk(cpu_env); gen_helper_rxbrk(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return true; return true;
} }
@ -2183,7 +2183,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
tcg_debug_assert(a->imm < 0x100); tcg_debug_assert(a->imm < 0x100);
vec = tcg_constant_i32(a->imm); vec = tcg_constant_i32(a->imm);
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
gen_helper_rxint(cpu_env, vec); gen_helper_rxint(tcg_env, vec);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return true; return true;
} }
@ -2193,7 +2193,7 @@ static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a)
{ {
if (is_privileged(ctx, 1)) { if (is_privileged(ctx, 1)) {
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
gen_helper_wait(cpu_env); gen_helper_wait(tcg_env);
} }
return true; return true;
} }
@ -2225,7 +2225,7 @@ static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
ctx->pc = ctx->base.pc_next; ctx->pc = ctx->base.pc_next;
insn = decode_load(ctx); insn = decode_load(ctx);
if (!decode(ctx, insn)) { if (!decode(ctx, insn)) {
gen_helper_raise_illegal_instruction(cpu_env); gen_helper_raise_illegal_instruction(tcg_env);
} }
} }
@ -2279,7 +2279,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
} }
#define ALLOC_REGISTER(sym, name) \ #define ALLOC_REGISTER(sym, name) \
cpu_##sym = tcg_global_mem_new_i32(cpu_env, \ cpu_##sym = tcg_global_mem_new_i32(tcg_env, \
offsetof(CPURXState, sym), name) offsetof(CPURXState, sym), name)
void rx_translate_init(void) void rx_translate_init(void)
@ -2291,7 +2291,7 @@ void rx_translate_init(void)
int i; int i;
for (i = 0; i < NUM_REGS; i++) { for (i = 0; i < NUM_REGS; i++) {
cpu_regs[i] = tcg_global_mem_new_i32(cpu_env, cpu_regs[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPURXState, regs[i]), offsetof(CPURXState, regs[i]),
regnames[i]); regnames[i]);
} }
@ -2311,6 +2311,6 @@ void rx_translate_init(void)
ALLOC_REGISTER(isp, "ISP"); ALLOC_REGISTER(isp, "ISP");
ALLOC_REGISTER(fintv, "FINTV"); ALLOC_REGISTER(fintv, "FINTV");
ALLOC_REGISTER(intb, "INTB"); ALLOC_REGISTER(intb, "INTB");
cpu_acc = tcg_global_mem_new_i64(cpu_env, cpu_acc = tcg_global_mem_new_i64(tcg_env,
offsetof(CPURXState, acc), "ACC"); offsetof(CPURXState, acc), "ACC");
} }

424
target/s390x/tcg/translate.c
View File

File diff suppressed because it is too large Load Diff

104
target/s390x/tcg/translate_vx.c.inc
View File

@ -36,7 +36,7 @@
* *
* CC handling: * CC handling:
* As gvec ool-helpers can currently not return values (besides via * As gvec ool-helpers can currently not return values (besides via
* pointers like vectors or cpu_env), whenever we have to set the CC and * pointers like vectors or tcg_env), whenever we have to set the CC and
* can't conclude the value from the result vector, we will directly * can't conclude the value from the result vector, we will directly
* set it in "env->cc_op" and mark it as static via set_cc_static()". * set it in "env->cc_op" and mark it as static via set_cc_static()".
* Whenever this is done, the helper writes globals (cc_op). * Whenever this is done, the helper writes globals (cc_op).
@ -69,26 +69,26 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
switch ((unsigned)memop) { switch ((unsigned)memop) {
case ES_8: case ES_8:
tcg_gen_ld8u_i64(dst, cpu_env, offs); tcg_gen_ld8u_i64(dst, tcg_env, offs);
break; break;
case ES_16: case ES_16:
tcg_gen_ld16u_i64(dst, cpu_env, offs); tcg_gen_ld16u_i64(dst, tcg_env, offs);
break; break;
case ES_32: case ES_32:
tcg_gen_ld32u_i64(dst, cpu_env, offs); tcg_gen_ld32u_i64(dst, tcg_env, offs);
break; break;
case ES_8 | MO_SIGN: case ES_8 | MO_SIGN:
tcg_gen_ld8s_i64(dst, cpu_env, offs); tcg_gen_ld8s_i64(dst, tcg_env, offs);
break; break;
case ES_16 | MO_SIGN: case ES_16 | MO_SIGN:
tcg_gen_ld16s_i64(dst, cpu_env, offs); tcg_gen_ld16s_i64(dst, tcg_env, offs);
break; break;
case ES_32 | MO_SIGN: case ES_32 | MO_SIGN:
tcg_gen_ld32s_i64(dst, cpu_env, offs); tcg_gen_ld32s_i64(dst, tcg_env, offs);
break; break;
case ES_64: case ES_64:
case ES_64 | MO_SIGN: case ES_64 | MO_SIGN:
tcg_gen_ld_i64(dst, cpu_env, offs); tcg_gen_ld_i64(dst, tcg_env, offs);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -102,20 +102,20 @@ static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,
switch (memop) { switch (memop) {
case ES_8: case ES_8:
tcg_gen_ld8u_i32(dst, cpu_env, offs); tcg_gen_ld8u_i32(dst, tcg_env, offs);
break; break;
case ES_16: case ES_16:
tcg_gen_ld16u_i32(dst, cpu_env, offs); tcg_gen_ld16u_i32(dst, tcg_env, offs);
break; break;
case ES_8 | MO_SIGN: case ES_8 | MO_SIGN:
tcg_gen_ld8s_i32(dst, cpu_env, offs); tcg_gen_ld8s_i32(dst, tcg_env, offs);
break; break;
case ES_16 | MO_SIGN: case ES_16 | MO_SIGN:
tcg_gen_ld16s_i32(dst, cpu_env, offs); tcg_gen_ld16s_i32(dst, tcg_env, offs);
break; break;
case ES_32: case ES_32:
case ES_32 | MO_SIGN: case ES_32 | MO_SIGN:
tcg_gen_ld_i32(dst, cpu_env, offs); tcg_gen_ld_i32(dst, tcg_env, offs);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -129,16 +129,16 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
switch (memop) { switch (memop) {
case ES_8: case ES_8:
tcg_gen_st8_i64(src, cpu_env, offs); tcg_gen_st8_i64(src, tcg_env, offs);
break; break;
case ES_16: case ES_16:
tcg_gen_st16_i64(src, cpu_env, offs); tcg_gen_st16_i64(src, tcg_env, offs);
break; break;
case ES_32: case ES_32:
tcg_gen_st32_i64(src, cpu_env, offs); tcg_gen_st32_i64(src, tcg_env, offs);
break; break;
case ES_64: case ES_64:
tcg_gen_st_i64(src, cpu_env, offs); tcg_gen_st_i64(src, tcg_env, offs);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -152,13 +152,13 @@ static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr,
switch (memop) { switch (memop) {
case ES_8: case ES_8:
tcg_gen_st8_i32(src, cpu_env, offs); tcg_gen_st8_i32(src, tcg_env, offs);
break; break;
case ES_16: case ES_16:
tcg_gen_st16_i32(src, cpu_env, offs); tcg_gen_st16_i32(src, tcg_env, offs);
break; break;
case ES_32: case ES_32:
tcg_gen_st_i32(src, cpu_env, offs); tcg_gen_st_i32(src, tcg_env, offs);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -173,16 +173,16 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
/* mask off invalid parts from the element nr */ /* mask off invalid parts from the element nr */
tcg_gen_andi_i64(tmp, enr, NUM_VEC_ELEMENTS(es) - 1); tcg_gen_andi_i64(tmp, enr, NUM_VEC_ELEMENTS(es) - 1);
/* convert it to an element offset relative to cpu_env (vec_reg_offset() */ /* convert it to an element offset relative to tcg_env (vec_reg_offset() */
tcg_gen_shli_i64(tmp, tmp, es); tcg_gen_shli_i64(tmp, tmp, es);
#if !HOST_BIG_ENDIAN #if !HOST_BIG_ENDIAN
tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es)); tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es));
#endif #endif
tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg)); tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg));
/* generate the final ptr by adding cpu_env */ /* generate the final ptr by adding tcg_env */
tcg_gen_trunc_i64_ptr(ptr, tmp); tcg_gen_trunc_i64_ptr(ptr, tmp);
tcg_gen_add_ptr(ptr, ptr, cpu_env); tcg_gen_add_ptr(ptr, ptr, tcg_env);
} }
#define gen_gvec_2(v1, v2, gen) \ #define gen_gvec_2(v1, v2, gen) \
@ -754,8 +754,8 @@ static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o)
tcg_gen_ori_i64(bytes, o->addr1, -block_size); tcg_gen_ori_i64(bytes, o->addr1, -block_size);
tcg_gen_neg_i64(bytes, bytes); tcg_gen_neg_i64(bytes, bytes);
tcg_gen_addi_ptr(a0, cpu_env, v1_offs); tcg_gen_addi_ptr(a0, tcg_env, v1_offs);
gen_helper_vll(cpu_env, a0, o->addr1, bytes); gen_helper_vll(tcg_env, a0, o->addr1, bytes);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -812,8 +812,8 @@ static DisasJumpType op_vll(DisasContext *s, DisasOps *o)
/* convert highest index into an actual length */ /* convert highest index into an actual length */
tcg_gen_addi_i64(o->in2, o->in2, 1); tcg_gen_addi_i64(o->in2, o->in2, 1);
tcg_gen_addi_ptr(a0, cpu_env, v1_offs); tcg_gen_addi_ptr(a0, tcg_env, v1_offs);
gen_helper_vll(cpu_env, a0, o->addr1, o->in2); gen_helper_vll(tcg_env, a0, o->addr1, o->in2);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -898,7 +898,7 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
switch (s->fields.op2) { switch (s->fields.op2) {
case 0x97: case 0x97:
if (get_field(s, m5) & 0x1) { if (get_field(s, m5) & 0x1) {
gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpks_cc[es - 1]); gen_gvec_3_ptr(v1, v2, v3, tcg_env, 0, vpks_cc[es - 1]);
set_cc_static(s); set_cc_static(s);
} else { } else {
gen_gvec_3_ool(v1, v2, v3, 0, vpks[es - 1]); gen_gvec_3_ool(v1, v2, v3, 0, vpks[es - 1]);
@ -906,7 +906,7 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
break; break;
case 0x95: case 0x95:
if (get_field(s, m5) & 0x1) { if (get_field(s, m5) & 0x1) {
gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpkls_cc[es - 1]); gen_gvec_3_ptr(v1, v2, v3, tcg_env, 0, vpkls_cc[es - 1]);
set_cc_static(s); set_cc_static(s);
} else { } else {
gen_gvec_3_ool(v1, v2, v3, 0, vpkls[es - 1]); gen_gvec_3_ool(v1, v2, v3, 0, vpkls[es - 1]);
@ -1058,7 +1058,7 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
TCGv_i64 tmp; TCGv_i64 tmp;
/* Probe write access before actually modifying memory */ /* Probe write access before actually modifying memory */
gen_helper_probe_write_access(cpu_env, o->addr1, gen_helper_probe_write_access(tcg_env, o->addr1,
tcg_constant_i64(16)); tcg_constant_i64(16));
tmp = tcg_temp_new_i64(); tmp = tcg_temp_new_i64();
@ -1098,7 +1098,7 @@ static DisasJumpType op_vstbr(DisasContext *s, DisasOps *o)
} }
/* Probe write access before actually modifying memory */ /* Probe write access before actually modifying memory */
gen_helper_probe_write_access(cpu_env, o->addr1, tcg_constant_i64(16)); gen_helper_probe_write_access(tcg_env, o->addr1, tcg_constant_i64(16));
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64();
@ -1169,7 +1169,7 @@ static DisasJumpType op_vster(DisasContext *s, DisasOps *o)
} }
/* Probe write access before actually modifying memory */ /* Probe write access before actually modifying memory */
gen_helper_probe_write_access(cpu_env, o->addr1, tcg_constant_i64(16)); gen_helper_probe_write_access(tcg_env, o->addr1, tcg_constant_i64(16));
/* Begin with the two doublewords swapped... */ /* Begin with the two doublewords swapped... */
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
@ -1211,7 +1211,7 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)
} }
/* Probe write access before actually modifying memory */ /* Probe write access before actually modifying memory */
gen_helper_probe_write_access(cpu_env, o->addr1, gen_helper_probe_write_access(tcg_env, o->addr1,
tcg_constant_i64((v3 - v1 + 1) * 16)); tcg_constant_i64((v3 - v1 + 1) * 16));
tmp = tcg_temp_new_i64(); tmp = tcg_temp_new_i64();
@ -1236,8 +1236,8 @@ static DisasJumpType op_vstl(DisasContext *s, DisasOps *o)
/* convert highest index into an actual length */ /* convert highest index into an actual length */
tcg_gen_addi_i64(o->in2, o->in2, 1); tcg_gen_addi_i64(o->in2, o->in2, 1);
tcg_gen_addi_ptr(a0, cpu_env, v1_offs); tcg_gen_addi_ptr(a0, tcg_env, v1_offs);
gen_helper_vstl(cpu_env, a0, o->addr1, o->in2); gen_helper_vstl(tcg_env, a0, o->addr1, o->in2);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -2479,7 +2479,7 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
static DisasJumpType op_vtm(DisasContext *s, DisasOps *o) static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
{ {
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
cpu_env, 0, gen_helper_gvec_vtm); tcg_env, 0, gen_helper_gvec_vtm);
set_cc_static(s); set_cc_static(s);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -2505,7 +2505,7 @@ static DisasJumpType op_vfae(DisasContext *s, DisasOps *o)
if (extract32(m5, 0, 1)) { if (extract32(m5, 0, 1)) {
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), cpu_env, m5, g_cc[es]); get_field(s, v3), tcg_env, m5, g_cc[es]);
set_cc_static(s); set_cc_static(s);
} else { } else {
gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
@ -2536,7 +2536,7 @@ static DisasJumpType op_vfee(DisasContext *s, DisasOps *o)
if (extract32(m5, 0, 1)) { if (extract32(m5, 0, 1)) {
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), cpu_env, m5, g_cc[es]); get_field(s, v3), tcg_env, m5, g_cc[es]);
set_cc_static(s); set_cc_static(s);
} else { } else {
gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
@ -2567,7 +2567,7 @@ static DisasJumpType op_vfene(DisasContext *s, DisasOps *o)
if (extract32(m5, 0, 1)) { if (extract32(m5, 0, 1)) {
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), cpu_env, m5, g_cc[es]); get_field(s, v3), tcg_env, m5, g_cc[es]);
set_cc_static(s); set_cc_static(s);
} else { } else {
gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
@ -2598,7 +2598,7 @@ static DisasJumpType op_vistr(DisasContext *s, DisasOps *o)
if (extract32(m5, 0, 1)) { if (extract32(m5, 0, 1)) {
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
cpu_env, 0, g_cc[es]); tcg_env, 0, g_cc[es]);
set_cc_static(s); set_cc_static(s);
} else { } else {
gen_gvec_2_ool(get_field(s, v1), get_field(s, v2), 0, gen_gvec_2_ool(get_field(s, v1), get_field(s, v2), 0,
@ -2641,11 +2641,11 @@ static DisasJumpType op_vstrc(DisasContext *s, DisasOps *o)
if (extract32(m6, 2, 1)) { if (extract32(m6, 2, 1)) {
gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), get_field(s, v4), get_field(s, v3), get_field(s, v4),
cpu_env, m6, g_cc_rt[es]); tcg_env, m6, g_cc_rt[es]);
} else { } else {
gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), get_field(s, v4), get_field(s, v3), get_field(s, v4),
cpu_env, m6, g_cc[es]); tcg_env, m6, g_cc[es]);
} }
set_cc_static(s); set_cc_static(s);
} else { } else {
@ -2682,7 +2682,7 @@ static DisasJumpType op_vstrs(DisasContext *s, DisasOps *o)
gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), get_field(s, v4), get_field(s, v3), get_field(s, v4),
cpu_env, 0, fns[es][zs]); tcg_env, 0, fns[es][zs]);
set_cc_static(s); set_cc_static(s);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -2780,7 +2780,7 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
} }
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), cpu_env, m5, fn); get_field(s, v3), tcg_env, m5, fn);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -2822,7 +2822,7 @@ static DisasJumpType op_wfc(DisasContext *s, DisasOps *o)
return DISAS_NORETURN; return DISAS_NORETURN;
} }
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, 0, fn); gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, 0, fn);
set_cc_static(s); set_cc_static(s);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -2893,7 +2893,7 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
} }
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3), gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3),
cpu_env, m5, fn); tcg_env, m5, fn);
if (cs) { if (cs) {
set_cc_static(s); set_cc_static(s);
} }
@ -3007,7 +3007,7 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
return DISAS_NORETURN; return DISAS_NORETURN;
} }
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env,
deposit32(m4, 4, 4, erm), fn); deposit32(m4, 4, 4, erm), fn);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -3036,7 +3036,7 @@ static DisasJumpType op_vfll(DisasContext *s, DisasOps *o)
return DISAS_NORETURN; return DISAS_NORETURN;
} }
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, m4, fn); gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, m4, fn);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -3080,7 +3080,7 @@ static DisasJumpType op_vfmax(DisasContext *s, DisasOps *o)
} }
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3), gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3),
cpu_env, deposit32(m5, 4, 4, m6), fn); tcg_env, deposit32(m5, 4, 4, m6), fn);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -3169,7 +3169,7 @@ static DisasJumpType op_vfma(DisasContext *s, DisasOps *o)
} }
gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), get_field(s, v4), cpu_env, m5, fn); get_field(s, v3), get_field(s, v4), tcg_env, m5, fn);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -3291,7 +3291,7 @@ static DisasJumpType op_vfsq(DisasContext *s, DisasOps *o)
return DISAS_NORETURN; return DISAS_NORETURN;
} }
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, m4, fn); gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, m4, fn);
return DISAS_NEXT; return DISAS_NEXT;
} }
@ -3325,7 +3325,7 @@ static DisasJumpType op_vftci(DisasContext *s, DisasOps *o)
return DISAS_NORETURN; return DISAS_NORETURN;
} }
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env,
deposit32(m5, 4, 12, i3), fn); deposit32(m5, 4, 12, i3), fn);
set_cc_static(s); set_cc_static(s);
return DISAS_NEXT; return DISAS_NEXT;

124
target/sh4/translate.c
View File

@ -96,63 +96,63 @@ void sh4_translate_init(void)
}; };
for (i = 0; i < 24; i++) { for (i = 0; i < 24; i++) {
cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env, cpu_gregs[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, gregs[i]), offsetof(CPUSH4State, gregs[i]),
gregnames[i]); gregnames[i]);
} }
memcpy(cpu_gregs + 24, cpu_gregs + 8, 8 * sizeof(TCGv)); memcpy(cpu_gregs + 24, cpu_gregs + 8, 8 * sizeof(TCGv));
cpu_pc = tcg_global_mem_new_i32(cpu_env, cpu_pc = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, pc), "PC"); offsetof(CPUSH4State, pc), "PC");
cpu_sr = tcg_global_mem_new_i32(cpu_env, cpu_sr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, sr), "SR"); offsetof(CPUSH4State, sr), "SR");
cpu_sr_m = tcg_global_mem_new_i32(cpu_env, cpu_sr_m = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, sr_m), "SR_M"); offsetof(CPUSH4State, sr_m), "SR_M");
cpu_sr_q = tcg_global_mem_new_i32(cpu_env, cpu_sr_q = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, sr_q), "SR_Q"); offsetof(CPUSH4State, sr_q), "SR_Q");
cpu_sr_t = tcg_global_mem_new_i32(cpu_env, cpu_sr_t = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, sr_t), "SR_T"); offsetof(CPUSH4State, sr_t), "SR_T");
cpu_ssr = tcg_global_mem_new_i32(cpu_env, cpu_ssr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, ssr), "SSR"); offsetof(CPUSH4State, ssr), "SSR");
cpu_spc = tcg_global_mem_new_i32(cpu_env, cpu_spc = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, spc), "SPC"); offsetof(CPUSH4State, spc), "SPC");
cpu_gbr = tcg_global_mem_new_i32(cpu_env, cpu_gbr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, gbr), "GBR"); offsetof(CPUSH4State, gbr), "GBR");
cpu_vbr = tcg_global_mem_new_i32(cpu_env, cpu_vbr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, vbr), "VBR"); offsetof(CPUSH4State, vbr), "VBR");
cpu_sgr = tcg_global_mem_new_i32(cpu_env, cpu_sgr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, sgr), "SGR"); offsetof(CPUSH4State, sgr), "SGR");
cpu_dbr = tcg_global_mem_new_i32(cpu_env, cpu_dbr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, dbr), "DBR"); offsetof(CPUSH4State, dbr), "DBR");
cpu_mach = tcg_global_mem_new_i32(cpu_env, cpu_mach = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, mach), "MACH"); offsetof(CPUSH4State, mach), "MACH");
cpu_macl = tcg_global_mem_new_i32(cpu_env, cpu_macl = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, macl), "MACL"); offsetof(CPUSH4State, macl), "MACL");
cpu_pr = tcg_global_mem_new_i32(cpu_env, cpu_pr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, pr), "PR"); offsetof(CPUSH4State, pr), "PR");
cpu_fpscr = tcg_global_mem_new_i32(cpu_env, cpu_fpscr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, fpscr), "FPSCR"); offsetof(CPUSH4State, fpscr), "FPSCR");
cpu_fpul = tcg_global_mem_new_i32(cpu_env, cpu_fpul = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, fpul), "FPUL"); offsetof(CPUSH4State, fpul), "FPUL");
cpu_flags = tcg_global_mem_new_i32(cpu_env, cpu_flags = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, flags), "_flags_"); offsetof(CPUSH4State, flags), "_flags_");
cpu_delayed_pc = tcg_global_mem_new_i32(cpu_env, cpu_delayed_pc = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, delayed_pc), offsetof(CPUSH4State, delayed_pc),
"_delayed_pc_"); "_delayed_pc_");
cpu_delayed_cond = tcg_global_mem_new_i32(cpu_env, cpu_delayed_cond = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, offsetof(CPUSH4State,
delayed_cond), delayed_cond),
"_delayed_cond_"); "_delayed_cond_");
cpu_lock_addr = tcg_global_mem_new_i32(cpu_env, cpu_lock_addr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, lock_addr), offsetof(CPUSH4State, lock_addr),
"_lock_addr_"); "_lock_addr_");
cpu_lock_value = tcg_global_mem_new_i32(cpu_env, cpu_lock_value = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, lock_value), offsetof(CPUSH4State, lock_value),
"_lock_value_"); "_lock_value_");
for (i = 0; i < 32; i++) for (i = 0; i < 32; i++)
cpu_fregs[i] = tcg_global_mem_new_i32(cpu_env, cpu_fregs[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, fregs[i]), offsetof(CPUSH4State, fregs[i]),
fregnames[i]); fregnames[i]);
} }
@ -416,7 +416,7 @@ static void _decode_opc(DisasContext * ctx)
if (opcode != 0x0093 /* ocbi */ if (opcode != 0x0093 /* ocbi */
&& opcode != 0x00c3 /* movca.l */) && opcode != 0x00c3 /* movca.l */)
{ {
gen_helper_discard_movcal_backup(cpu_env); gen_helper_discard_movcal_backup(tcg_env);
ctx->has_movcal = 0; ctx->has_movcal = 0;
} }
} }
@ -449,7 +449,7 @@ static void _decode_opc(DisasContext * ctx)
return; return;
case 0x0038: /* ldtlb */ case 0x0038: /* ldtlb */
CHECK_PRIVILEGED CHECK_PRIVILEGED
gen_helper_ldtlb(cpu_env); gen_helper_ldtlb(tcg_env);
return; return;
case 0x002b: /* rte */ case 0x002b: /* rte */
CHECK_PRIVILEGED CHECK_PRIVILEGED
@ -486,7 +486,7 @@ static void _decode_opc(DisasContext * ctx)
case 0x001b: /* sleep */ case 0x001b: /* sleep */
CHECK_PRIVILEGED CHECK_PRIVILEGED
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next + 2); tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next + 2);
gen_helper_sleep(cpu_env); gen_helper_sleep(tcg_env);
return; return;
} }
@ -807,7 +807,7 @@ static void _decode_opc(DisasContext * ctx)
arg1 = tcg_temp_new(); arg1 = tcg_temp_new();
tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx,
MO_TESL | MO_ALIGN); MO_TESL | MO_ALIGN);
gen_helper_macl(cpu_env, arg0, arg1); gen_helper_macl(tcg_env, arg0, arg1);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
} }
@ -821,7 +821,7 @@ static void _decode_opc(DisasContext * ctx)
arg1 = tcg_temp_new(); arg1 = tcg_temp_new();
tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx,
MO_TESL | MO_ALIGN); MO_TESL | MO_ALIGN);
gen_helper_macw(cpu_env, arg0, arg1); gen_helper_macw(tcg_env, arg0, arg1);
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
} }
@ -1069,49 +1069,49 @@ static void _decode_opc(DisasContext * ctx)
gen_load_fpr64(ctx, fp1, B7_4); gen_load_fpr64(ctx, fp1, B7_4);
switch (ctx->opcode & 0xf00f) { switch (ctx->opcode & 0xf00f) {
case 0xf000: /* fadd Rm,Rn */ case 0xf000: /* fadd Rm,Rn */
gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1); gen_helper_fadd_DT(fp0, tcg_env, fp0, fp1);
break; break;
case 0xf001: /* fsub Rm,Rn */ case 0xf001: /* fsub Rm,Rn */
gen_helper_fsub_DT(fp0, cpu_env, fp0, fp1); gen_helper_fsub_DT(fp0, tcg_env, fp0, fp1);
break; break;
case 0xf002: /* fmul Rm,Rn */ case 0xf002: /* fmul Rm,Rn */
gen_helper_fmul_DT(fp0, cpu_env, fp0, fp1); gen_helper_fmul_DT(fp0, tcg_env, fp0, fp1);
break; break;
case 0xf003: /* fdiv Rm,Rn */ case 0xf003: /* fdiv Rm,Rn */
gen_helper_fdiv_DT(fp0, cpu_env, fp0, fp1); gen_helper_fdiv_DT(fp0, tcg_env, fp0, fp1);
break; break;
case 0xf004: /* fcmp/eq Rm,Rn */ case 0xf004: /* fcmp/eq Rm,Rn */
gen_helper_fcmp_eq_DT(cpu_sr_t, cpu_env, fp0, fp1); gen_helper_fcmp_eq_DT(cpu_sr_t, tcg_env, fp0, fp1);
return; return;
case 0xf005: /* fcmp/gt Rm,Rn */ case 0xf005: /* fcmp/gt Rm,Rn */
gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1); gen_helper_fcmp_gt_DT(cpu_sr_t, tcg_env, fp0, fp1);
return; return;
} }
gen_store_fpr64(ctx, fp0, B11_8); gen_store_fpr64(ctx, fp0, B11_8);
} else { } else {
switch (ctx->opcode & 0xf00f) { switch (ctx->opcode & 0xf00f) {
case 0xf000: /* fadd Rm,Rn */ case 0xf000: /* fadd Rm,Rn */
gen_helper_fadd_FT(FREG(B11_8), cpu_env, gen_helper_fadd_FT(FREG(B11_8), tcg_env,
FREG(B11_8), FREG(B7_4)); FREG(B11_8), FREG(B7_4));
break; break;
case 0xf001: /* fsub Rm,Rn */ case 0xf001: /* fsub Rm,Rn */
gen_helper_fsub_FT(FREG(B11_8), cpu_env, gen_helper_fsub_FT(FREG(B11_8), tcg_env,
FREG(B11_8), FREG(B7_4)); FREG(B11_8), FREG(B7_4));
break; break;
case 0xf002: /* fmul Rm,Rn */ case 0xf002: /* fmul Rm,Rn */
gen_helper_fmul_FT(FREG(B11_8), cpu_env, gen_helper_fmul_FT(FREG(B11_8), tcg_env,
FREG(B11_8), FREG(B7_4)); FREG(B11_8), FREG(B7_4));
break; break;
case 0xf003: /* fdiv Rm,Rn */ case 0xf003: /* fdiv Rm,Rn */
gen_helper_fdiv_FT(FREG(B11_8), cpu_env, gen_helper_fdiv_FT(FREG(B11_8), tcg_env,
FREG(B11_8), FREG(B7_4)); FREG(B11_8), FREG(B7_4));
break; break;
case 0xf004: /* fcmp/eq Rm,Rn */ case 0xf004: /* fcmp/eq Rm,Rn */
gen_helper_fcmp_eq_FT(cpu_sr_t, cpu_env, gen_helper_fcmp_eq_FT(cpu_sr_t, tcg_env,
FREG(B11_8), FREG(B7_4)); FREG(B11_8), FREG(B7_4));
return; return;
case 0xf005: /* fcmp/gt Rm,Rn */ case 0xf005: /* fcmp/gt Rm,Rn */
gen_helper_fcmp_gt_FT(cpu_sr_t, cpu_env, gen_helper_fcmp_gt_FT(cpu_sr_t, tcg_env,
FREG(B11_8), FREG(B7_4)); FREG(B11_8), FREG(B7_4));
return; return;
} }
@ -1121,7 +1121,7 @@ static void _decode_opc(DisasContext * ctx)
case 0xf00e: /* fmac FR0,RM,Rn */ case 0xf00e: /* fmac FR0,RM,Rn */
CHECK_FPU_ENABLED CHECK_FPU_ENABLED
CHECK_FPSCR_PR_0 CHECK_FPSCR_PR_0
gen_helper_fmac_FT(FREG(B11_8), cpu_env, gen_helper_fmac_FT(FREG(B11_8), tcg_env,
FREG(0), FREG(B7_4), FREG(B11_8)); FREG(0), FREG(B7_4), FREG(B11_8));
return; return;
} }
@ -1260,7 +1260,7 @@ static void _decode_opc(DisasContext * ctx)
CHECK_NOT_DELAY_SLOT CHECK_NOT_DELAY_SLOT
gen_save_cpu_state(ctx, true); gen_save_cpu_state(ctx, true);
imm = tcg_constant_i32(B7_0); imm = tcg_constant_i32(B7_0);
gen_helper_trapa(cpu_env, imm); gen_helper_trapa(tcg_env, imm);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
} }
return; return;
@ -1438,7 +1438,7 @@ static void _decode_opc(DisasContext * ctx)
LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED}) LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})
case 0x406a: /* lds Rm,FPSCR */ case 0x406a: /* lds Rm,FPSCR */
CHECK_FPU_ENABLED CHECK_FPU_ENABLED
gen_helper_ld_fpscr(cpu_env, REG(B11_8)); gen_helper_ld_fpscr(tcg_env, REG(B11_8));
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
return; return;
case 0x4066: /* lds.l @Rm+,FPSCR */ case 0x4066: /* lds.l @Rm+,FPSCR */
@ -1448,7 +1448,7 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx, tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx,
MO_TESL | MO_ALIGN); MO_TESL | MO_ALIGN);
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
gen_helper_ld_fpscr(cpu_env, addr); gen_helper_ld_fpscr(tcg_env, addr);
ctx->base.is_jmp = DISAS_STOP; ctx->base.is_jmp = DISAS_STOP;
} }
return; return;
@ -1473,7 +1473,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv val = tcg_temp_new(); TCGv val = tcg_temp_new();
tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx,
MO_TEUL | MO_ALIGN); MO_TEUL | MO_ALIGN);
gen_helper_movcal(cpu_env, REG(B11_8), val); gen_helper_movcal(tcg_env, REG(B11_8), val);
tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx,
MO_TEUL | MO_ALIGN); MO_TEUL | MO_ALIGN);
} }
@ -1560,7 +1560,7 @@ static void _decode_opc(DisasContext * ctx)
return; return;
case 0x0093: /* ocbi @Rn */ case 0x0093: /* ocbi @Rn */
{ {
gen_helper_ocbi(cpu_env, REG(B11_8)); gen_helper_ocbi(tcg_env, REG(B11_8));
} }
return; return;
case 0x00a3: /* ocbp @Rn */ case 0x00a3: /* ocbp @Rn */
@ -1659,11 +1659,11 @@ static void _decode_opc(DisasContext * ctx)
goto do_illegal; goto do_illegal;
} }
fp = tcg_temp_new_i64(); fp = tcg_temp_new_i64();
gen_helper_float_DT(fp, cpu_env, cpu_fpul); gen_helper_float_DT(fp, tcg_env, cpu_fpul);
gen_store_fpr64(ctx, fp, B11_8); gen_store_fpr64(ctx, fp, B11_8);
} }
else { else {
gen_helper_float_FT(FREG(B11_8), cpu_env, cpu_fpul); gen_helper_float_FT(FREG(B11_8), tcg_env, cpu_fpul);
} }
return; return;
case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
@ -1675,10 +1675,10 @@ static void _decode_opc(DisasContext * ctx)
} }
fp = tcg_temp_new_i64(); fp = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp, B11_8); gen_load_fpr64(ctx, fp, B11_8);
gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp); gen_helper_ftrc_DT(cpu_fpul, tcg_env, fp);
} }
else { else {
gen_helper_ftrc_FT(cpu_fpul, cpu_env, FREG(B11_8)); gen_helper_ftrc_FT(cpu_fpul, tcg_env, FREG(B11_8));
} }
return; return;
case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
@ -1697,16 +1697,16 @@ static void _decode_opc(DisasContext * ctx)
} }
TCGv_i64 fp = tcg_temp_new_i64(); TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp, B11_8); gen_load_fpr64(ctx, fp, B11_8);
gen_helper_fsqrt_DT(fp, cpu_env, fp); gen_helper_fsqrt_DT(fp, tcg_env, fp);
gen_store_fpr64(ctx, fp, B11_8); gen_store_fpr64(ctx, fp, B11_8);
} else { } else {
gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); gen_helper_fsqrt_FT(FREG(B11_8), tcg_env, FREG(B11_8));
} }
return; return;
case 0xf07d: /* fsrra FRn */ case 0xf07d: /* fsrra FRn */
CHECK_FPU_ENABLED CHECK_FPU_ENABLED
CHECK_FPSCR_PR_0 CHECK_FPSCR_PR_0
gen_helper_fsrra_FT(FREG(B11_8), cpu_env, FREG(B11_8)); gen_helper_fsrra_FT(FREG(B11_8), tcg_env, FREG(B11_8));
break; break;
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
CHECK_FPU_ENABLED CHECK_FPU_ENABLED
@ -1722,7 +1722,7 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED CHECK_FPU_ENABLED
{ {
TCGv_i64 fp = tcg_temp_new_i64(); TCGv_i64 fp = tcg_temp_new_i64();
gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul); gen_helper_fcnvsd_FT_DT(fp, tcg_env, cpu_fpul);
gen_store_fpr64(ctx, fp, B11_8); gen_store_fpr64(ctx, fp, B11_8);
} }
return; return;
@ -1731,7 +1731,7 @@ static void _decode_opc(DisasContext * ctx)
{ {
TCGv_i64 fp = tcg_temp_new_i64(); TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp, B11_8); gen_load_fpr64(ctx, fp, B11_8);
gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp); gen_helper_fcnvds_DT_FT(cpu_fpul, tcg_env, fp);
} }
return; return;
case 0xf0ed: /* fipr FVm,FVn */ case 0xf0ed: /* fipr FVm,FVn */
@ -1740,7 +1740,7 @@ static void _decode_opc(DisasContext * ctx)
{ {
TCGv m = tcg_constant_i32((ctx->opcode >> 8) & 3); TCGv m = tcg_constant_i32((ctx->opcode >> 8) & 3);
TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3); TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
gen_helper_fipr(cpu_env, m, n); gen_helper_fipr(tcg_env, m, n);
return; return;
} }
break; break;
@ -1752,7 +1752,7 @@ static void _decode_opc(DisasContext * ctx)
goto do_illegal; goto do_illegal;
} }
TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3); TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
gen_helper_ftrv(cpu_env, n); gen_helper_ftrv(tcg_env, n);
return; return;
} }
break; break;
@ -1766,10 +1766,10 @@ static void _decode_opc(DisasContext * ctx)
if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {
do_illegal_slot: do_illegal_slot:
gen_save_cpu_state(ctx, true); gen_save_cpu_state(ctx, true);
gen_helper_raise_slot_illegal_instruction(cpu_env); gen_helper_raise_slot_illegal_instruction(tcg_env);
} else { } else {
gen_save_cpu_state(ctx, true); gen_save_cpu_state(ctx, true);
gen_helper_raise_illegal_instruction(cpu_env); gen_helper_raise_illegal_instruction(tcg_env);
} }
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return; return;
@ -1777,9 +1777,9 @@ static void _decode_opc(DisasContext * ctx)
do_fpu_disabled: do_fpu_disabled:
gen_save_cpu_state(ctx, true); gen_save_cpu_state(ctx, true);
if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {
gen_helper_raise_slot_fpu_disable(cpu_env); gen_helper_raise_slot_fpu_disable(tcg_env);
} else { } else {
gen_helper_raise_fpu_disable(cpu_env); gen_helper_raise_fpu_disable(tcg_env);
} }
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
return; return;
@ -2153,7 +2153,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
cpu_exec_step_atomic holding the exclusive lock. */ cpu_exec_step_atomic holding the exclusive lock. */
ctx->envflags |= TB_FLAG_GUSA_EXCLUSIVE; ctx->envflags |= TB_FLAG_GUSA_EXCLUSIVE;
gen_save_cpu_state(ctx, false); gen_save_cpu_state(ctx, false);
gen_helper_exclusive(cpu_env); gen_helper_exclusive(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
/* We're not executing an instruction, but we must report one for the /* We're not executing an instruction, but we must report one for the

328
target/sparc/translate.c
View File

File diff suppressed because it is too large Load Diff

226
target/tricore/translate.c
View File

@ -132,7 +132,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#define gen_helper_1arg(name, arg) do { \ #define gen_helper_1arg(name, arg) do { \
TCGv_i32 helper_tmp = tcg_constant_i32(arg); \ TCGv_i32 helper_tmp = tcg_constant_i32(arg); \
gen_helper_##name(cpu_env, helper_tmp); \ gen_helper_##name(tcg_env, helper_tmp); \
} while (0) } while (0)
#define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
@ -191,7 +191,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
TCGv_i64 ret = tcg_temp_new_i64(); \ TCGv_i64 ret = tcg_temp_new_i64(); \
\ \
gen_helper_##name(ret, cpu_env, arg1, arg2); \ gen_helper_##name(ret, tcg_env, arg1, arg2); \
tcg_gen_extr_i64_i32(rl, rh, ret); \ tcg_gen_extr_i64_i32(rl, rh, ret); \
} while (0) } while (0)
@ -341,7 +341,7 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
#define R(ADDRESS, REG, FEATURE) \ #define R(ADDRESS, REG, FEATURE) \
case ADDRESS: \ case ADDRESS: \
if (has_feature(ctx, FEATURE)) { \ if (has_feature(ctx, FEATURE)) { \
tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ tcg_gen_ld_tl(ret, tcg_env, offsetof(CPUTriCoreState, REG)); \
} \ } \
break; break;
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
@ -350,7 +350,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
{ {
/* since we're caching PSW make this a special case */ /* since we're caching PSW make this a special case */
if (offset == 0xfe04) { if (offset == 0xfe04) {
gen_helper_psw_read(ret, cpu_env); gen_helper_psw_read(ret, tcg_env);
} else { } else {
switch (offset) { switch (offset) {
#include "csfr.h.inc" #include "csfr.h.inc"
@ -366,7 +366,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
case ADDRESS: \ case ADDRESS: \
if (has_feature(ctx, FEATURE)) { \ if (has_feature(ctx, FEATURE)) { \
tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ tcg_gen_st_tl(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \
} \ } \
break; break;
/* Endinit protected registers /* Endinit protected registers
@ -380,7 +380,7 @@ static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
if (ctx->priv == TRICORE_PRIV_SM) { if (ctx->priv == TRICORE_PRIV_SM) {
/* since we're caching PSW make this a special case */ /* since we're caching PSW make this a special case */
if (offset == 0xfe04) { if (offset == 0xfe04) {
gen_helper_psw_write(cpu_env, r1); gen_helper_psw_write(tcg_env, r1);
ctx->base.is_jmp = DISAS_EXIT_UPDATE; ctx->base.is_jmp = DISAS_EXIT_UPDATE;
} else { } else {
switch (offset) { switch (offset) {
@ -788,7 +788,7 @@ gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_shli_i64(temp64, temp64, 16); tcg_gen_shli_i64(temp64, temp64, 16);
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
} }
@ -843,7 +843,7 @@ gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
break; break;
} }
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
} }
@ -867,7 +867,7 @@ gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break; break;
} }
gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); gen_helper_addr_h(ret, tcg_env, temp64, r1_low, r1_high);
} }
static inline void static inline void
@ -904,7 +904,7 @@ gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
} }
tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16); tcg_gen_shli_tl(temp, r1, 16);
gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); gen_helper_addsur_h(ret, tcg_env, temp64, temp, temp2);
} }
@ -928,7 +928,7 @@ gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break; break;
} }
gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); gen_helper_addr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high);
} }
static inline void static inline void
@ -965,21 +965,21 @@ gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
} }
tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16); tcg_gen_shli_tl(temp, r1, 16);
gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); gen_helper_addsur_h_ssov(ret, tcg_env, temp64, temp, temp2);
} }
static inline void static inline void
gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{ {
TCGv t_n = tcg_constant_i32(n); TCGv t_n = tcg_constant_i32(n);
gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n); gen_helper_maddr_q(ret, tcg_env, r1, r2, r3, t_n);
} }
static inline void static inline void
gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{ {
TCGv t_n = tcg_constant_i32(n); TCGv t_n = tcg_constant_i32(n);
gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n); gen_helper_maddr_q_ssov(ret, tcg_env, r1, r2, r3, t_n);
} }
static inline void static inline void
@ -1115,7 +1115,7 @@ gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_shli_i64(t2, t2, 16); tcg_gen_shli_i64(t2, t2, 16);
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
gen_helper_add64_ssov(t1, cpu_env, t1, t2); gen_helper_add64_ssov(t1, tcg_env, t1, t2);
tcg_gen_extr_i64_i32(rl, rh, t1); tcg_gen_extr_i64_i32(rl, rh, t1);
} }
@ -1182,7 +1182,7 @@ gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
tcg_gen_mul_i64(t2, t2, t3); tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_sari_i64(t2, t2, up_shift - n); tcg_gen_sari_i64(t2, t2, up_shift - n);
gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); gen_helper_madd32_q_add_ssov(ret, tcg_env, t1, t2);
} }
static inline void static inline void
@ -1193,7 +1193,7 @@ gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv t_n = tcg_constant_i32(n); TCGv t_n = tcg_constant_i32(n);
tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); gen_helper_madd64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n);
tcg_gen_extr_i64_i32(rl, rh, r1); tcg_gen_extr_i64_i32(rl, rh, r1);
} }
@ -1638,7 +1638,7 @@ gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
break; break;
} }
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
} }
@ -1662,7 +1662,7 @@ gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break; break;
} }
gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); gen_helper_subr_h(ret, tcg_env, temp64, r1_low, r1_high);
} }
static inline void static inline void
@ -1696,7 +1696,7 @@ gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break; break;
} }
gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); gen_helper_subr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high);
} }
static inline void static inline void
@ -1714,14 +1714,14 @@ static inline void
gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{ {
TCGv temp = tcg_constant_i32(n); TCGv temp = tcg_constant_i32(n);
gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); gen_helper_msubr_q(ret, tcg_env, r1, r2, r3, temp);
} }
static inline void static inline void
gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{ {
TCGv temp = tcg_constant_i32(n); TCGv temp = tcg_constant_i32(n);
gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); gen_helper_msubr_q_ssov(ret, tcg_env, r1, r2, r3, temp);
} }
static inline void static inline void
@ -1848,7 +1848,7 @@ gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_shli_i64(t2, t2, 16); tcg_gen_shli_i64(t2, t2, 16);
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
gen_helper_sub64_ssov(t1, cpu_env, t1, t2); gen_helper_sub64_ssov(t1, tcg_env, t1, t2);
tcg_gen_extr_i64_i32(rl, rh, t1); tcg_gen_extr_i64_i32(rl, rh, t1);
} }
@ -1920,7 +1920,7 @@ gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
tcg_gen_sari_i64(t3, t2, up_shift - n); tcg_gen_sari_i64(t3, t2, up_shift - n);
tcg_gen_add_i64(t3, t3, t4); tcg_gen_add_i64(t3, t3, t4);
gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); gen_helper_msub32_q_sub_ssov(ret, tcg_env, t1, t3);
} }
static inline void static inline void
@ -1931,7 +1931,7 @@ gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv t_n = tcg_constant_i32(n); TCGv t_n = tcg_constant_i32(n);
tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); gen_helper_msub64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n);
tcg_gen_extr_i64_i32(rl, rh, r1); tcg_gen_extr_i64_i32(rl, rh, r1);
} }
@ -2018,7 +2018,7 @@ gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
} }
tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16); tcg_gen_shli_tl(temp, r1, 16);
gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); gen_helper_subadr_h(ret, tcg_env, temp64, temp, temp2);
} }
static inline void static inline void
@ -2084,7 +2084,7 @@ gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_shli_i64(temp64, temp64, 16); tcg_gen_shli_i64(temp64, temp64, 16);
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
} }
@ -2111,7 +2111,7 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
} }
tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16); tcg_gen_shli_tl(temp, r1, 16);
gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); gen_helper_subadr_h_ssov(ret, tcg_env, temp64, temp, temp2);
} }
static inline void gen_abs(TCGv ret, TCGv r1) static inline void gen_abs(TCGv ret, TCGv r1)
@ -2164,7 +2164,7 @@ static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
{ {
TCGv temp = tcg_constant_i32(con); TCGv temp = tcg_constant_i32(con);
gen_helper_absdif_ssov(ret, cpu_env, r1, temp); gen_helper_absdif_ssov(ret, tcg_env, r1, temp);
} }
static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
@ -2238,26 +2238,26 @@ static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
{ {
TCGv temp = tcg_constant_i32(con); TCGv temp = tcg_constant_i32(con);
gen_helper_mul_ssov(ret, cpu_env, r1, temp); gen_helper_mul_ssov(ret, tcg_env, r1, temp);
} }
static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
{ {
TCGv temp = tcg_constant_i32(con); TCGv temp = tcg_constant_i32(con);
gen_helper_mul_suov(ret, cpu_env, r1, temp); gen_helper_mul_suov(ret, tcg_env, r1, temp);
} }
/* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{ {
TCGv temp = tcg_constant_i32(con); TCGv temp = tcg_constant_i32(con);
gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); gen_helper_madd32_ssov(ret, tcg_env, r1, r2, temp);
} }
static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{ {
TCGv temp = tcg_constant_i32(con); TCGv temp = tcg_constant_i32(con);
gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); gen_helper_madd32_suov(ret, tcg_env, r1, r2, temp);
} }
static void static void
@ -2371,7 +2371,7 @@ gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
{ {
TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); gen_helper_madd64_ssov(temp64, tcg_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
} }
@ -2389,7 +2389,7 @@ gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
{ {
TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); gen_helper_madd64_suov(temp64, tcg_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
} }
@ -2404,13 +2404,13 @@ gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{ {
TCGv temp = tcg_constant_i32(con); TCGv temp = tcg_constant_i32(con);
gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); gen_helper_msub32_ssov(ret, tcg_env, r1, r2, temp);
} }
static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{ {
TCGv temp = tcg_constant_i32(con); TCGv temp = tcg_constant_i32(con);
gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); gen_helper_msub32_suov(ret, tcg_env, r1, r2, temp);
} }
static inline void static inline void
@ -2419,7 +2419,7 @@ gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
{ {
TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); gen_helper_msub64_ssov(temp64, tcg_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
} }
@ -2437,7 +2437,7 @@ gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
{ {
TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); gen_helper_msub64_suov(temp64, tcg_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
} }
@ -2542,7 +2542,7 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
static void gen_shas(TCGv ret, TCGv r1, TCGv r2) static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
{ {
gen_helper_sha_ssov(ret, cpu_env, r1, r2); gen_helper_sha_ssov(ret, tcg_env, r1, r2);
} }
static void gen_shasi(TCGv ret, TCGv r1, int32_t con) static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
@ -2595,29 +2595,29 @@ static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
{ {
gen_helper_add_ssov(ret, cpu_env, r1, r2); gen_helper_add_ssov(ret, tcg_env, r1, r2);
} }
static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
{ {
TCGv temp = tcg_constant_i32(con); TCGv temp = tcg_constant_i32(con);
gen_helper_add_ssov(ret, cpu_env, r1, temp); gen_helper_add_ssov(ret, tcg_env, r1, temp);
} }
static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
{ {
TCGv temp = tcg_constant_i32(con); TCGv temp = tcg_constant_i32(con);
gen_helper_add_suov(ret, cpu_env, r1, temp); gen_helper_add_suov(ret, tcg_env, r1, temp);
} }
static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
{ {
gen_helper_sub_ssov(ret, cpu_env, r1, r2); gen_helper_sub_ssov(ret, tcg_env, r1, r2);
} }
static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
{ {
gen_helper_sub_suov(ret, cpu_env, r1, r2); gen_helper_sub_suov(ret, tcg_env, r1, r2);
} }
static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
@ -2767,9 +2767,9 @@ gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
TCGv_i64 ret = tcg_temp_new_i64(); TCGv_i64 ret = tcg_temp_new_i64();
if (!has_feature(ctx, TRICORE_FEATURE_131)) { if (!has_feature(ctx, TRICORE_FEATURE_131)) {
gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); gen_helper_dvinit_b_13(ret, tcg_env, r1, r2);
} else { } else {
gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); gen_helper_dvinit_b_131(ret, tcg_env, r1, r2);
} }
tcg_gen_extr_i64_i32(rl, rh, ret); tcg_gen_extr_i64_i32(rl, rh, ret);
} }
@ -2780,9 +2780,9 @@ gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
TCGv_i64 ret = tcg_temp_new_i64(); TCGv_i64 ret = tcg_temp_new_i64();
if (!has_feature(ctx, TRICORE_FEATURE_131)) { if (!has_feature(ctx, TRICORE_FEATURE_131)) {
gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); gen_helper_dvinit_h_13(ret, tcg_env, r1, r2);
} else { } else {
gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); gen_helper_dvinit_h_131(ret, tcg_env, r1, r2);
} }
tcg_gen_extr_i64_i32(rl, rh, ret); tcg_gen_extr_i64_i32(rl, rh, ret);
} }
@ -2841,7 +2841,7 @@ static void generate_trap(DisasContext *ctx, int class, int tin)
TCGv_i32 tintemp = tcg_constant_i32(tin); TCGv_i32 tintemp = tcg_constant_i32(tin);
gen_save_pc(ctx->base.pc_next); gen_save_pc(ctx->base.pc_next);
gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); gen_helper_raise_exception_sync(tcg_env, classtemp, tintemp);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
} }
@ -2996,7 +2996,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
break; break;
case OPC2_32_SYS_RET: case OPC2_32_SYS_RET:
case OPC2_16_SR_RET: case OPC2_16_SR_RET:
gen_helper_ret(cpu_env); gen_helper_ret(tcg_env);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
break; break;
/* B-format */ /* B-format */
@ -3493,7 +3493,7 @@ static void decode_sr_system(DisasContext *ctx)
gen_compute_branch(ctx, op2, 0, 0, 0, 0); gen_compute_branch(ctx, op2, 0, 0, 0, 0);
break; break;
case OPC2_16_SR_RFE: case OPC2_16_SR_RFE:
gen_helper_rfe(cpu_env); gen_helper_rfe(tcg_env);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
break; break;
case OPC2_16_SR_DEBUG: case OPC2_16_SR_DEBUG:
@ -4741,7 +4741,7 @@ static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx)
switch (op2) { switch (op2) {
case OPC2_32_BO_LDLCX_SHORTOFF: case OPC2_32_BO_LDLCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_helper_ldlcx(cpu_env, temp); gen_helper_ldlcx(tcg_env, temp);
break; break;
case OPC2_32_BO_LDMST_SHORTOFF: case OPC2_32_BO_LDMST_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
@ -4757,18 +4757,18 @@ static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx)
break; break;
case OPC2_32_BO_LDUCX_SHORTOFF: case OPC2_32_BO_LDUCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_helper_lducx(cpu_env, temp); gen_helper_lducx(tcg_env, temp);
break; break;
case OPC2_32_BO_LEA_SHORTOFF: case OPC2_32_BO_LEA_SHORTOFF:
tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
break; break;
case OPC2_32_BO_STLCX_SHORTOFF: case OPC2_32_BO_STLCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_helper_stlcx(cpu_env, temp); gen_helper_stlcx(tcg_env, temp);
break; break;
case OPC2_32_BO_STUCX_SHORTOFF: case OPC2_32_BO_STUCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_helper_stucx(cpu_env, temp); gen_helper_stucx(tcg_env, temp);
break; break;
case OPC2_32_BO_SWAP_W_SHORTOFF: case OPC2_32_BO_SWAP_W_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
@ -5593,44 +5593,44 @@ static void decode_rr_accumulator(DisasContext *ctx)
gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ABS_B: case OPC2_32_RR_ABS_B:
gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); gen_helper_abs_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ABS_H: case OPC2_32_RR_ABS_H:
gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); gen_helper_abs_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ABSDIF: case OPC2_32_RR_ABSDIF:
gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ABSDIF_B: case OPC2_32_RR_ABSDIF_B:
gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_absdif_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ABSDIF_H: case OPC2_32_RR_ABSDIF_H:
gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_absdif_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ABSDIFS: case OPC2_32_RR_ABSDIFS:
gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_absdif_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ABSDIFS_H: case OPC2_32_RR_ABSDIFS_H:
gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_absdif_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ABSS: case OPC2_32_RR_ABSS:
gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); gen_helper_abs_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ABSS_H: case OPC2_32_RR_ABSS_H:
gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); gen_helper_abs_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ADD: case OPC2_32_RR_ADD:
gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ADD_B: case OPC2_32_RR_ADD_B:
gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_helper_add_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ADD_H: case OPC2_32_RR_ADD_H:
gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_helper_add_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ADDC: case OPC2_32_RR_ADDC:
gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
@ -5639,15 +5639,15 @@ static void decode_rr_accumulator(DisasContext *ctx)
gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ADDS_H: case OPC2_32_RR_ADDS_H:
gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_add_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ADDS_HU: case OPC2_32_RR_ADDS_HU:
gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_add_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ADDS_U: case OPC2_32_RR_ADDS_U:
gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_add_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_ADDX: case OPC2_32_RR_ADDX:
@ -5865,10 +5865,10 @@ static void decode_rr_accumulator(DisasContext *ctx)
gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_SUB_B: case OPC2_32_RR_SUB_B:
gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_helper_sub_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_SUB_H: case OPC2_32_RR_SUB_H:
gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_helper_sub_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_SUBC: case OPC2_32_RR_SUBC:
gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
@ -5880,11 +5880,11 @@ static void decode_rr_accumulator(DisasContext *ctx)
gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_SUBS_H: case OPC2_32_RR_SUBS_H:
gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_sub_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_SUBS_HU: case OPC2_32_RR_SUBS_HU:
gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_sub_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_SUBX: case OPC2_32_RR_SUBX:
@ -5974,7 +5974,7 @@ static void decode_rr_logical_shift(DisasContext *ctx)
gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_SHA: case OPC2_32_RR_SHA:
gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_helper_sha(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_SHA_H: case OPC2_32_RR_SHA_H:
gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
@ -6258,55 +6258,55 @@ static void decode_rr_divide(DisasContext *ctx)
} }
break; break;
case OPC2_32_RR_MUL_F: case OPC2_32_RR_MUL_F:
gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_helper_fmul(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_DIV_F: case OPC2_32_RR_DIV_F:
gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_helper_fdiv(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_FTOHP: case OPC2_32_RR_FTOHP:
if (has_feature(ctx, TRICORE_FEATURE_162)) { if (has_feature(ctx, TRICORE_FEATURE_162)) {
gen_helper_ftohp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); gen_helper_ftohp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
} else { } else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
} }
break; break;
case OPC2_32_RR_HPTOF: case OPC2_32_RR_HPTOF:
if (has_feature(ctx, TRICORE_FEATURE_162)) { if (has_feature(ctx, TRICORE_FEATURE_162)) {
gen_helper_hptof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); gen_helper_hptof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
} else { } else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
} }
break; break;
case OPC2_32_RR_CMP_F: case OPC2_32_RR_CMP_F:
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); gen_helper_fcmp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR_FTOI: case OPC2_32_RR_FTOI:
gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); gen_helper_ftoi(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break; break;
case OPC2_32_RR_ITOF: case OPC2_32_RR_ITOF:
gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); gen_helper_itof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break; break;
case OPC2_32_RR_FTOU: case OPC2_32_RR_FTOU:
gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); gen_helper_ftou(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break; break;
case OPC2_32_RR_FTOUZ: case OPC2_32_RR_FTOUZ:
if (has_feature(ctx, TRICORE_FEATURE_131)) { if (has_feature(ctx, TRICORE_FEATURE_131)) {
gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); gen_helper_ftouz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
} else { } else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
} }
break; break;
case OPC2_32_RR_UPDFL: case OPC2_32_RR_UPDFL:
gen_helper_updfl(cpu_env, cpu_gpr_d[r1]); gen_helper_updfl(tcg_env, cpu_gpr_d[r1]);
break; break;
case OPC2_32_RR_UTOF: case OPC2_32_RR_UTOF:
gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); gen_helper_utof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break; break;
case OPC2_32_RR_FTOIZ: case OPC2_32_RR_FTOIZ:
gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); gen_helper_ftoiz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break; break;
case OPC2_32_RR_QSEED_F: case OPC2_32_RR_QSEED_F:
gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); gen_helper_qseed(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break; break;
default: default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@ -6507,7 +6507,7 @@ static void decode_rr2_mul(DisasContext *ctx)
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR2_MULS_32: case OPC2_32_RR2_MULS_32:
gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_mul_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR2_MUL_U_64: case OPC2_32_RR2_MUL_U_64:
@ -6516,7 +6516,7 @@ static void decode_rr2_mul(DisasContext *ctx)
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
case OPC2_32_RR2_MULS_U_32: case OPC2_32_RR2_MULS_U_32:
gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], gen_helper_mul_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]); cpu_gpr_d[r2]);
break; break;
default: default:
@ -6705,17 +6705,17 @@ static void decode_rrr_divide(DisasContext *ctx)
} }
break; break;
case OPC2_32_RRR_ADD_F: case OPC2_32_RRR_ADD_F:
gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); gen_helper_fadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break; break;
case OPC2_32_RRR_SUB_F: case OPC2_32_RRR_SUB_F:
gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); gen_helper_fsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break; break;
case OPC2_32_RRR_MADD_F: case OPC2_32_RRR_MADD_F:
gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], gen_helper_fmadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r3]); cpu_gpr_d[r2], cpu_gpr_d[r3]);
break; break;
case OPC2_32_RRR_MSUB_F: case OPC2_32_RRR_MSUB_F:
gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], gen_helper_fmsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r3]); cpu_gpr_d[r2], cpu_gpr_d[r3]);
break; break;
default: default:
@ -6746,7 +6746,7 @@ static void decode_rrr2_madd(DisasContext *ctx)
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RRR2_MADDS_32: case OPC2_32_RRR2_MADDS_32:
gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], gen_helper_madd32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]); cpu_gpr_d[r3], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RRR2_MADDS_64: case OPC2_32_RRR2_MADDS_64:
@ -6762,7 +6762,7 @@ static void decode_rrr2_madd(DisasContext *ctx)
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RRR2_MADDS_U_32: case OPC2_32_RRR2_MADDS_U_32:
gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], gen_helper_madd32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]); cpu_gpr_d[r3], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RRR2_MADDS_U_64: case OPC2_32_RRR2_MADDS_U_64:
@ -6799,7 +6799,7 @@ static void decode_rrr2_msub(DisasContext *ctx)
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RRR2_MSUBS_32: case OPC2_32_RRR2_MSUBS_32:
gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], gen_helper_msub32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]); cpu_gpr_d[r3], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RRR2_MSUBS_64: case OPC2_32_RRR2_MSUBS_64:
@ -6815,7 +6815,7 @@ static void decode_rrr2_msub(DisasContext *ctx)
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RRR2_MSUBS_U_32: case OPC2_32_RRR2_MSUBS_U_32:
gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], gen_helper_msub32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]); cpu_gpr_d[r3], cpu_gpr_d[r2]);
break; break;
case OPC2_32_RRR2_MSUBS_U_64: case OPC2_32_RRR2_MSUBS_U_64:
@ -7968,7 +7968,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
gen_fret(ctx); gen_fret(ctx);
break; break;
case OPC2_32_SYS_RFE: case OPC2_32_SYS_RFE:
gen_helper_rfe(cpu_env); gen_helper_rfe(tcg_env);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
break; break;
case OPC2_32_SYS_RFM: case OPC2_32_SYS_RFM:
@ -7976,10 +7976,10 @@ static void decode_sys_interrupts(DisasContext *ctx)
tmp = tcg_temp_new(); tmp = tcg_temp_new();
l1 = gen_new_label(); l1 = gen_new_label();
tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR)); tcg_gen_ld32u_tl(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR));
tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
gen_helper_rfm(cpu_env); gen_helper_rfm(tcg_env);
gen_set_label(l1); gen_set_label(l1);
ctx->base.is_jmp = DISAS_EXIT; ctx->base.is_jmp = DISAS_EXIT;
} else { } else {
@ -7987,10 +7987,10 @@ static void decode_sys_interrupts(DisasContext *ctx)
} }
break; break;
case OPC2_32_SYS_RSLCX: case OPC2_32_SYS_RSLCX:
gen_helper_rslcx(cpu_env); gen_helper_rslcx(tcg_env);
break; break;
case OPC2_32_SYS_SVLCX: case OPC2_32_SYS_SVLCX:
gen_helper_svlcx(cpu_env); gen_helper_svlcx(tcg_env);
break; break;
case OPC2_32_SYS_RESTORE: case OPC2_32_SYS_RESTORE:
if (has_feature(ctx, TRICORE_FEATURE_16)) { if (has_feature(ctx, TRICORE_FEATURE_16)) {
@ -8506,13 +8506,13 @@ void cpu_state_reset(CPUTriCoreState *env)
static void tricore_tcg_init_csfr(void) static void tricore_tcg_init_csfr(void)
{ {
cpu_PCXI = tcg_global_mem_new(cpu_env, cpu_PCXI = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PCXI), "PCXI"); offsetof(CPUTriCoreState, PCXI), "PCXI");
cpu_PSW = tcg_global_mem_new(cpu_env, cpu_PSW = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW), "PSW"); offsetof(CPUTriCoreState, PSW), "PSW");
cpu_PC = tcg_global_mem_new(cpu_env, cpu_PC = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PC), "PC"); offsetof(CPUTriCoreState, PC), "PC");
cpu_ICR = tcg_global_mem_new(cpu_env, cpu_ICR = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, ICR), "ICR"); offsetof(CPUTriCoreState, ICR), "ICR");
} }
@ -8522,30 +8522,30 @@ void tricore_tcg_init(void)
/* reg init */ /* reg init */
for (i = 0 ; i < 16 ; i++) { for (i = 0 ; i < 16 ; i++) {
cpu_gpr_a[i] = tcg_global_mem_new(cpu_env, cpu_gpr_a[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, gpr_a[i]), offsetof(CPUTriCoreState, gpr_a[i]),
regnames_a[i]); regnames_a[i]);
} }
for (i = 0 ; i < 16 ; i++) { for (i = 0 ; i < 16 ; i++) {
cpu_gpr_d[i] = tcg_global_mem_new(cpu_env, cpu_gpr_d[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, gpr_d[i]), offsetof(CPUTriCoreState, gpr_d[i]),
regnames_d[i]); regnames_d[i]);
} }
tricore_tcg_init_csfr(); tricore_tcg_init_csfr();
/* init PSW flag cache */ /* init PSW flag cache */
cpu_PSW_C = tcg_global_mem_new(cpu_env, cpu_PSW_C = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW_USB_C), offsetof(CPUTriCoreState, PSW_USB_C),
"PSW_C"); "PSW_C");
cpu_PSW_V = tcg_global_mem_new(cpu_env, cpu_PSW_V = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW_USB_V), offsetof(CPUTriCoreState, PSW_USB_V),
"PSW_V"); "PSW_V");
cpu_PSW_SV = tcg_global_mem_new(cpu_env, cpu_PSW_SV = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW_USB_SV), offsetof(CPUTriCoreState, PSW_USB_SV),
"PSW_SV"); "PSW_SV");
cpu_PSW_AV = tcg_global_mem_new(cpu_env, cpu_PSW_AV = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW_USB_AV), offsetof(CPUTriCoreState, PSW_USB_AV),
"PSW_AV"); "PSW_AV");
cpu_PSW_SAV = tcg_global_mem_new(cpu_env, cpu_PSW_SAV = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW_USB_SAV), offsetof(CPUTriCoreState, PSW_USB_SAV),
"PSW_SAV"); "PSW_SAV");
} }

188
target/xtensa/translate.c
View File

@ -154,49 +154,49 @@ void xtensa_translate_init(void)
}; };
int i; int i;
cpu_pc = tcg_global_mem_new_i32(cpu_env, cpu_pc = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, pc), "pc"); offsetof(CPUXtensaState, pc), "pc");
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env, cpu_R[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, regs[i]), offsetof(CPUXtensaState, regs[i]),
regnames[i]); regnames[i]);
} }
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
cpu_FR[i] = tcg_global_mem_new_i32(cpu_env, cpu_FR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, offsetof(CPUXtensaState,
fregs[i].f32[FP_F32_LOW]), fregs[i].f32[FP_F32_LOW]),
fregnames[i]); fregnames[i]);
} }
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
cpu_FRD[i] = tcg_global_mem_new_i64(cpu_env, cpu_FRD[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUXtensaState, offsetof(CPUXtensaState,
fregs[i].f64), fregs[i].f64),
fregnames[i]); fregnames[i]);
} }
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
cpu_MR[i] = tcg_global_mem_new_i32(cpu_env, cpu_MR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, offsetof(CPUXtensaState,
sregs[MR + i]), sregs[MR + i]),
mregnames[i]); mregnames[i]);
} }
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
cpu_BR[i] = tcg_global_mem_new_i32(cpu_env, cpu_BR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, offsetof(CPUXtensaState,
sregs[BR]), sregs[BR]),
bregnames[i]); bregnames[i]);
if (i % 4 == 0) { if (i % 4 == 0) {
cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env, cpu_BR4[i / 4] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, offsetof(CPUXtensaState,
sregs[BR]), sregs[BR]),
bregnames[i]); bregnames[i]);
} }
if (i % 8 == 0) { if (i % 8 == 0) {
cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env, cpu_BR8[i / 8] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, offsetof(CPUXtensaState,
sregs[BR]), sregs[BR]),
bregnames[i]); bregnames[i]);
@ -205,7 +205,7 @@ void xtensa_translate_init(void)
for (i = 0; i < 256; ++i) { for (i = 0; i < 256; ++i) {
if (sr_name[i]) { if (sr_name[i]) {
cpu_SR[i] = tcg_global_mem_new_i32(cpu_env, cpu_SR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, offsetof(CPUXtensaState,
sregs[i]), sregs[i]),
sr_name[i]); sr_name[i]);
@ -214,7 +214,7 @@ void xtensa_translate_init(void)
for (i = 0; i < 256; ++i) { for (i = 0; i < 256; ++i) {
if (ur_name[i]) { if (ur_name[i]) {
cpu_UR[i] = tcg_global_mem_new_i32(cpu_env, cpu_UR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, offsetof(CPUXtensaState,
uregs[i]), uregs[i]),
ur_name[i]); ur_name[i]);
@ -222,15 +222,15 @@ void xtensa_translate_init(void)
} }
cpu_windowbase_next = cpu_windowbase_next =
tcg_global_mem_new_i32(cpu_env, tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, windowbase_next), offsetof(CPUXtensaState, windowbase_next),
"windowbase_next"); "windowbase_next");
cpu_exclusive_addr = cpu_exclusive_addr =
tcg_global_mem_new_i32(cpu_env, tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, exclusive_addr), offsetof(CPUXtensaState, exclusive_addr),
"exclusive_addr"); "exclusive_addr");
cpu_exclusive_val = cpu_exclusive_val =
tcg_global_mem_new_i32(cpu_env, tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, exclusive_val), offsetof(CPUXtensaState, exclusive_val),
"exclusive_val"); "exclusive_val");
} }
@ -311,13 +311,13 @@ static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
static void gen_exception(DisasContext *dc, int excp) static void gen_exception(DisasContext *dc, int excp)
{ {
gen_helper_exception(cpu_env, tcg_constant_i32(excp)); gen_helper_exception(tcg_env, tcg_constant_i32(excp));
} }
static void gen_exception_cause(DisasContext *dc, uint32_t cause) static void gen_exception_cause(DisasContext *dc, uint32_t cause)
{ {
TCGv_i32 pc = tcg_constant_i32(dc->pc); TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_exception_cause(cpu_env, pc, tcg_constant_i32(cause)); gen_helper_exception_cause(tcg_env, pc, tcg_constant_i32(cause));
if (cause == ILLEGAL_INSTRUCTION_CAUSE || if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) { cause == SYSCALL_CAUSE) {
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
@ -327,7 +327,7 @@ static void gen_exception_cause(DisasContext *dc, uint32_t cause)
static void gen_debug_exception(DisasContext *dc, uint32_t cause) static void gen_debug_exception(DisasContext *dc, uint32_t cause)
{ {
TCGv_i32 pc = tcg_constant_i32(dc->pc); TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_debug_exception(cpu_env, pc, tcg_constant_i32(cause)); gen_helper_debug_exception(tcg_env, pc, tcg_constant_i32(cause));
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
} }
@ -536,7 +536,7 @@ static bool gen_window_check(DisasContext *dc, uint32_t mask)
TCGv_i32 pc = tcg_constant_i32(dc->pc); TCGv_i32 pc = tcg_constant_i32(dc->pc);
TCGv_i32 w = tcg_constant_i32(r / 4); TCGv_i32 w = tcg_constant_i32(r / 4);
gen_helper_window_check(cpu_env, pc, w); gen_helper_window_check(tcg_env, pc, w);
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
return false; return false;
} }
@ -576,11 +576,11 @@ static int gen_postprocess(DisasContext *dc, int slot)
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
translator_io_start(&dc->base); translator_io_start(&dc->base);
gen_helper_check_interrupts(cpu_env); gen_helper_check_interrupts(tcg_env);
} }
#endif #endif
if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) { if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
gen_helper_sync_windowbase(cpu_env); gen_helper_sync_windowbase(tcg_env);
} }
if (op_flags & XTENSA_OP_EXIT_TB_M1) { if (op_flags & XTENSA_OP_EXIT_TB_M1) {
slot = -1; slot = -1;
@ -1042,13 +1042,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
if (op_flags & XTENSA_OP_UNDERFLOW) { if (op_flags & XTENSA_OP_UNDERFLOW) {
TCGv_i32 pc = tcg_constant_i32(dc->pc); TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_test_underflow_retw(cpu_env, pc); gen_helper_test_underflow_retw(tcg_env, pc);
} }
if (op_flags & XTENSA_OP_ALLOCA) { if (op_flags & XTENSA_OP_ALLOCA) {
TCGv_i32 pc = tcg_constant_i32(dc->pc); TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_movsp(cpu_env, pc); gen_helper_movsp(tcg_env, pc);
} }
if (coprocessor && !gen_check_cpenable(dc, coprocessor)) { if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
@ -1589,7 +1589,7 @@ static void translate_entry(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 pc = tcg_constant_i32(dc->pc); TCGv_i32 pc = tcg_constant_i32(dc->pc);
TCGv_i32 s = tcg_constant_i32(arg[0].imm); TCGv_i32 s = tcg_constant_i32(arg[0].imm);
TCGv_i32 imm = tcg_constant_i32(arg[1].imm); TCGv_i32 imm = tcg_constant_i32(arg[1].imm);
gen_helper_entry(cpu_env, pc, s, imm); gen_helper_entry(tcg_env, pc, s, imm);
} }
static void translate_extui(DisasContext *dc, const OpcodeArg arg[], static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
@ -1620,7 +1620,7 @@ static void translate_icache(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_movi_i32(cpu_pc, dc->pc); tcg_gen_movi_i32(cpu_pc, dc->pc);
tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
gen_helper_itlb_hit_test(cpu_env, addr); gen_helper_itlb_hit_test(tcg_env, addr);
#endif #endif
} }
@ -1630,7 +1630,7 @@ static void translate_itlb(DisasContext *dc, const OpcodeArg arg[],
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
TCGv_i32 dtlb = tcg_constant_i32(par[0]); TCGv_i32 dtlb = tcg_constant_i32(par[0]);
gen_helper_itlb(cpu_env, arg[0].in, dtlb); gen_helper_itlb(tcg_env, arg[0].in, dtlb);
#endif #endif
} }
@ -1667,7 +1667,7 @@ static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write)
if (!option_enabled(dc, XTENSA_OPTION_MPU)) { if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
TCGv_i32 pc = tcg_constant_i32(dc->pc); TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_check_exclusive(cpu_env, pc, addr, gen_helper_check_exclusive(tcg_env, pc, addr,
tcg_constant_i32(is_write)); tcg_constant_i32(is_write));
} }
} }
@ -1959,7 +1959,7 @@ static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 dtlb = tcg_constant_i32(par[0]); TCGv_i32 dtlb = tcg_constant_i32(par[0]);
tcg_gen_movi_i32(cpu_pc, dc->pc); tcg_gen_movi_i32(cpu_pc, dc->pc);
gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb); gen_helper_ptlb(arg[0].out, tcg_env, arg[1].in, dtlb);
#endif #endif
} }
@ -1968,7 +1968,7 @@ static void translate_pptlb(DisasContext *dc, const OpcodeArg arg[],
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
tcg_gen_movi_i32(cpu_pc, dc->pc); tcg_gen_movi_i32(cpu_pc, dc->pc);
gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in); gen_helper_pptlb(arg[0].out, tcg_env, arg[1].in);
#endif #endif
} }
@ -2020,7 +2020,7 @@ static void translate_remu(DisasContext *dc, const OpcodeArg arg[],
static void translate_rer(DisasContext *dc, const OpcodeArg arg[], static void translate_rer(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_rer(arg[0].out, cpu_env, arg[1].in); gen_helper_rer(arg[0].out, tcg_env, arg[1].in);
} }
static void translate_ret(DisasContext *dc, const OpcodeArg arg[], static void translate_ret(DisasContext *dc, const OpcodeArg arg[],
@ -2039,7 +2039,7 @@ static uint32_t test_exceptions_retw(DisasContext *dc, const OpcodeArg arg[],
} else { } else {
TCGv_i32 pc = tcg_constant_i32(dc->pc); TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_test_ill_retw(cpu_env, pc); gen_helper_test_ill_retw(tcg_env, pc);
return 0; return 0;
} }
} }
@ -2053,7 +2053,7 @@ static void translate_retw(DisasContext *dc, const OpcodeArg arg[],
cpu_SR[WINDOW_START], tmp); cpu_SR[WINDOW_START], tmp);
tcg_gen_movi_i32(tmp, dc->pc); tcg_gen_movi_i32(tmp, dc->pc);
tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30); tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30);
gen_helper_retw(cpu_env, cpu_R[0]); gen_helper_retw(tcg_env, cpu_R[0]);
gen_jump(dc, tmp); gen_jump(dc, tmp);
} }
@ -2093,7 +2093,7 @@ static void translate_rfw(DisasContext *dc, const OpcodeArg arg[],
cpu_SR[WINDOW_START], tmp); cpu_SR[WINDOW_START], tmp);
} }
gen_helper_restore_owb(cpu_env); gen_helper_restore_owb(tcg_env);
gen_jump(dc, cpu_SR[EPC1]); gen_jump(dc, cpu_SR[EPC1]);
} }
@ -2126,7 +2126,7 @@ static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[],
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
translator_io_start(&dc->base); translator_io_start(&dc->base);
gen_helper_update_ccount(cpu_env); gen_helper_update_ccount(tcg_env);
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
#endif #endif
} }
@ -2154,7 +2154,7 @@ static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[],
}; };
TCGv_i32 dtlb = tcg_constant_i32(par[0]); TCGv_i32 dtlb = tcg_constant_i32(par[0]);
helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb); helper[par[1]](arg[0].out, tcg_env, arg[1].in, dtlb);
#endif #endif
} }
@ -2162,7 +2162,7 @@ static void translate_rptlb0(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in); gen_helper_rptlb0(arg[0].out, tcg_env, arg[1].in);
#endif #endif
} }
@ -2170,7 +2170,7 @@ static void translate_rptlb1(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in); gen_helper_rptlb1(arg[0].out, tcg_env, arg[1].in);
#endif #endif
} }
@ -2196,7 +2196,7 @@ static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
{ {
TCGv_i32 pc = tcg_constant_i32(dc->pc); TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_check_atomctl(cpu_env, pc, addr); gen_helper_check_atomctl(tcg_env, pc, addr);
} }
#endif #endif
@ -2297,7 +2297,7 @@ static void translate_simcall(DisasContext *dc, const OpcodeArg arg[],
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (semihosting_enabled(dc->cring != 0)) { if (semihosting_enabled(dc->cring != 0)) {
gen_helper_simcall(cpu_env); gen_helper_simcall(tcg_env);
} }
#endif #endif
} }
@ -2442,7 +2442,7 @@ static void translate_waiti(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 pc = tcg_constant_i32(dc->base.pc_next); TCGv_i32 pc = tcg_constant_i32(dc->base.pc_next);
translator_io_start(&dc->base); translator_io_start(&dc->base);
gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm)); gen_helper_waiti(tcg_env, pc, tcg_constant_i32(arg[0].imm));
#endif #endif
} }
@ -2452,7 +2452,7 @@ static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[],
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
TCGv_i32 dtlb = tcg_constant_i32(par[0]); TCGv_i32 dtlb = tcg_constant_i32(par[0]);
gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb); gen_helper_wtlb(tcg_env, arg[0].in, arg[1].in, dtlb);
#endif #endif
} }
@ -2460,14 +2460,14 @@ static void translate_wptlb(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in); gen_helper_wptlb(tcg_env, arg[0].in, arg[1].in);
#endif #endif
} }
static void translate_wer(DisasContext *dc, const OpcodeArg arg[], static void translate_wer(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_wer(cpu_env, arg[0].in, arg[1].in); gen_helper_wer(tcg_env, arg[0].in, arg[1].in);
} }
static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[], static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
@ -2508,7 +2508,7 @@ static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[],
assert(id < dc->config->nccompare); assert(id < dc->config->nccompare);
translator_io_start(&dc->base); translator_io_start(&dc->base);
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id)); gen_helper_update_ccompare(tcg_env, tcg_constant_i32(id));
#endif #endif
} }
@ -2517,7 +2517,7 @@ static void translate_wsr_ccount(DisasContext *dc, const OpcodeArg arg[],
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
translator_io_start(&dc->base); translator_io_start(&dc->base);
gen_helper_wsr_ccount(cpu_env, arg[0].in); gen_helper_wsr_ccount(tcg_env, arg[0].in);
#endif #endif
} }
@ -2528,7 +2528,7 @@ static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[],
unsigned id = par[0] - DBREAKA; unsigned id = par[0] - DBREAKA;
assert(id < dc->config->ndbreak); assert(id < dc->config->ndbreak);
gen_helper_wsr_dbreaka(cpu_env, tcg_constant_i32(id), arg[0].in); gen_helper_wsr_dbreaka(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif #endif
} }
@ -2539,7 +2539,7 @@ static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[],
unsigned id = par[0] - DBREAKC; unsigned id = par[0] - DBREAKC;
assert(id < dc->config->ndbreak); assert(id < dc->config->ndbreak);
gen_helper_wsr_dbreakc(cpu_env, tcg_constant_i32(id), arg[0].in); gen_helper_wsr_dbreakc(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif #endif
} }
@ -2550,7 +2550,7 @@ static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[],
unsigned id = par[0] - IBREAKA; unsigned id = par[0] - IBREAKA;
assert(id < dc->config->nibreak); assert(id < dc->config->nibreak);
gen_helper_wsr_ibreaka(cpu_env, tcg_constant_i32(id), arg[0].in); gen_helper_wsr_ibreaka(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif #endif
} }
@ -2558,7 +2558,7 @@ static void translate_wsr_ibreakenable(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_helper_wsr_ibreakenable(cpu_env, arg[0].in); gen_helper_wsr_ibreakenable(tcg_env, arg[0].in);
#endif #endif
} }
@ -2578,7 +2578,7 @@ static void translate_wsr_intclear(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_helper_intclear(cpu_env, arg[0].in); gen_helper_intclear(tcg_env, arg[0].in);
#endif #endif
} }
@ -2586,7 +2586,7 @@ static void translate_wsr_intset(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_helper_intset(cpu_env, arg[0].in); gen_helper_intset(tcg_env, arg[0].in);
#endif #endif
} }
@ -2594,7 +2594,7 @@ static void translate_wsr_memctl(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_helper_wsr_memctl(cpu_env, arg[0].in); gen_helper_wsr_memctl(tcg_env, arg[0].in);
#endif #endif
} }
@ -2602,7 +2602,7 @@ static void translate_wsr_mpuenb(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_helper_wsr_mpuenb(cpu_env, arg[0].in); gen_helper_wsr_mpuenb(tcg_env, arg[0].in);
#endif #endif
} }
@ -2625,7 +2625,7 @@ static void translate_wsr_rasid(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_helper_wsr_rasid(cpu_env, arg[0].in); gen_helper_wsr_rasid(tcg_env, arg[0].in);
#endif #endif
} }
@ -2704,9 +2704,9 @@ static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 tmp = tcg_temp_new_i32();
translator_io_start(&dc->base); translator_io_start(&dc->base);
gen_helper_update_ccount(cpu_env); gen_helper_update_ccount(tcg_env);
tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); tcg_gen_mov_i32(tmp, cpu_SR[par[0]]);
gen_helper_wsr_ccount(cpu_env, arg[0].in); gen_helper_wsr_ccount(tcg_env, arg[0].in);
tcg_gen_mov_i32(arg[0].out, tmp); tcg_gen_mov_i32(arg[0].out, tmp);
#endif #endif
@ -6295,7 +6295,7 @@ static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[], static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_fpu2k_add_s(arg[0].out, cpu_env, gen_helper_fpu2k_add_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in); arg[1].in, arg[2].in);
} }
@ -6330,7 +6330,7 @@ static void translate_compare_d(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm);
tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm)); tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
helper[par[0]](res, cpu_env, arg[1].in, arg[2].in); helper[par[0]](res, tcg_env, arg[1].in, arg[2].in);
tcg_gen_movcond_i32(TCG_COND_NE, tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero, arg[0].out, res, zero,
set_br, clr_br); set_br, clr_br);
@ -6359,7 +6359,7 @@ static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm)); tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
get_f32_i2(arg, arg32, 1, 2); get_f32_i2(arg, arg32, 1, 2);
helper[par[0]](res, cpu_env, arg32[1].in, arg32[2].in); helper[par[0]](res, tcg_env, arg32[1].in, arg32[2].in);
tcg_gen_movcond_i32(TCG_COND_NE, tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero, arg[0].out, res, zero,
set_br, clr_br); set_br, clr_br);
@ -6412,9 +6412,9 @@ static void translate_float_d(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 scale = tcg_constant_i32(-arg[2].imm); TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
if (par[0]) { if (par[0]) {
gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale); gen_helper_uitof_d(arg[0].out, tcg_env, arg[1].in, scale);
} else { } else {
gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale); gen_helper_itof_d(arg[0].out, tcg_env, arg[1].in, scale);
} }
} }
@ -6426,9 +6426,9 @@ static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
get_f32_o1(arg, arg32, 0); get_f32_o1(arg, arg32, 0);
if (par[0]) { if (par[0]) {
gen_helper_uitof_s(arg32[0].out, cpu_env, arg[1].in, scale); gen_helper_uitof_s(arg32[0].out, tcg_env, arg[1].in, scale);
} else { } else {
gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale); gen_helper_itof_s(arg32[0].out, tcg_env, arg[1].in, scale);
} }
put_f32_o1(arg, arg32, 0); put_f32_o1(arg, arg32, 0);
} }
@ -6440,10 +6440,10 @@ static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 scale = tcg_constant_i32(arg[2].imm); TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
if (par[1]) { if (par[1]) {
gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in, gen_helper_ftoui_d(arg[0].out, tcg_env, arg[1].in,
rounding_mode, scale); rounding_mode, scale);
} else { } else {
gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in, gen_helper_ftoi_d(arg[0].out, tcg_env, arg[1].in,
rounding_mode, scale); rounding_mode, scale);
} }
} }
@ -6457,10 +6457,10 @@ static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
get_f32_i1(arg, arg32, 1); get_f32_i1(arg, arg32, 1);
if (par[1]) { if (par[1]) {
gen_helper_ftoui_s(arg[0].out, cpu_env, arg32[1].in, gen_helper_ftoui_s(arg[0].out, tcg_env, arg32[1].in,
rounding_mode, scale); rounding_mode, scale);
} else { } else {
gen_helper_ftoi_s(arg[0].out, cpu_env, arg32[1].in, gen_helper_ftoi_s(arg[0].out, tcg_env, arg32[1].in,
rounding_mode, scale); rounding_mode, scale);
} }
put_f32_i1(arg, arg32, 1); put_f32_i1(arg, arg32, 1);
@ -6505,7 +6505,7 @@ static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[],
static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[], static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_fpu2k_madd_s(arg[0].out, cpu_env, gen_helper_fpu2k_madd_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in); arg[0].in, arg[1].in, arg[2].in);
} }
@ -6584,14 +6584,14 @@ static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[], static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_fpu2k_mul_s(arg[0].out, cpu_env, gen_helper_fpu2k_mul_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in); arg[1].in, arg[2].in);
} }
static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[], static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_fpu2k_msub_s(arg[0].out, cpu_env, gen_helper_fpu2k_msub_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in); arg[0].in, arg[1].in, arg[2].in);
} }
@ -6630,7 +6630,7 @@ static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[], static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_fpu2k_sub_s(arg[0].out, cpu_env, gen_helper_fpu2k_sub_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in); arg[1].in, arg[2].in);
} }
@ -6653,7 +6653,7 @@ static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[], static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in); gen_helper_wur_fpu2k_fcr(tcg_env, arg[0].in);
} }
static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[], static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[],
@ -6882,20 +6882,20 @@ const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = {
static void translate_add_d(DisasContext *dc, const OpcodeArg arg[], static void translate_add_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_add_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); gen_helper_add_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
} }
static void translate_add_s(DisasContext *dc, const OpcodeArg arg[], static void translate_add_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
gen_helper_fpu2k_add_s(arg[0].out, cpu_env, gen_helper_fpu2k_add_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in); arg[1].in, arg[2].in);
} else { } else {
OpcodeArg arg32[3]; OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2); get_f32_o1_i2(arg, arg32, 0, 1, 2);
gen_helper_add_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); gen_helper_add_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2); put_f32_o1_i2(arg, arg32, 0, 1, 2);
} }
} }
@ -6906,7 +6906,7 @@ static void translate_cvtd_s(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 v = tcg_temp_new_i32(); TCGv_i32 v = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(v, arg[1].in); tcg_gen_extrl_i64_i32(v, arg[1].in);
gen_helper_cvtd_s(arg[0].out, cpu_env, v); gen_helper_cvtd_s(arg[0].out, tcg_env, v);
} }
static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[], static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[],
@ -6914,7 +6914,7 @@ static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[],
{ {
TCGv_i32 v = tcg_temp_new_i32(); TCGv_i32 v = tcg_temp_new_i32();
gen_helper_cvts_d(v, cpu_env, arg[1].in); gen_helper_cvts_d(v, tcg_env, arg[1].in);
tcg_gen_extu_i32_i64(arg[0].out, v); tcg_gen_extu_i32_i64(arg[0].out, v);
} }
@ -7039,7 +7039,7 @@ static void translate_ldstx_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[], static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_madd_d(arg[0].out, cpu_env, gen_helper_madd_d(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in); arg[0].in, arg[1].in, arg[2].in);
} }
@ -7047,13 +7047,13 @@ static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
gen_helper_fpu2k_madd_s(arg[0].out, cpu_env, gen_helper_fpu2k_madd_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in); arg[0].in, arg[1].in, arg[2].in);
} else { } else {
OpcodeArg arg32[3]; OpcodeArg arg32[3];
get_f32_o1_i3(arg, arg32, 0, 0, 1, 2); get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
gen_helper_madd_s(arg32[0].out, cpu_env, gen_helper_madd_s(arg32[0].out, tcg_env,
arg32[0].in, arg32[1].in, arg32[2].in); arg32[0].in, arg32[1].in, arg32[2].in);
put_f32_o1_i3(arg, arg32, 0, 0, 1, 2); put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
} }
@ -7062,20 +7062,20 @@ static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[], static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_mul_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); gen_helper_mul_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
} }
static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[], static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
gen_helper_fpu2k_mul_s(arg[0].out, cpu_env, gen_helper_fpu2k_mul_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in); arg[1].in, arg[2].in);
} else { } else {
OpcodeArg arg32[3]; OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2); get_f32_o1_i2(arg, arg32, 0, 1, 2);
gen_helper_mul_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); gen_helper_mul_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2); put_f32_o1_i2(arg, arg32, 0, 1, 2);
} }
} }
@ -7083,7 +7083,7 @@ static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[], static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_msub_d(arg[0].out, cpu_env, gen_helper_msub_d(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in); arg[0].in, arg[1].in, arg[2].in);
} }
@ -7091,13 +7091,13 @@ static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
gen_helper_fpu2k_msub_s(arg[0].out, cpu_env, gen_helper_fpu2k_msub_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in); arg[0].in, arg[1].in, arg[2].in);
} else { } else {
OpcodeArg arg32[3]; OpcodeArg arg32[3];
get_f32_o1_i3(arg, arg32, 0, 0, 1, 2); get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
gen_helper_msub_s(arg32[0].out, cpu_env, gen_helper_msub_s(arg32[0].out, tcg_env,
arg32[0].in, arg32[1].in, arg32[2].in); arg32[0].in, arg32[1].in, arg32[2].in);
put_f32_o1_i3(arg, arg32, 0, 0, 1, 2); put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
} }
@ -7106,20 +7106,20 @@ static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[], static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_sub_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); gen_helper_sub_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
} }
static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[], static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
gen_helper_fpu2k_sub_s(arg[0].out, cpu_env, gen_helper_fpu2k_sub_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in); arg[1].in, arg[2].in);
} else { } else {
OpcodeArg arg32[3]; OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2); get_f32_o1_i2(arg, arg32, 0, 1, 2);
gen_helper_sub_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); gen_helper_sub_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2); put_f32_o1_i2(arg, arg32, 0, 1, 2);
} }
} }
@ -7127,7 +7127,7 @@ static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[], static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_mkdadj_d(arg[0].out, cpu_env, arg[0].in, arg[1].in); gen_helper_mkdadj_d(arg[0].out, tcg_env, arg[0].in, arg[1].in);
} }
static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[], static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[],
@ -7136,14 +7136,14 @@ static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[],
OpcodeArg arg32[2]; OpcodeArg arg32[2];
get_f32_o1_i2(arg, arg32, 0, 0, 1); get_f32_o1_i2(arg, arg32, 0, 0, 1);
gen_helper_mkdadj_s(arg32[0].out, cpu_env, arg32[0].in, arg32[1].in); gen_helper_mkdadj_s(arg32[0].out, tcg_env, arg32[0].in, arg32[1].in);
put_f32_o1_i2(arg, arg32, 0, 0, 1); put_f32_o1_i2(arg, arg32, 0, 0, 1);
} }
static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[], static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_mksadj_d(arg[0].out, cpu_env, arg[1].in); gen_helper_mksadj_d(arg[0].out, tcg_env, arg[1].in);
} }
static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[], static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[],
@ -7152,26 +7152,26 @@ static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[],
OpcodeArg arg32[2]; OpcodeArg arg32[2];
get_f32_o1_i1(arg, arg32, 0, 1); get_f32_o1_i1(arg, arg32, 0, 1);
gen_helper_mksadj_s(arg32[0].out, cpu_env, arg32[1].in); gen_helper_mksadj_s(arg32[0].out, tcg_env, arg32[1].in);
put_f32_o1_i1(arg, arg32, 0, 1); put_f32_o1_i1(arg, arg32, 0, 1);
} }
static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[], static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_wur_fpu_fcr(cpu_env, arg[0].in); gen_helper_wur_fpu_fcr(tcg_env, arg[0].in);
} }
static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[], static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_rur_fpu_fsr(arg[0].out, cpu_env); gen_helper_rur_fpu_fsr(arg[0].out, tcg_env);
} }
static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[], static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
gen_helper_wur_fpu_fsr(cpu_env, arg[0].in); gen_helper_wur_fpu_fsr(tcg_env, arg[0].in);
} }
static const XtensaOpcodeOps fpu_ops[] = { static const XtensaOpcodeOps fpu_ops[] = {

300
tcg/tcg-op-gvec.c
View File

@ -120,8 +120,8 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
a0 = tcg_temp_ebb_new_ptr(); a0 = tcg_temp_ebb_new_ptr();
a1 = tcg_temp_ebb_new_ptr(); a1 = tcg_temp_ebb_new_ptr();
tcg_gen_addi_ptr(a0, cpu_env, dofs); tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, cpu_env, aofs); tcg_gen_addi_ptr(a1, tcg_env, aofs);
fn(a0, a1, desc); fn(a0, a1, desc);
@ -141,8 +141,8 @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
a0 = tcg_temp_ebb_new_ptr(); a0 = tcg_temp_ebb_new_ptr();
a1 = tcg_temp_ebb_new_ptr(); a1 = tcg_temp_ebb_new_ptr();
tcg_gen_addi_ptr(a0, cpu_env, dofs); tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, cpu_env, aofs); tcg_gen_addi_ptr(a1, tcg_env, aofs);
fn(a0, a1, c, desc); fn(a0, a1, c, desc);
@ -162,9 +162,9 @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
a1 = tcg_temp_ebb_new_ptr(); a1 = tcg_temp_ebb_new_ptr();
a2 = tcg_temp_ebb_new_ptr(); a2 = tcg_temp_ebb_new_ptr();
tcg_gen_addi_ptr(a0, cpu_env, dofs); tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, cpu_env, aofs); tcg_gen_addi_ptr(a1, tcg_env, aofs);
tcg_gen_addi_ptr(a2, cpu_env, bofs); tcg_gen_addi_ptr(a2, tcg_env, bofs);
fn(a0, a1, a2, desc); fn(a0, a1, a2, desc);
@ -186,10 +186,10 @@ void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
a2 = tcg_temp_ebb_new_ptr(); a2 = tcg_temp_ebb_new_ptr();
a3 = tcg_temp_ebb_new_ptr(); a3 = tcg_temp_ebb_new_ptr();
tcg_gen_addi_ptr(a0, cpu_env, dofs); tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, cpu_env, aofs); tcg_gen_addi_ptr(a1, tcg_env, aofs);
tcg_gen_addi_ptr(a2, cpu_env, bofs); tcg_gen_addi_ptr(a2, tcg_env, bofs);
tcg_gen_addi_ptr(a3, cpu_env, cofs); tcg_gen_addi_ptr(a3, tcg_env, cofs);
fn(a0, a1, a2, a3, desc); fn(a0, a1, a2, a3, desc);
@ -213,11 +213,11 @@ void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
a3 = tcg_temp_ebb_new_ptr(); a3 = tcg_temp_ebb_new_ptr();
a4 = tcg_temp_ebb_new_ptr(); a4 = tcg_temp_ebb_new_ptr();
tcg_gen_addi_ptr(a0, cpu_env, dofs); tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, cpu_env, aofs); tcg_gen_addi_ptr(a1, tcg_env, aofs);
tcg_gen_addi_ptr(a2, cpu_env, bofs); tcg_gen_addi_ptr(a2, tcg_env, bofs);
tcg_gen_addi_ptr(a3, cpu_env, cofs); tcg_gen_addi_ptr(a3, tcg_env, cofs);
tcg_gen_addi_ptr(a4, cpu_env, xofs); tcg_gen_addi_ptr(a4, tcg_env, xofs);
fn(a0, a1, a2, a3, a4, desc); fn(a0, a1, a2, a3, a4, desc);
@ -240,8 +240,8 @@ void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
a0 = tcg_temp_ebb_new_ptr(); a0 = tcg_temp_ebb_new_ptr();
a1 = tcg_temp_ebb_new_ptr(); a1 = tcg_temp_ebb_new_ptr();
tcg_gen_addi_ptr(a0, cpu_env, dofs); tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, cpu_env, aofs); tcg_gen_addi_ptr(a1, tcg_env, aofs);
fn(a0, a1, ptr, desc); fn(a0, a1, ptr, desc);
@ -262,9 +262,9 @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
a1 = tcg_temp_ebb_new_ptr(); a1 = tcg_temp_ebb_new_ptr();
a2 = tcg_temp_ebb_new_ptr(); a2 = tcg_temp_ebb_new_ptr();
tcg_gen_addi_ptr(a0, cpu_env, dofs); tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, cpu_env, aofs); tcg_gen_addi_ptr(a1, tcg_env, aofs);
tcg_gen_addi_ptr(a2, cpu_env, bofs); tcg_gen_addi_ptr(a2, tcg_env, bofs);
fn(a0, a1, a2, ptr, desc); fn(a0, a1, a2, ptr, desc);
@ -288,10 +288,10 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
a2 = tcg_temp_ebb_new_ptr(); a2 = tcg_temp_ebb_new_ptr();
a3 = tcg_temp_ebb_new_ptr(); a3 = tcg_temp_ebb_new_ptr();
tcg_gen_addi_ptr(a0, cpu_env, dofs); tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, cpu_env, aofs); tcg_gen_addi_ptr(a1, tcg_env, aofs);
tcg_gen_addi_ptr(a2, cpu_env, bofs); tcg_gen_addi_ptr(a2, tcg_env, bofs);
tcg_gen_addi_ptr(a3, cpu_env, cofs); tcg_gen_addi_ptr(a3, tcg_env, cofs);
fn(a0, a1, a2, a3, ptr, desc); fn(a0, a1, a2, a3, ptr, desc);
@ -317,11 +317,11 @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
a3 = tcg_temp_ebb_new_ptr(); a3 = tcg_temp_ebb_new_ptr();
a4 = tcg_temp_ebb_new_ptr(); a4 = tcg_temp_ebb_new_ptr();
tcg_gen_addi_ptr(a0, cpu_env, dofs); tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, cpu_env, aofs); tcg_gen_addi_ptr(a1, tcg_env, aofs);
tcg_gen_addi_ptr(a2, cpu_env, bofs); tcg_gen_addi_ptr(a2, tcg_env, bofs);
tcg_gen_addi_ptr(a3, cpu_env, cofs); tcg_gen_addi_ptr(a3, tcg_env, cofs);
tcg_gen_addi_ptr(a4, cpu_env, eofs); tcg_gen_addi_ptr(a4, tcg_env, eofs);
fn(a0, a1, a2, a3, a4, ptr, desc); fn(a0, a1, a2, a3, a4, ptr, desc);
@ -482,7 +482,7 @@ static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz,
* are misaligned wrt the maximum vector size, so do that first. * are misaligned wrt the maximum vector size, so do that first.
*/ */
if (dofs & 8) { if (dofs & 8) {
tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V64);
i += 8; i += 8;
} }
@ -494,17 +494,17 @@ static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz,
* that e.g. size == 80 would be expanded with 2x32 + 1x16. * that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/ */
for (; i + 32 <= oprsz; i += 32) { for (; i + 32 <= oprsz; i += 32) {
tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V256);
} }
/* fallthru */ /* fallthru */
case TCG_TYPE_V128: case TCG_TYPE_V128:
for (; i + 16 <= oprsz; i += 16) { for (; i + 16 <= oprsz; i += 16) {
tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V128);
} }
break; break;
case TCG_TYPE_V64: case TCG_TYPE_V64:
for (; i < oprsz; i += 8) { for (; i < oprsz; i += 8) {
tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V64);
} }
break; break;
default: default:
@ -605,14 +605,14 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
/* Implement inline if we picked an implementation size above. */ /* Implement inline if we picked an implementation size above. */
if (t_32) { if (t_32) {
for (i = 0; i < oprsz; i += 4) { for (i = 0; i < oprsz; i += 4) {
tcg_gen_st_i32(t_32, cpu_env, dofs + i); tcg_gen_st_i32(t_32, tcg_env, dofs + i);
} }
tcg_temp_free_i32(t_32); tcg_temp_free_i32(t_32);
goto done; goto done;
} }
if (t_64) { if (t_64) {
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_st_i64(t_64, cpu_env, dofs + i); tcg_gen_st_i64(t_64, tcg_env, dofs + i);
} }
tcg_temp_free_i64(t_64); tcg_temp_free_i64(t_64);
goto done; goto done;
@ -621,7 +621,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
/* Otherwise implement out of line. */ /* Otherwise implement out of line. */
t_ptr = tcg_temp_ebb_new_ptr(); t_ptr = tcg_temp_ebb_new_ptr();
tcg_gen_addi_ptr(t_ptr, cpu_env, dofs); tcg_gen_addi_ptr(t_ptr, tcg_env, dofs);
/* /*
* This may be expand_clr for the tail of an operation, e.g. * This may be expand_clr for the tail of an operation, e.g.
@ -709,12 +709,12 @@ static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 4) { for (i = 0; i < oprsz; i += 4) {
tcg_gen_ld_i32(t0, cpu_env, aofs + i); tcg_gen_ld_i32(t0, tcg_env, aofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_i32(t1, cpu_env, dofs + i); tcg_gen_ld_i32(t1, tcg_env, dofs + i);
} }
fni(t1, t0); fni(t1, t0);
tcg_gen_st_i32(t1, cpu_env, dofs + i); tcg_gen_st_i32(t1, tcg_env, dofs + i);
} }
tcg_temp_free_i32(t0); tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
@ -729,12 +729,12 @@ static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 4) { for (i = 0; i < oprsz; i += 4) {
tcg_gen_ld_i32(t0, cpu_env, aofs + i); tcg_gen_ld_i32(t0, tcg_env, aofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_i32(t1, cpu_env, dofs + i); tcg_gen_ld_i32(t1, tcg_env, dofs + i);
} }
fni(t1, t0, c); fni(t1, t0, c);
tcg_gen_st_i32(t1, cpu_env, dofs + i); tcg_gen_st_i32(t1, tcg_env, dofs + i);
} }
tcg_temp_free_i32(t0); tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
@ -749,13 +749,13 @@ static void expand_2s_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 4) { for (i = 0; i < oprsz; i += 4) {
tcg_gen_ld_i32(t0, cpu_env, aofs + i); tcg_gen_ld_i32(t0, tcg_env, aofs + i);
if (scalar_first) { if (scalar_first) {
fni(t1, c, t0); fni(t1, c, t0);
} else { } else {
fni(t1, t0, c); fni(t1, t0, c);
} }
tcg_gen_st_i32(t1, cpu_env, dofs + i); tcg_gen_st_i32(t1, tcg_env, dofs + i);
} }
tcg_temp_free_i32(t0); tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
@ -772,13 +772,13 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 4) { for (i = 0; i < oprsz; i += 4) {
tcg_gen_ld_i32(t0, cpu_env, aofs + i); tcg_gen_ld_i32(t0, tcg_env, aofs + i);
tcg_gen_ld_i32(t1, cpu_env, bofs + i); tcg_gen_ld_i32(t1, tcg_env, bofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_i32(t2, cpu_env, dofs + i); tcg_gen_ld_i32(t2, tcg_env, dofs + i);
} }
fni(t2, t0, t1); fni(t2, t0, t1);
tcg_gen_st_i32(t2, cpu_env, dofs + i); tcg_gen_st_i32(t2, tcg_env, dofs + i);
} }
tcg_temp_free_i32(t2); tcg_temp_free_i32(t2);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
@ -795,13 +795,13 @@ static void expand_3i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 4) { for (i = 0; i < oprsz; i += 4) {
tcg_gen_ld_i32(t0, cpu_env, aofs + i); tcg_gen_ld_i32(t0, tcg_env, aofs + i);
tcg_gen_ld_i32(t1, cpu_env, bofs + i); tcg_gen_ld_i32(t1, tcg_env, bofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_i32(t2, cpu_env, dofs + i); tcg_gen_ld_i32(t2, tcg_env, dofs + i);
} }
fni(t2, t0, t1, c); fni(t2, t0, t1, c);
tcg_gen_st_i32(t2, cpu_env, dofs + i); tcg_gen_st_i32(t2, tcg_env, dofs + i);
} }
tcg_temp_free_i32(t0); tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
@ -820,13 +820,13 @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 4) { for (i = 0; i < oprsz; i += 4) {
tcg_gen_ld_i32(t1, cpu_env, aofs + i); tcg_gen_ld_i32(t1, tcg_env, aofs + i);
tcg_gen_ld_i32(t2, cpu_env, bofs + i); tcg_gen_ld_i32(t2, tcg_env, bofs + i);
tcg_gen_ld_i32(t3, cpu_env, cofs + i); tcg_gen_ld_i32(t3, tcg_env, cofs + i);
fni(t0, t1, t2, t3); fni(t0, t1, t2, t3);
tcg_gen_st_i32(t0, cpu_env, dofs + i); tcg_gen_st_i32(t0, tcg_env, dofs + i);
if (write_aofs) { if (write_aofs) {
tcg_gen_st_i32(t1, cpu_env, aofs + i); tcg_gen_st_i32(t1, tcg_env, aofs + i);
} }
} }
tcg_temp_free_i32(t3); tcg_temp_free_i32(t3);
@ -847,11 +847,11 @@ static void expand_4i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 4) { for (i = 0; i < oprsz; i += 4) {
tcg_gen_ld_i32(t1, cpu_env, aofs + i); tcg_gen_ld_i32(t1, tcg_env, aofs + i);
tcg_gen_ld_i32(t2, cpu_env, bofs + i); tcg_gen_ld_i32(t2, tcg_env, bofs + i);
tcg_gen_ld_i32(t3, cpu_env, cofs + i); tcg_gen_ld_i32(t3, tcg_env, cofs + i);
fni(t0, t1, t2, t3, c); fni(t0, t1, t2, t3, c);
tcg_gen_st_i32(t0, cpu_env, dofs + i); tcg_gen_st_i32(t0, tcg_env, dofs + i);
} }
tcg_temp_free_i32(t3); tcg_temp_free_i32(t3);
tcg_temp_free_i32(t2); tcg_temp_free_i32(t2);
@ -868,12 +868,12 @@ static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i64(t0, cpu_env, aofs + i); tcg_gen_ld_i64(t0, tcg_env, aofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_i64(t1, cpu_env, dofs + i); tcg_gen_ld_i64(t1, tcg_env, dofs + i);
} }
fni(t1, t0); fni(t1, t0);
tcg_gen_st_i64(t1, cpu_env, dofs + i); tcg_gen_st_i64(t1, tcg_env, dofs + i);
} }
tcg_temp_free_i64(t0); tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1); tcg_temp_free_i64(t1);
@ -888,12 +888,12 @@ static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i64(t0, cpu_env, aofs + i); tcg_gen_ld_i64(t0, tcg_env, aofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_i64(t1, cpu_env, dofs + i); tcg_gen_ld_i64(t1, tcg_env, dofs + i);
} }
fni(t1, t0, c); fni(t1, t0, c);
tcg_gen_st_i64(t1, cpu_env, dofs + i); tcg_gen_st_i64(t1, tcg_env, dofs + i);
} }
tcg_temp_free_i64(t0); tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1); tcg_temp_free_i64(t1);
@ -908,13 +908,13 @@ static void expand_2s_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i64(t0, cpu_env, aofs + i); tcg_gen_ld_i64(t0, tcg_env, aofs + i);
if (scalar_first) { if (scalar_first) {
fni(t1, c, t0); fni(t1, c, t0);
} else { } else {
fni(t1, t0, c); fni(t1, t0, c);
} }
tcg_gen_st_i64(t1, cpu_env, dofs + i); tcg_gen_st_i64(t1, tcg_env, dofs + i);
} }
tcg_temp_free_i64(t0); tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1); tcg_temp_free_i64(t1);
@ -931,13 +931,13 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i64(t0, cpu_env, aofs + i); tcg_gen_ld_i64(t0, tcg_env, aofs + i);
tcg_gen_ld_i64(t1, cpu_env, bofs + i); tcg_gen_ld_i64(t1, tcg_env, bofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_i64(t2, cpu_env, dofs + i); tcg_gen_ld_i64(t2, tcg_env, dofs + i);
} }
fni(t2, t0, t1); fni(t2, t0, t1);
tcg_gen_st_i64(t2, cpu_env, dofs + i); tcg_gen_st_i64(t2, tcg_env, dofs + i);
} }
tcg_temp_free_i64(t2); tcg_temp_free_i64(t2);
tcg_temp_free_i64(t1); tcg_temp_free_i64(t1);
@ -954,13 +954,13 @@ static void expand_3i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i64(t0, cpu_env, aofs + i); tcg_gen_ld_i64(t0, tcg_env, aofs + i);
tcg_gen_ld_i64(t1, cpu_env, bofs + i); tcg_gen_ld_i64(t1, tcg_env, bofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_i64(t2, cpu_env, dofs + i); tcg_gen_ld_i64(t2, tcg_env, dofs + i);
} }
fni(t2, t0, t1, c); fni(t2, t0, t1, c);
tcg_gen_st_i64(t2, cpu_env, dofs + i); tcg_gen_st_i64(t2, tcg_env, dofs + i);
} }
tcg_temp_free_i64(t0); tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1); tcg_temp_free_i64(t1);
@ -979,13 +979,13 @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i64(t1, cpu_env, aofs + i); tcg_gen_ld_i64(t1, tcg_env, aofs + i);
tcg_gen_ld_i64(t2, cpu_env, bofs + i); tcg_gen_ld_i64(t2, tcg_env, bofs + i);
tcg_gen_ld_i64(t3, cpu_env, cofs + i); tcg_gen_ld_i64(t3, tcg_env, cofs + i);
fni(t0, t1, t2, t3); fni(t0, t1, t2, t3);
tcg_gen_st_i64(t0, cpu_env, dofs + i); tcg_gen_st_i64(t0, tcg_env, dofs + i);
if (write_aofs) { if (write_aofs) {
tcg_gen_st_i64(t1, cpu_env, aofs + i); tcg_gen_st_i64(t1, tcg_env, aofs + i);
} }
} }
tcg_temp_free_i64(t3); tcg_temp_free_i64(t3);
@ -1006,11 +1006,11 @@ static void expand_4i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i64(t1, cpu_env, aofs + i); tcg_gen_ld_i64(t1, tcg_env, aofs + i);
tcg_gen_ld_i64(t2, cpu_env, bofs + i); tcg_gen_ld_i64(t2, tcg_env, bofs + i);
tcg_gen_ld_i64(t3, cpu_env, cofs + i); tcg_gen_ld_i64(t3, tcg_env, cofs + i);
fni(t0, t1, t2, t3, c); fni(t0, t1, t2, t3, c);
tcg_gen_st_i64(t0, cpu_env, dofs + i); tcg_gen_st_i64(t0, tcg_env, dofs + i);
} }
tcg_temp_free_i64(t3); tcg_temp_free_i64(t3);
tcg_temp_free_i64(t2); tcg_temp_free_i64(t2);
@ -1029,12 +1029,12 @@ static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += tysz) { for (i = 0; i < oprsz; i += tysz) {
tcg_gen_ld_vec(t0, cpu_env, aofs + i); tcg_gen_ld_vec(t0, tcg_env, aofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_vec(t1, cpu_env, dofs + i); tcg_gen_ld_vec(t1, tcg_env, dofs + i);
} }
fni(vece, t1, t0); fni(vece, t1, t0);
tcg_gen_st_vec(t1, cpu_env, dofs + i); tcg_gen_st_vec(t1, tcg_env, dofs + i);
} }
tcg_temp_free_vec(t0); tcg_temp_free_vec(t0);
tcg_temp_free_vec(t1); tcg_temp_free_vec(t1);
@ -1052,12 +1052,12 @@ static void expand_2i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += tysz) { for (i = 0; i < oprsz; i += tysz) {
tcg_gen_ld_vec(t0, cpu_env, aofs + i); tcg_gen_ld_vec(t0, tcg_env, aofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_vec(t1, cpu_env, dofs + i); tcg_gen_ld_vec(t1, tcg_env, dofs + i);
} }
fni(vece, t1, t0, c); fni(vece, t1, t0, c);
tcg_gen_st_vec(t1, cpu_env, dofs + i); tcg_gen_st_vec(t1, tcg_env, dofs + i);
} }
tcg_temp_free_vec(t0); tcg_temp_free_vec(t0);
tcg_temp_free_vec(t1); tcg_temp_free_vec(t1);
@ -1073,13 +1073,13 @@ static void expand_2s_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += tysz) { for (i = 0; i < oprsz; i += tysz) {
tcg_gen_ld_vec(t0, cpu_env, aofs + i); tcg_gen_ld_vec(t0, tcg_env, aofs + i);
if (scalar_first) { if (scalar_first) {
fni(vece, t1, c, t0); fni(vece, t1, c, t0);
} else { } else {
fni(vece, t1, t0, c); fni(vece, t1, t0, c);
} }
tcg_gen_st_vec(t1, cpu_env, dofs + i); tcg_gen_st_vec(t1, tcg_env, dofs + i);
} }
tcg_temp_free_vec(t0); tcg_temp_free_vec(t0);
tcg_temp_free_vec(t1); tcg_temp_free_vec(t1);
@ -1097,13 +1097,13 @@ static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += tysz) { for (i = 0; i < oprsz; i += tysz) {
tcg_gen_ld_vec(t0, cpu_env, aofs + i); tcg_gen_ld_vec(t0, tcg_env, aofs + i);
tcg_gen_ld_vec(t1, cpu_env, bofs + i); tcg_gen_ld_vec(t1, tcg_env, bofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_vec(t2, cpu_env, dofs + i); tcg_gen_ld_vec(t2, tcg_env, dofs + i);
} }
fni(vece, t2, t0, t1); fni(vece, t2, t0, t1);
tcg_gen_st_vec(t2, cpu_env, dofs + i); tcg_gen_st_vec(t2, tcg_env, dofs + i);
} }
tcg_temp_free_vec(t2); tcg_temp_free_vec(t2);
tcg_temp_free_vec(t1); tcg_temp_free_vec(t1);
@ -1126,13 +1126,13 @@ static void expand_3i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += tysz) { for (i = 0; i < oprsz; i += tysz) {
tcg_gen_ld_vec(t0, cpu_env, aofs + i); tcg_gen_ld_vec(t0, tcg_env, aofs + i);
tcg_gen_ld_vec(t1, cpu_env, bofs + i); tcg_gen_ld_vec(t1, tcg_env, bofs + i);
if (load_dest) { if (load_dest) {
tcg_gen_ld_vec(t2, cpu_env, dofs + i); tcg_gen_ld_vec(t2, tcg_env, dofs + i);
} }
fni(vece, t2, t0, t1, c); fni(vece, t2, t0, t1, c);
tcg_gen_st_vec(t2, cpu_env, dofs + i); tcg_gen_st_vec(t2, tcg_env, dofs + i);
} }
tcg_temp_free_vec(t0); tcg_temp_free_vec(t0);
tcg_temp_free_vec(t1); tcg_temp_free_vec(t1);
@ -1153,13 +1153,13 @@ static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += tysz) { for (i = 0; i < oprsz; i += tysz) {
tcg_gen_ld_vec(t1, cpu_env, aofs + i); tcg_gen_ld_vec(t1, tcg_env, aofs + i);
tcg_gen_ld_vec(t2, cpu_env, bofs + i); tcg_gen_ld_vec(t2, tcg_env, bofs + i);
tcg_gen_ld_vec(t3, cpu_env, cofs + i); tcg_gen_ld_vec(t3, tcg_env, cofs + i);
fni(vece, t0, t1, t2, t3); fni(vece, t0, t1, t2, t3);
tcg_gen_st_vec(t0, cpu_env, dofs + i); tcg_gen_st_vec(t0, tcg_env, dofs + i);
if (write_aofs) { if (write_aofs) {
tcg_gen_st_vec(t1, cpu_env, aofs + i); tcg_gen_st_vec(t1, tcg_env, aofs + i);
} }
} }
tcg_temp_free_vec(t3); tcg_temp_free_vec(t3);
@ -1185,11 +1185,11 @@ static void expand_4i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += tysz) { for (i = 0; i < oprsz; i += tysz) {
tcg_gen_ld_vec(t1, cpu_env, aofs + i); tcg_gen_ld_vec(t1, tcg_env, aofs + i);
tcg_gen_ld_vec(t2, cpu_env, bofs + i); tcg_gen_ld_vec(t2, tcg_env, bofs + i);
tcg_gen_ld_vec(t3, cpu_env, cofs + i); tcg_gen_ld_vec(t3, tcg_env, cofs + i);
fni(vece, t0, t1, t2, t3, c); fni(vece, t0, t1, t2, t3, c);
tcg_gen_st_vec(t0, cpu_env, dofs + i); tcg_gen_st_vec(t0, tcg_env, dofs + i);
} }
tcg_temp_free_vec(t3); tcg_temp_free_vec(t3);
tcg_temp_free_vec(t2); tcg_temp_free_vec(t2);
@ -1730,27 +1730,27 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
TCGType type = choose_vector_type(NULL, vece, oprsz, 0); TCGType type = choose_vector_type(NULL, vece, oprsz, 0);
if (type != 0) { if (type != 0) {
TCGv_vec t_vec = tcg_temp_new_vec(type); TCGv_vec t_vec = tcg_temp_new_vec(type);
tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs); tcg_gen_dup_mem_vec(vece, t_vec, tcg_env, aofs);
do_dup_store(type, dofs, oprsz, maxsz, t_vec); do_dup_store(type, dofs, oprsz, maxsz, t_vec);
tcg_temp_free_vec(t_vec); tcg_temp_free_vec(t_vec);
} else if (vece <= MO_32) { } else if (vece <= MO_32) {
TCGv_i32 in = tcg_temp_ebb_new_i32(); TCGv_i32 in = tcg_temp_ebb_new_i32();
switch (vece) { switch (vece) {
case MO_8: case MO_8:
tcg_gen_ld8u_i32(in, cpu_env, aofs); tcg_gen_ld8u_i32(in, tcg_env, aofs);
break; break;
case MO_16: case MO_16:
tcg_gen_ld16u_i32(in, cpu_env, aofs); tcg_gen_ld16u_i32(in, tcg_env, aofs);
break; break;
default: default:
tcg_gen_ld_i32(in, cpu_env, aofs); tcg_gen_ld_i32(in, tcg_env, aofs);
break; break;
} }
do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0); do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0);
tcg_temp_free_i32(in); tcg_temp_free_i32(in);
} else { } else {
TCGv_i64 in = tcg_temp_ebb_new_i64(); TCGv_i64 in = tcg_temp_ebb_new_i64();
tcg_gen_ld_i64(in, cpu_env, aofs); tcg_gen_ld_i64(in, tcg_env, aofs);
do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0); do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0);
tcg_temp_free_i64(in); tcg_temp_free_i64(in);
} }
@ -1762,20 +1762,20 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
if (TCG_TARGET_HAS_v128) { if (TCG_TARGET_HAS_v128) {
TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V128); TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V128);
tcg_gen_ld_vec(in, cpu_env, aofs); tcg_gen_ld_vec(in, tcg_env, aofs);
for (i = (aofs == dofs) * 16; i < oprsz; i += 16) { for (i = (aofs == dofs) * 16; i < oprsz; i += 16) {
tcg_gen_st_vec(in, cpu_env, dofs + i); tcg_gen_st_vec(in, tcg_env, dofs + i);
} }
tcg_temp_free_vec(in); tcg_temp_free_vec(in);
} else { } else {
TCGv_i64 in0 = tcg_temp_ebb_new_i64(); TCGv_i64 in0 = tcg_temp_ebb_new_i64();
TCGv_i64 in1 = tcg_temp_ebb_new_i64(); TCGv_i64 in1 = tcg_temp_ebb_new_i64();
tcg_gen_ld_i64(in0, cpu_env, aofs); tcg_gen_ld_i64(in0, tcg_env, aofs);
tcg_gen_ld_i64(in1, cpu_env, aofs + 8); tcg_gen_ld_i64(in1, tcg_env, aofs + 8);
for (i = (aofs == dofs) * 16; i < oprsz; i += 16) { for (i = (aofs == dofs) * 16; i < oprsz; i += 16) {
tcg_gen_st_i64(in0, cpu_env, dofs + i); tcg_gen_st_i64(in0, tcg_env, dofs + i);
tcg_gen_st_i64(in1, cpu_env, dofs + i + 8); tcg_gen_st_i64(in1, tcg_env, dofs + i + 8);
} }
tcg_temp_free_i64(in0); tcg_temp_free_i64(in0);
tcg_temp_free_i64(in1); tcg_temp_free_i64(in1);
@ -1792,20 +1792,20 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
if (TCG_TARGET_HAS_v256) { if (TCG_TARGET_HAS_v256) {
TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V256); TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V256);
tcg_gen_ld_vec(in, cpu_env, aofs); tcg_gen_ld_vec(in, tcg_env, aofs);
for (i = (aofs == dofs) * 32; i < oprsz; i += 32) { for (i = (aofs == dofs) * 32; i < oprsz; i += 32) {
tcg_gen_st_vec(in, cpu_env, dofs + i); tcg_gen_st_vec(in, tcg_env, dofs + i);
} }
tcg_temp_free_vec(in); tcg_temp_free_vec(in);
} else if (TCG_TARGET_HAS_v128) { } else if (TCG_TARGET_HAS_v128) {
TCGv_vec in0 = tcg_temp_new_vec(TCG_TYPE_V128); TCGv_vec in0 = tcg_temp_new_vec(TCG_TYPE_V128);
TCGv_vec in1 = tcg_temp_new_vec(TCG_TYPE_V128); TCGv_vec in1 = tcg_temp_new_vec(TCG_TYPE_V128);
tcg_gen_ld_vec(in0, cpu_env, aofs); tcg_gen_ld_vec(in0, tcg_env, aofs);
tcg_gen_ld_vec(in1, cpu_env, aofs + 16); tcg_gen_ld_vec(in1, tcg_env, aofs + 16);
for (i = (aofs == dofs) * 32; i < oprsz; i += 32) { for (i = (aofs == dofs) * 32; i < oprsz; i += 32) {
tcg_gen_st_vec(in0, cpu_env, dofs + i); tcg_gen_st_vec(in0, tcg_env, dofs + i);
tcg_gen_st_vec(in1, cpu_env, dofs + i + 16); tcg_gen_st_vec(in1, tcg_env, dofs + i + 16);
} }
tcg_temp_free_vec(in0); tcg_temp_free_vec(in0);
tcg_temp_free_vec(in1); tcg_temp_free_vec(in1);
@ -1815,11 +1815,11 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
for (j = 0; j < 4; ++j) { for (j = 0; j < 4; ++j) {
in[j] = tcg_temp_ebb_new_i64(); in[j] = tcg_temp_ebb_new_i64();
tcg_gen_ld_i64(in[j], cpu_env, aofs + j * 8); tcg_gen_ld_i64(in[j], tcg_env, aofs + j * 8);
} }
for (i = (aofs == dofs) * 32; i < oprsz; i += 32) { for (i = (aofs == dofs) * 32; i < oprsz; i += 32) {
for (j = 0; j < 4; ++j) { for (j = 0; j < 4; ++j) {
tcg_gen_st_i64(in[j], cpu_env, dofs + i + j * 8); tcg_gen_st_i64(in[j], tcg_env, dofs + i + j * 8);
} }
} }
for (j = 0; j < 4; ++j) { for (j = 0; j < 4; ++j) {
@ -3140,9 +3140,9 @@ static void expand_2sh_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += tysz) { for (i = 0; i < oprsz; i += tysz) {
tcg_gen_ld_vec(t0, cpu_env, aofs + i); tcg_gen_ld_vec(t0, tcg_env, aofs + i);
fni(vece, t0, t0, shift); fni(vece, t0, t0, shift);
tcg_gen_st_vec(t0, cpu_env, dofs + i); tcg_gen_st_vec(t0, tcg_env, dofs + i);
} }
tcg_temp_free_vec(t0); tcg_temp_free_vec(t0);
} }
@ -3248,8 +3248,8 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,
tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT); tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT);
tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0)); tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0));
tcg_gen_addi_ptr(a0, cpu_env, dofs); tcg_gen_addi_ptr(a0, tcg_env, dofs);
tcg_gen_addi_ptr(a1, cpu_env, aofs); tcg_gen_addi_ptr(a1, tcg_env, aofs);
g->fno[vece](a0, a1, desc); g->fno[vece](a0, a1, desc);
@ -3690,10 +3690,10 @@ static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 4) { for (i = 0; i < oprsz; i += 4) {
tcg_gen_ld_i32(t0, cpu_env, aofs + i); tcg_gen_ld_i32(t0, tcg_env, aofs + i);
tcg_gen_ld_i32(t1, cpu_env, bofs + i); tcg_gen_ld_i32(t1, tcg_env, bofs + i);
tcg_gen_negsetcond_i32(cond, t0, t0, t1); tcg_gen_negsetcond_i32(cond, t0, t0, t1);
tcg_gen_st_i32(t0, cpu_env, dofs + i); tcg_gen_st_i32(t0, tcg_env, dofs + i);
} }
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
tcg_temp_free_i32(t0); tcg_temp_free_i32(t0);
@ -3707,10 +3707,10 @@ static void expand_cmp_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i64(t0, cpu_env, aofs + i); tcg_gen_ld_i64(t0, tcg_env, aofs + i);
tcg_gen_ld_i64(t1, cpu_env, bofs + i); tcg_gen_ld_i64(t1, tcg_env, bofs + i);
tcg_gen_negsetcond_i64(cond, t0, t0, t1); tcg_gen_negsetcond_i64(cond, t0, t0, t1);
tcg_gen_st_i64(t0, cpu_env, dofs + i); tcg_gen_st_i64(t0, tcg_env, dofs + i);
} }
tcg_temp_free_i64(t1); tcg_temp_free_i64(t1);
tcg_temp_free_i64(t0); tcg_temp_free_i64(t0);
@ -3725,10 +3725,10 @@ static void expand_cmp_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += tysz) { for (i = 0; i < oprsz; i += tysz) {
tcg_gen_ld_vec(t0, cpu_env, aofs + i); tcg_gen_ld_vec(t0, tcg_env, aofs + i);
tcg_gen_ld_vec(t1, cpu_env, bofs + i); tcg_gen_ld_vec(t1, tcg_env, bofs + i);
tcg_gen_cmp_vec(cond, vece, t0, t0, t1); tcg_gen_cmp_vec(cond, vece, t0, t0, t1);
tcg_gen_st_vec(t0, cpu_env, dofs + i); tcg_gen_st_vec(t0, tcg_env, dofs + i);
} }
tcg_temp_free_vec(t1); tcg_temp_free_vec(t1);
tcg_temp_free_vec(t0); tcg_temp_free_vec(t0);
@ -3855,9 +3855,9 @@ static void expand_cmps_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += tysz) { for (i = 0; i < oprsz; i += tysz) {
tcg_gen_ld_vec(t1, cpu_env, aofs + i); tcg_gen_ld_vec(t1, tcg_env, aofs + i);
tcg_gen_cmp_vec(cond, vece, t0, t1, c); tcg_gen_cmp_vec(cond, vece, t0, t1, c);
tcg_gen_st_vec(t0, cpu_env, dofs + i); tcg_gen_st_vec(t0, tcg_env, dofs + i);
} }
} }
@ -3950,9 +3950,9 @@ void tcg_gen_gvec_cmps(TCGCond cond, unsigned vece, uint32_t dofs,
uint32_t i; uint32_t i;
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i64(t0, cpu_env, aofs + i); tcg_gen_ld_i64(t0, tcg_env, aofs + i);
tcg_gen_negsetcond_i64(cond, t0, t0, c); tcg_gen_negsetcond_i64(cond, t0, t0, c);
tcg_gen_st_i64(t0, cpu_env, dofs + i); tcg_gen_st_i64(t0, tcg_env, dofs + i);
} }
tcg_temp_free_i64(t0); tcg_temp_free_i64(t0);
} else if (vece == MO_32 && check_size_impl(oprsz, 4)) { } else if (vece == MO_32 && check_size_impl(oprsz, 4)) {
@ -3962,9 +3962,9 @@ void tcg_gen_gvec_cmps(TCGCond cond, unsigned vece, uint32_t dofs,
tcg_gen_extrl_i64_i32(t1, c); tcg_gen_extrl_i64_i32(t1, c);
for (i = 0; i < oprsz; i += 8) { for (i = 0; i < oprsz; i += 8) {
tcg_gen_ld_i32(t0, cpu_env, aofs + i); tcg_gen_ld_i32(t0, tcg_env, aofs + i);
tcg_gen_negsetcond_i32(cond, t0, t0, t1); tcg_gen_negsetcond_i32(cond, t0, t0, t1);
tcg_gen_st_i32(t0, cpu_env, dofs + i); tcg_gen_st_i32(t0, tcg_env, dofs + i);
} }
tcg_temp_free_i32(t0); tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);

22
tcg/tcg-op-ldst.c
View File

@ -589,7 +589,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
tcg_gen_extu_i32_i64(ext_addr, temp_tcgv_i32(addr)); tcg_gen_extu_i32_i64(ext_addr, temp_tcgv_i32(addr));
addr = tcgv_i64_temp(ext_addr); addr = tcgv_i64_temp(ext_addr);
} }
gen_helper_ld_i128(val, cpu_env, temp_tcgv_i64(addr), gen_helper_ld_i128(val, tcg_env, temp_tcgv_i64(addr),
tcg_constant_i32(orig_oi)); tcg_constant_i32(orig_oi));
} }
@ -698,7 +698,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
tcg_gen_extu_i32_i64(ext_addr, temp_tcgv_i32(addr)); tcg_gen_extu_i32_i64(ext_addr, temp_tcgv_i32(addr));
addr = tcgv_i64_temp(ext_addr); addr = tcgv_i64_temp(ext_addr);
} }
gen_helper_st_i128(cpu_env, temp_tcgv_i64(addr), val, gen_helper_st_i128(tcg_env, temp_tcgv_i64(addr), val,
tcg_constant_i32(orig_oi)); tcg_constant_i32(orig_oi));
} }
@ -847,7 +847,7 @@ static void tcg_gen_atomic_cmpxchg_i32_int(TCGv_i32 retv, TCGTemp *addr,
oi = make_memop_idx(memop & ~MO_SIGN, idx); oi = make_memop_idx(memop & ~MO_SIGN, idx);
a64 = maybe_extend_addr64(addr); a64 = maybe_extend_addr64(addr);
gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi));
maybe_free_addr64(a64); maybe_free_addr64(a64);
if (memop & MO_SIGN) { if (memop & MO_SIGN) {
@ -927,12 +927,12 @@ static void tcg_gen_atomic_cmpxchg_i64_int(TCGv_i64 retv, TCGTemp *addr,
if (gen) { if (gen) {
MemOpIdx oi = make_memop_idx(memop, idx); MemOpIdx oi = make_memop_idx(memop, idx);
TCGv_i64 a64 = maybe_extend_addr64(addr); TCGv_i64 a64 = maybe_extend_addr64(addr);
gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi));
maybe_free_addr64(a64); maybe_free_addr64(a64);
return; return;
} }
gen_helper_exit_atomic(cpu_env); gen_helper_exit_atomic(tcg_env);
/* /*
* Produce a result for a well-formed opcode stream. This satisfies * Produce a result for a well-formed opcode stream. This satisfies
@ -990,7 +990,7 @@ static void tcg_gen_nonatomic_cmpxchg_i128_int(TCGv_i128 retv, TCGTemp *addr,
MemOpIdx oi = make_memop_idx(memop, idx); MemOpIdx oi = make_memop_idx(memop, idx);
TCGv_i64 a64 = maybe_extend_addr64(addr); TCGv_i64 a64 = maybe_extend_addr64(addr);
gen_helper_nonatomic_cmpxchgo(retv, cpu_env, a64, cmpv, newv, gen_helper_nonatomic_cmpxchgo(retv, tcg_env, a64, cmpv, newv,
tcg_constant_i32(oi)); tcg_constant_i32(oi));
maybe_free_addr64(a64); maybe_free_addr64(a64);
} else { } else {
@ -1049,12 +1049,12 @@ static void tcg_gen_atomic_cmpxchg_i128_int(TCGv_i128 retv, TCGTemp *addr,
if (gen) { if (gen) {
MemOpIdx oi = make_memop_idx(memop, idx); MemOpIdx oi = make_memop_idx(memop, idx);
TCGv_i64 a64 = maybe_extend_addr64(addr); TCGv_i64 a64 = maybe_extend_addr64(addr);
gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi));
maybe_free_addr64(a64); maybe_free_addr64(a64);
return; return;
} }
gen_helper_exit_atomic(cpu_env); gen_helper_exit_atomic(tcg_env);
/* /*
* Produce a result for a well-formed opcode stream. This satisfies * Produce a result for a well-formed opcode stream. This satisfies
@ -1108,7 +1108,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGTemp *addr, TCGv_i32 val,
oi = make_memop_idx(memop & ~MO_SIGN, idx); oi = make_memop_idx(memop & ~MO_SIGN, idx);
a64 = maybe_extend_addr64(addr); a64 = maybe_extend_addr64(addr);
gen(ret, cpu_env, a64, val, tcg_constant_i32(oi)); gen(ret, tcg_env, a64, val, tcg_constant_i32(oi));
maybe_free_addr64(a64); maybe_free_addr64(a64);
if (memop & MO_SIGN) { if (memop & MO_SIGN) {
@ -1146,12 +1146,12 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGTemp *addr, TCGv_i64 val,
if (gen) { if (gen) {
MemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx); MemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx);
TCGv_i64 a64 = maybe_extend_addr64(addr); TCGv_i64 a64 = maybe_extend_addr64(addr);
gen(ret, cpu_env, a64, val, tcg_constant_i32(oi)); gen(ret, tcg_env, a64, val, tcg_constant_i32(oi));
maybe_free_addr64(a64); maybe_free_addr64(a64);
return; return;
} }
gen_helper_exit_atomic(cpu_env); gen_helper_exit_atomic(tcg_env);
/* Produce a result, so that we have a well-formed opcode stream /* Produce a result, so that we have a well-formed opcode stream
with respect to uses of the result in the (dead) code following. */ with respect to uses of the result in the (dead) code following. */
tcg_gen_movi_i64(ret, 0); tcg_gen_movi_i64(ret, 0);

2
tcg/tcg-op.c
View File

@ -2939,7 +2939,7 @@ void tcg_gen_lookup_and_goto_ptr(void)
plugin_gen_disable_mem_helpers(); plugin_gen_disable_mem_helpers();
ptr = tcg_temp_ebb_new_ptr(); ptr = tcg_temp_ebb_new_ptr();
gen_helper_lookup_tb_ptr(ptr, cpu_env); gen_helper_lookup_tb_ptr(ptr, tcg_env);
tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr));
tcg_temp_free_ptr(ptr); tcg_temp_free_ptr(ptr);
} }

4
tcg/tcg.c
View File

@ -231,7 +231,7 @@ __thread TCGContext *tcg_ctx;
TCGContext **tcg_ctxs; TCGContext **tcg_ctxs;
unsigned int tcg_cur_ctxs; unsigned int tcg_cur_ctxs;
unsigned int tcg_max_ctxs; unsigned int tcg_max_ctxs;
TCGv_env cpu_env = 0; TCGv_env tcg_env;
const void *tcg_code_gen_epilogue; const void *tcg_code_gen_epilogue;
uintptr_t tcg_splitwx_diff; uintptr_t tcg_splitwx_diff;
@ -1353,7 +1353,7 @@ static void tcg_context_init(unsigned max_cpus)
tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0));
ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env");
cpu_env = temp_tcgv_ptr(ts); tcg_env = temp_tcgv_ptr(ts);
} }
void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus) void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus)