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target/loongarch: Implement xvpack xvpick xvilv{l/h}

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This patch includes:
- XVPACK{EV/OD}.{B/H/W/D};
- XVPICK{EV/OD}.{B/H/W/D};
- XVILV{L/H}.{B/H/W/D}.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-54-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-09-14 10:26:41 +08:00
parent df97f33807
commit ad2921482c
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
4 changed files with 156 additions and 60 deletions
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27
target/loongarch/disas.c
View File

@ -2547,3 +2547,30 @@ INSN_LASX(xvpickve_d, vv_i)
INSN_LASX(xvbsll_v, vv_i) INSN_LASX(xvbsll_v, vv_i)
INSN_LASX(xvbsrl_v, vv_i) INSN_LASX(xvbsrl_v, vv_i)
INSN_LASX(xvpackev_b, vvv)
INSN_LASX(xvpackev_h, vvv)
INSN_LASX(xvpackev_w, vvv)
INSN_LASX(xvpackev_d, vvv)
INSN_LASX(xvpackod_b, vvv)
INSN_LASX(xvpackod_h, vvv)
INSN_LASX(xvpackod_w, vvv)
INSN_LASX(xvpackod_d, vvv)
INSN_LASX(xvpickev_b, vvv)
INSN_LASX(xvpickev_h, vvv)
INSN_LASX(xvpickev_w, vvv)
INSN_LASX(xvpickev_d, vvv)
INSN_LASX(xvpickod_b, vvv)
INSN_LASX(xvpickod_h, vvv)
INSN_LASX(xvpickod_w, vvv)
INSN_LASX(xvpickod_d, vvv)
INSN_LASX(xvilvl_b, vvv)
INSN_LASX(xvilvl_h, vvv)
INSN_LASX(xvilvl_w, vvv)
INSN_LASX(xvilvl_d, vvv)
INSN_LASX(xvilvh_b, vvv)
INSN_LASX(xvilvh_h, vvv)
INSN_LASX(xvilvh_w, vvv)
INSN_LASX(xvilvh_d, vvv)

24
target/loongarch/insn_trans/trans_vec.c.inc
View File

@ -5171,6 +5171,14 @@ TRANS(vpackod_b, LSX, gen_vvv, gen_helper_vpackod_b)
TRANS(vpackod_h, LSX, gen_vvv, gen_helper_vpackod_h) TRANS(vpackod_h, LSX, gen_vvv, gen_helper_vpackod_h)
TRANS(vpackod_w, LSX, gen_vvv, gen_helper_vpackod_w) TRANS(vpackod_w, LSX, gen_vvv, gen_helper_vpackod_w)
TRANS(vpackod_d, LSX, gen_vvv, gen_helper_vpackod_d) TRANS(vpackod_d, LSX, gen_vvv, gen_helper_vpackod_d)
TRANS(xvpackev_b, LASX, gen_xxx, gen_helper_vpackev_b)
TRANS(xvpackev_h, LASX, gen_xxx, gen_helper_vpackev_h)
TRANS(xvpackev_w, LASX, gen_xxx, gen_helper_vpackev_w)
TRANS(xvpackev_d, LASX, gen_xxx, gen_helper_vpackev_d)
TRANS(xvpackod_b, LASX, gen_xxx, gen_helper_vpackod_b)
TRANS(xvpackod_h, LASX, gen_xxx, gen_helper_vpackod_h)
TRANS(xvpackod_w, LASX, gen_xxx, gen_helper_vpackod_w)
TRANS(xvpackod_d, LASX, gen_xxx, gen_helper_vpackod_d)
TRANS(vpickev_b, LSX, gen_vvv, gen_helper_vpickev_b) TRANS(vpickev_b, LSX, gen_vvv, gen_helper_vpickev_b)
TRANS(vpickev_h, LSX, gen_vvv, gen_helper_vpickev_h) TRANS(vpickev_h, LSX, gen_vvv, gen_helper_vpickev_h)
@ -5180,6 +5188,14 @@ TRANS(vpickod_b, LSX, gen_vvv, gen_helper_vpickod_b)
TRANS(vpickod_h, LSX, gen_vvv, gen_helper_vpickod_h) TRANS(vpickod_h, LSX, gen_vvv, gen_helper_vpickod_h)
TRANS(vpickod_w, LSX, gen_vvv, gen_helper_vpickod_w) TRANS(vpickod_w, LSX, gen_vvv, gen_helper_vpickod_w)
TRANS(vpickod_d, LSX, gen_vvv, gen_helper_vpickod_d) TRANS(vpickod_d, LSX, gen_vvv, gen_helper_vpickod_d)
TRANS(xvpickev_b, LASX, gen_xxx, gen_helper_vpickev_b)
TRANS(xvpickev_h, LASX, gen_xxx, gen_helper_vpickev_h)
TRANS(xvpickev_w, LASX, gen_xxx, gen_helper_vpickev_w)
TRANS(xvpickev_d, LASX, gen_xxx, gen_helper_vpickev_d)
TRANS(xvpickod_b, LASX, gen_xxx, gen_helper_vpickod_b)
TRANS(xvpickod_h, LASX, gen_xxx, gen_helper_vpickod_h)
TRANS(xvpickod_w, LASX, gen_xxx, gen_helper_vpickod_w)
TRANS(xvpickod_d, LASX, gen_xxx, gen_helper_vpickod_d)
TRANS(vilvl_b, LSX, gen_vvv, gen_helper_vilvl_b) TRANS(vilvl_b, LSX, gen_vvv, gen_helper_vilvl_b)
TRANS(vilvl_h, LSX, gen_vvv, gen_helper_vilvl_h) TRANS(vilvl_h, LSX, gen_vvv, gen_helper_vilvl_h)
@ -5189,6 +5205,14 @@ TRANS(vilvh_b, LSX, gen_vvv, gen_helper_vilvh_b)
TRANS(vilvh_h, LSX, gen_vvv, gen_helper_vilvh_h) TRANS(vilvh_h, LSX, gen_vvv, gen_helper_vilvh_h)
TRANS(vilvh_w, LSX, gen_vvv, gen_helper_vilvh_w) TRANS(vilvh_w, LSX, gen_vvv, gen_helper_vilvh_w)
TRANS(vilvh_d, LSX, gen_vvv, gen_helper_vilvh_d) TRANS(vilvh_d, LSX, gen_vvv, gen_helper_vilvh_d)
TRANS(xvilvl_b, LASX, gen_xxx, gen_helper_vilvl_b)
TRANS(xvilvl_h, LASX, gen_xxx, gen_helper_vilvl_h)
TRANS(xvilvl_w, LASX, gen_xxx, gen_helper_vilvl_w)
TRANS(xvilvl_d, LASX, gen_xxx, gen_helper_vilvl_d)
TRANS(xvilvh_b, LASX, gen_xxx, gen_helper_vilvh_b)
TRANS(xvilvh_h, LASX, gen_xxx, gen_helper_vilvh_h)
TRANS(xvilvh_w, LASX, gen_xxx, gen_helper_vilvh_w)
TRANS(xvilvh_d, LASX, gen_xxx, gen_helper_vilvh_d)
TRANS(vshuf_b, LSX, gen_vvvv, gen_helper_vshuf_b) TRANS(vshuf_b, LSX, gen_vvvv, gen_helper_vshuf_b)
TRANS(vshuf_h, LSX, gen_vvv, gen_helper_vshuf_h) TRANS(vshuf_h, LSX, gen_vvv, gen_helper_vshuf_h)

27
target/loongarch/insns.decode
View File

@ -2012,3 +2012,30 @@ xvpickve_d 0111 01110000 00111 110 .. ..... ..... @vv_ui2
xvbsll_v 0111 01101000 11100 ..... ..... ..... @vv_ui5 xvbsll_v 0111 01101000 11100 ..... ..... ..... @vv_ui5
xvbsrl_v 0111 01101000 11101 ..... ..... ..... @vv_ui5 xvbsrl_v 0111 01101000 11101 ..... ..... ..... @vv_ui5
xvpackev_b 0111 01010001 01100 ..... ..... ..... @vvv
xvpackev_h 0111 01010001 01101 ..... ..... ..... @vvv
xvpackev_w 0111 01010001 01110 ..... ..... ..... @vvv
xvpackev_d 0111 01010001 01111 ..... ..... ..... @vvv
xvpackod_b 0111 01010001 10000 ..... ..... ..... @vvv
xvpackod_h 0111 01010001 10001 ..... ..... ..... @vvv
xvpackod_w 0111 01010001 10010 ..... ..... ..... @vvv
xvpackod_d 0111 01010001 10011 ..... ..... ..... @vvv
xvpickev_b 0111 01010001 11100 ..... ..... ..... @vvv
xvpickev_h 0111 01010001 11101 ..... ..... ..... @vvv
xvpickev_w 0111 01010001 11110 ..... ..... ..... @vvv
xvpickev_d 0111 01010001 11111 ..... ..... ..... @vvv
xvpickod_b 0111 01010010 00000 ..... ..... ..... @vvv
xvpickod_h 0111 01010010 00001 ..... ..... ..... @vvv
xvpickod_w 0111 01010010 00010 ..... ..... ..... @vvv
xvpickod_d 0111 01010010 00011 ..... ..... ..... @vvv
xvilvl_b 0111 01010001 10100 ..... ..... ..... @vvv
xvilvl_h 0111 01010001 10101 ..... ..... ..... @vvv
xvilvl_w 0111 01010001 10110 ..... ..... ..... @vvv
xvilvl_d 0111 01010001 10111 ..... ..... ..... @vvv
xvilvh_b 0111 01010001 11000 ..... ..... ..... @vvv
xvilvh_h 0111 01010001 11001 ..... ..... ..... @vvv
xvilvh_w 0111 01010001 11010 ..... ..... ..... @vvv
xvilvh_d 0111 01010001 11011 ..... ..... ..... @vvv

138
target/loongarch/vec_helper.c
View File

@ -3241,12 +3241,13 @@ XVPICKVE(xvpickve_d, D, 64, 0x3)
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \ { \
int i; \ int i; \
VReg temp; \ VReg temp = {}; \
VReg *Vd = (VReg *)vd; \ VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \ VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \ VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\ \
for (i = 0; i < LSX_LEN/BIT; i++) { \ for (i = 0; i < oprsz / (BIT / 8); i++) { \
temp.E(2 * i + 1) = Vj->E(2 * i); \ temp.E(2 * i + 1) = Vj->E(2 * i); \
temp.E(2 *i) = Vk->E(2 * i); \ temp.E(2 *i) = Vk->E(2 * i); \
} \ } \
@ -3262,12 +3263,13 @@ VPACKEV(vpackev_d, 128, D)
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \ { \
int i; \ int i; \
VReg temp; \ VReg temp = {}; \
VReg *Vd = (VReg *)vd; \ VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \ VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \ VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\ \
for (i = 0; i < LSX_LEN/BIT; i++) { \ for (i = 0; i < oprsz / (BIT / 8); i++) { \
temp.E(2 * i + 1) = Vj->E(2 * i + 1); \ temp.E(2 * i + 1) = Vj->E(2 * i + 1); \
temp.E(2 * i) = Vk->E(2 * i + 1); \ temp.E(2 * i) = Vk->E(2 * i + 1); \
} \ } \
@ -3279,20 +3281,24 @@ VPACKOD(vpackod_h, 32, H)
VPACKOD(vpackod_w, 64, W) VPACKOD(vpackod_w, 64, W)
VPACKOD(vpackod_d, 128, D) VPACKOD(vpackod_d, 128, D)
#define VPICKEV(NAME, BIT, E) \ #define VPICKEV(NAME, BIT, E) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \ { \
int i; \ int i, j, ofs; \
VReg temp; \ VReg temp = {}; \
VReg *Vd = (VReg *)vd; \ VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \ VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \ VReg *Vk = (VReg *)vk; \
\ int oprsz = simd_oprsz(desc); \
for (i = 0; i < LSX_LEN/BIT; i++) { \ \
temp.E(i + LSX_LEN/BIT) = Vj->E(2 * i); \ ofs = LSX_LEN / BIT; \
temp.E(i) = Vk->E(2 * i); \ for (i = 0; i < oprsz / 16; i++) { \
} \ for (j = 0; j < ofs; j++) { \
*Vd = temp; \ temp.E(j + ofs * (2 * i + 1)) = Vj->E(2 * (j + ofs * i)); \
temp.E(j + ofs * 2 * i) = Vk->E(2 * (j + ofs * i)); \
} \
} \
*Vd = temp; \
} }
VPICKEV(vpickev_b, 16, B) VPICKEV(vpickev_b, 16, B)
@ -3300,20 +3306,24 @@ VPICKEV(vpickev_h, 32, H)
VPICKEV(vpickev_w, 64, W) VPICKEV(vpickev_w, 64, W)
VPICKEV(vpickev_d, 128, D) VPICKEV(vpickev_d, 128, D)
#define VPICKOD(NAME, BIT, E) \ #define VPICKOD(NAME, BIT, E) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \ { \
int i; \ int i, j, ofs; \
VReg temp; \ VReg temp = {}; \
VReg *Vd = (VReg *)vd; \ VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \ VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \ VReg *Vk = (VReg *)vk; \
\ int oprsz = simd_oprsz(desc); \
for (i = 0; i < LSX_LEN/BIT; i++) { \ \
temp.E(i + LSX_LEN/BIT) = Vj->E(2 * i + 1); \ ofs = LSX_LEN / BIT; \
temp.E(i) = Vk->E(2 * i + 1); \ for (i = 0; i < oprsz / 16; i++) { \
} \ for (j = 0; j < ofs; j++) { \
*Vd = temp; \ temp.E(j + ofs * (2 * i + 1)) = Vj->E(2 * (j + ofs * i) + 1); \
temp.E(j + ofs * 2 * i) = Vk->E(2 * (j + ofs * i) + 1); \
} \
} \
*Vd = temp; \
} }
VPICKOD(vpickod_b, 16, B) VPICKOD(vpickod_b, 16, B)
@ -3321,20 +3331,24 @@ VPICKOD(vpickod_h, 32, H)
VPICKOD(vpickod_w, 64, W) VPICKOD(vpickod_w, 64, W)
VPICKOD(vpickod_d, 128, D) VPICKOD(vpickod_d, 128, D)
#define VILVL(NAME, BIT, E) \ #define VILVL(NAME, BIT, E) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \ { \
int i; \ int i, j, ofs; \
VReg temp; \ VReg temp = {}; \
VReg *Vd = (VReg *)vd; \ VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \ VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \ VReg *Vk = (VReg *)vk; \
\ int oprsz = simd_oprsz(desc); \
for (i = 0; i < LSX_LEN/BIT; i++) { \ \
temp.E(2 * i + 1) = Vj->E(i); \ ofs = LSX_LEN / BIT; \
temp.E(2 * i) = Vk->E(i); \ for (i = 0; i < oprsz / 16; i++) { \
} \ for (j = 0; j < ofs; j++) { \
*Vd = temp; \ temp.E(2 * (j + ofs * i) + 1) = Vj->E(j + ofs * 2 * i); \
temp.E(2 * (j + ofs * i)) = Vk->E(j + ofs * 2 * i); \
} \
} \
*Vd = temp; \
} }
VILVL(vilvl_b, 16, B) VILVL(vilvl_b, 16, B)
@ -3342,20 +3356,24 @@ VILVL(vilvl_h, 32, H)
VILVL(vilvl_w, 64, W) VILVL(vilvl_w, 64, W)
VILVL(vilvl_d, 128, D) VILVL(vilvl_d, 128, D)
#define VILVH(NAME, BIT, E) \ #define VILVH(NAME, BIT, E) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \ { \
int i; \ int i, j, ofs; \
VReg temp; \ VReg temp = {}; \
VReg *Vd = (VReg *)vd; \ VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \ VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \ VReg *Vk = (VReg *)vk; \
\ int oprsz = simd_oprsz(desc); \
for (i = 0; i < LSX_LEN/BIT; i++) { \ \
temp.E(2 * i + 1) = Vj->E(i + LSX_LEN/BIT); \ ofs = LSX_LEN / BIT; \
temp.E(2 * i) = Vk->E(i + LSX_LEN/BIT); \ for (i = 0; i < oprsz / 16; i++) { \
} \ for (j = 0; j < ofs; j++) { \
*Vd = temp; \ temp.E(2 * (j + ofs * i) + 1) = Vj->E(j + ofs * (2 * i + 1)); \
temp.E(2 * (j + ofs * i)) = Vk->E(j + ofs * (2 * i + 1)); \
} \
} \
*Vd = temp; \
} }
VILVH(vilvh_b, 16, B) VILVH(vilvh_b, 16, B)