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target/arm: Introduce clear_vec

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In a couple of places, clearing the entire vector before storing one
element is the easiest solution.  Wrap that into a helper function.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-49-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:30:15 -06:00 committed by Peter Maydell
parent 07e0d7a0c7
commit ace363a1e9
1 changed files with 12 additions and 9 deletions
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21
target/arm/tcg/translate-a64.c
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@ -628,7 +628,16 @@ static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
return v; return v;
} }
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). static void clear_vec(DisasContext *s, int rd)
{
unsigned ofs = fp_reg_offset(s, rd, MO_64);
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_dup_imm(MO_64, ofs, vsz, vsz, 0);
}
/*
* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
* If SVE is not enabled, then there are only 128 bits in the vector. * If SVE is not enabled, then there are only 128 bits in the vector.
*/ */
static void clear_vec_high(DisasContext *s, bool is_q, int rd) static void clear_vec_high(DisasContext *s, bool is_q, int rd)
@ -4851,7 +4860,6 @@ static bool trans_SM3SS1(DisasContext *s, arg_SM3SS1 *a)
TCGv_i32 tcg_op2 = tcg_temp_new_i32(); TCGv_i32 tcg_op2 = tcg_temp_new_i32();
TCGv_i32 tcg_op3 = tcg_temp_new_i32(); TCGv_i32 tcg_op3 = tcg_temp_new_i32();
TCGv_i32 tcg_res = tcg_temp_new_i32(); TCGv_i32 tcg_res = tcg_temp_new_i32();
unsigned vsz, dofs;
read_vec_element_i32(s, tcg_op1, a->rn, 3, MO_32); read_vec_element_i32(s, tcg_op1, a->rn, 3, MO_32);
read_vec_element_i32(s, tcg_op2, a->rm, 3, MO_32); read_vec_element_i32(s, tcg_op2, a->rm, 3, MO_32);
@ -4863,9 +4871,7 @@ static bool trans_SM3SS1(DisasContext *s, arg_SM3SS1 *a)
tcg_gen_rotri_i32(tcg_res, tcg_res, 25); tcg_gen_rotri_i32(tcg_res, tcg_res, 25);
/* Clear the whole register first, then store bits [127:96]. */ /* Clear the whole register first, then store bits [127:96]. */
vsz = vec_full_reg_size(s); clear_vec(s, a->rd);
dofs = vec_full_reg_offset(s, a->rd);
tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0);
write_vec_element_i32(s, tcg_res, a->rd, 3, MO_32); write_vec_element_i32(s, tcg_res, a->rd, 3, MO_32);
} }
return true; return true;
@ -6307,7 +6313,6 @@ static bool do_scalar_muladd_widening_idx(DisasContext *s, arg_rrx_e *a,
TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64();
unsigned vsz, dofs;
if (acc) { if (acc) {
read_vec_element(s, t0, a->rd, 0, a->esz + 1); read_vec_element(s, t0, a->rd, 0, a->esz + 1);
@ -6317,9 +6322,7 @@ static bool do_scalar_muladd_widening_idx(DisasContext *s, arg_rrx_e *a,
fn(t0, t1, t2); fn(t0, t1, t2);
/* Clear the whole register first, then store scalar. */ /* Clear the whole register first, then store scalar. */
vsz = vec_full_reg_size(s); clear_vec(s, a->rd);
dofs = vec_full_reg_offset(s, a->rd);
tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0);
write_vec_element(s, t0, a->rd, 0, a->esz + 1); write_vec_element(s, t0, a->rd, 0, a->esz + 1);
} }
return true; return true;