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target/s390x: vxeh2: vector convert short/32b

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Signed-off-by: David Miller <dmiller423@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20220428094708.84835-6-david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
David Miller 2022-04-28 11:47:00 +02:00 committed by Thomas Huth
parent 46be8425ff
commit acc2d3a406
3 changed files with 75 additions and 4 deletions
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4
target/s390x/helper.h
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@ -275,6 +275,10 @@ DEF_HELPER_FLAGS_5(gvec_vfche64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32
DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32) DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfche128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32) DEF_HELPER_FLAGS_5(gvec_vfche128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfche128_cc, void, ptr, cptr, cptr, env, i32) DEF_HELPER_5(gvec_vfche128_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdg32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdlg32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcgd32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vclgd32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)

44
target/s390x/tcg/translate_vx.c.inc
View File

@ -2720,23 +2720,59 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
switch (s->fields.op2) { switch (s->fields.op2) {
case 0xc3: case 0xc3:
if (fpf == FPF_LONG) { switch (fpf) {
case FPF_LONG:
fn = gen_helper_gvec_vcdg64; fn = gen_helper_gvec_vcdg64;
break;
case FPF_SHORT:
if (s390_has_feat(S390_FEAT_VECTOR_ENH2)) {
fn = gen_helper_gvec_vcdg32;
}
break;
default:
break;
} }
break; break;
case 0xc1: case 0xc1:
if (fpf == FPF_LONG) { switch (fpf) {
case FPF_LONG:
fn = gen_helper_gvec_vcdlg64; fn = gen_helper_gvec_vcdlg64;
break;
case FPF_SHORT:
if (s390_has_feat(S390_FEAT_VECTOR_ENH2)) {
fn = gen_helper_gvec_vcdlg32;
}
break;
default:
break;
} }
break; break;
case 0xc2: case 0xc2:
if (fpf == FPF_LONG) { switch (fpf) {
case FPF_LONG:
fn = gen_helper_gvec_vcgd64; fn = gen_helper_gvec_vcgd64;
break;
case FPF_SHORT:
if (s390_has_feat(S390_FEAT_VECTOR_ENH2)) {
fn = gen_helper_gvec_vcgd32;
}
break;
default:
break;
} }
break; break;
case 0xc0: case 0xc0:
if (fpf == FPF_LONG) { switch (fpf) {
case FPF_LONG:
fn = gen_helper_gvec_vclgd64; fn = gen_helper_gvec_vclgd64;
break;
case FPF_SHORT:
if (s390_has_feat(S390_FEAT_VECTOR_ENH2)) {
fn = gen_helper_gvec_vclgd32;
}
break;
default:
break;
} }
break; break;
case 0xc7: case 0xc7:

31
target/s390x/tcg/vec_fpu_helper.c
View File

@ -175,6 +175,30 @@ static void vop128_2(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
*v1 = tmp; *v1 = tmp;
} }
static float32 vcdg32(float32 a, float_status *s)
{
return int32_to_float32(a, s);
}
static float32 vcdlg32(float32 a, float_status *s)
{
return uint32_to_float32(a, s);
}
static float32 vcgd32(float32 a, float_status *s)
{
const float32 tmp = float32_to_int32(a, s);
return float32_is_any_nan(a) ? INT32_MIN : tmp;
}
static float32 vclgd32(float32 a, float_status *s)
{
const float32 tmp = float32_to_uint32(a, s);
return float32_is_any_nan(a) ? 0 : tmp;
}
static float64 vcdg64(float64 a, float_status *s) static float64 vcdg64(float64 a, float_status *s)
{ {
return int64_to_float64(a, s); return int64_to_float64(a, s);
@ -210,6 +234,9 @@ void HELPER(gvec_##NAME##BITS)(void *v1, const void *v2, CPUS390XState *env, \
vop##BITS##_2(v1, v2, env, se, XxC, erm, FN, GETPC()); \ vop##BITS##_2(v1, v2, env, se, XxC, erm, FN, GETPC()); \
} }
#define DEF_GVEC_VOP2_32(NAME) \
DEF_GVEC_VOP2_FN(NAME, NAME##32, 32)
#define DEF_GVEC_VOP2_64(NAME) \ #define DEF_GVEC_VOP2_64(NAME) \
DEF_GVEC_VOP2_FN(NAME, NAME##64, 64) DEF_GVEC_VOP2_FN(NAME, NAME##64, 64)
@ -218,6 +245,10 @@ DEF_GVEC_VOP2_FN(NAME, float32_##OP, 32) \
DEF_GVEC_VOP2_FN(NAME, float64_##OP, 64) \ DEF_GVEC_VOP2_FN(NAME, float64_##OP, 64) \
DEF_GVEC_VOP2_FN(NAME, float128_##OP, 128) DEF_GVEC_VOP2_FN(NAME, float128_##OP, 128)
DEF_GVEC_VOP2_32(vcdg)
DEF_GVEC_VOP2_32(vcdlg)
DEF_GVEC_VOP2_32(vcgd)
DEF_GVEC_VOP2_32(vclgd)
DEF_GVEC_VOP2_64(vcdg) DEF_GVEC_VOP2_64(vcdg)
DEF_GVEC_VOP2_64(vcdlg) DEF_GVEC_VOP2_64(vcdlg)
DEF_GVEC_VOP2_64(vcgd) DEF_GVEC_VOP2_64(vcgd)