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hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address

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The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.

However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin numbers for input and output are different.
It is difficult to use a formula to determine the index number of INTC model
supported input and output IRQs.

To simplify and improve readability, introduces the AspeedINTCIRQ structure to
save the input/output IRQ index and its enable/status register address.

Introduce the "aspeed_2700_intc_irqs" table to store IRQ information for INTC.
Introduce the "aspeed_intc_get_irq" function to retrieve the input/output IRQ
pin index from the provided status/enable register address.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-15-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-03-07 11:59:23 +08:00 committed by Cédric Le Goater
parent c6c5e63d46
commit ab24c6a2df
2 changed files with 58 additions and 39 deletions
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87
hw/intc/aspeed_intc.c
View File

@ -40,7 +40,23 @@ REG32(GICINT135_STATUS, 0x704)
REG32(GICINT136_EN, 0x800)
REG32(GICINT136_STATUS, 0x804)
#define GICINT_STATUS_BASE R_GICINT128_STATUS
static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
uint32_t reg)
{
int i;
for (i = 0; i < aic->irq_table_count; i++) {
if (aic->irq_table[i].enable_reg == reg ||
aic->irq_table[i].status_reg == reg) {
return &aic->irq_table[i];
}
}
/*
* Invalid reg.
*/
g_assert_not_reached();
}
/*
* Update the state of an interrupt controller pin by setting
@ -54,17 +70,7 @@ static void aspeed_intc_update(AspeedINTCState *s, int inpin_idx,
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
const char *name = object_get_typename(OBJECT(s));
if (inpin_idx >= aic->num_inpins) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n",
__func__, inpin_idx);
return;
}
if (outpin_idx >= aic->num_outpins) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid output pin index: %d\n",
__func__, outpin_idx);
return;
}
assert((outpin_idx < aic->num_outpins) && (inpin_idx < aic->num_inpins));
trace_aspeed_intc_update_irq(name, inpin_idx, outpin_idx, level);
qemu_set_irq(s->output_pins[outpin_idx], level);
@ -81,21 +87,20 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
AspeedINTCState *s = (AspeedINTCState *)opaque;
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
const char *name = object_get_typename(OBJECT(s));
uint32_t status_reg = GICINT_STATUS_BASE + ((0x100 * irq) >> 2);
const AspeedINTCIRQ *intc_irq;
uint32_t status_reg;
uint32_t select = 0;
uint32_t enable;
int outpin_idx;
int inpin_idx;
int i;
outpin_idx = irq;
inpin_idx = irq;
assert(irq < aic->num_inpins);
if (irq >= aic->num_inpins) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n",
__func__, irq);
return;
}
intc_irq = &aic->irq_table[irq];
status_reg = intc_irq->status_reg;
outpin_idx = intc_irq->outpin_idx;
inpin_idx = intc_irq->inpin_idx;
trace_aspeed_intc_set_irq(name, inpin_idx, level);
enable = s->enable[inpin_idx];
@ -146,21 +151,16 @@ static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
{
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
const char *name = object_get_typename(OBJECT(s));
const AspeedINTCIRQ *intc_irq;
uint32_t reg = offset >> 2;
uint32_t old_enable;
uint32_t change;
int inpin_idx;
uint32_t irq;
irq = (offset & 0x0f00) >> 8;
inpin_idx = irq;
intc_irq = aspeed_intc_get_irq(aic, reg);
inpin_idx = intc_irq->inpin_idx;
if (inpin_idx >= aic->num_inpins) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Invalid input pin index: %d\n",
__func__, inpin_idx);
return;
}
assert(inpin_idx < aic->num_inpins);
/*
* The enable registers are used to enable source interrupts.
@ -202,26 +202,21 @@ static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
{
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
const char *name = object_get_typename(OBJECT(s));
const AspeedINTCIRQ *intc_irq;
uint32_t reg = offset >> 2;
int outpin_idx;
int inpin_idx;
uint32_t irq;
if (!data) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
return;
}
irq = (offset & 0x0f00) >> 8;
outpin_idx = irq;
inpin_idx = irq;
intc_irq = aspeed_intc_get_irq(aic, reg);
outpin_idx = intc_irq->outpin_idx;
inpin_idx = intc_irq->inpin_idx;
if (inpin_idx >= aic->num_inpins) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Invalid input pin index: %d\n",
__func__, inpin_idx);
return;
}
assert(inpin_idx < aic->num_inpins);
/* clear status */
s->regs[reg] &= ~data;
@ -411,6 +406,18 @@ static const TypeInfo aspeed_intc_info = {
.abstract = true,
};
static AspeedINTCIRQ aspeed_2700_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
{0, 0, 1, R_GICINT128_EN, R_GICINT128_STATUS},
{1, 1, 1, R_GICINT129_EN, R_GICINT129_STATUS},
{2, 2, 1, R_GICINT130_EN, R_GICINT130_STATUS},
{3, 3, 1, R_GICINT131_EN, R_GICINT131_STATUS},
{4, 4, 1, R_GICINT132_EN, R_GICINT132_STATUS},
{5, 5, 1, R_GICINT133_EN, R_GICINT133_STATUS},
{6, 6, 1, R_GICINT134_EN, R_GICINT134_STATUS},
{7, 7, 1, R_GICINT135_EN, R_GICINT135_STATUS},
{8, 8, 1, R_GICINT136_EN, R_GICINT136_STATUS},
};
static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -423,6 +430,8 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
aic->mem_size = 0x4000;
aic->nr_regs = 0x808 >> 2;
aic->reg_offset = 0x1000;
aic->irq_table = aspeed_2700_intc_irqs;
aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intc_irqs);
}
static const TypeInfo aspeed_2700_intc_info = {

10
include/hw/intc/aspeed_intc.h
View File

@ -19,6 +19,14 @@ OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_MAX_INPINS 9
#define ASPEED_INTC_MAX_OUTPINS 9
typedef struct AspeedINTCIRQ {
int inpin_idx;
int outpin_idx;
int num_outpins;
uint32_t enable_reg;
uint32_t status_reg;
} AspeedINTCIRQ;
struct AspeedINTCState {
/*< private >*/
SysBusDevice parent_obj;
@ -46,6 +54,8 @@ struct AspeedINTCClass {
uint64_t nr_regs;
uint64_t reg_offset;
const MemoryRegionOps *reg_ops;
const AspeedINTCIRQ *irq_table;
int irq_table_count;
};
#endif /* ASPEED_INTC_H */