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hw/nvme fixes

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- fix for invalid protection information calculation
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Merge tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu into staging

hw/nvme fixes

- fix for invalid protection information calculation

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# gpg: Signature made Tue 08 Aug 2023 06:34:02 AM PDT
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# gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown]
# gpg:                 aka "Klaus Jensen <k.jensen@samsung.com>" [unknown]
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#      Subkey fingerprint: 5228 33AA 75E2 DCE6 A247  66C0 4DE1 AF31 6D4F 0DE9

* tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu:
  docs: update hw/nvme documentation for protection information
  hw/nvme: fix CRC64 for guard tag

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-08-08 16:39:20 -07:00
commit a8fc5165aa
2 changed files with 11 additions and 5 deletions
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12
docs/system/devices/nvme.rst
View File

@ -271,9 +271,15 @@ The virtual namespace device supports DIF- and DIX-based protection information
``pil=UINT8`` (default: ``0``) ``pil=UINT8`` (default: ``0``)
Controls the location of the protection information within the metadata. Set Controls the location of the protection information within the metadata. Set
to ``1`` to transfer protection information as the first eight bytes of to ``1`` to transfer protection information as the first bytes of metadata.
metadata. Otherwise, the protection information is transferred as the last Otherwise, the protection information is transferred as the last bytes of
eight bytes. metadata.
``pif=UINT8`` (default: ``0``)
By default, the namespace device uses 16 bit guard protection information
format (``pif=0``). Set to ``2`` to enable 64 bit guard protection
information format. This requires at least 16 bytes of metadata. Note that
``pif=1`` (32 bit guards) is currently not supported.
Virtualization Enhancements and SR-IOV (Experimental Support) Virtualization Enhancements and SR-IOV (Experimental Support)
------------------------------------------------------------- -------------------------------------------------------------

4
hw/nvme/dif.c
View File

@ -115,7 +115,7 @@ static void nvme_dif_pract_generate_dif_crc64(NvmeNamespace *ns, uint8_t *buf,
uint64_t crc = crc64_nvme(~0ULL, buf, ns->lbasz); uint64_t crc = crc64_nvme(~0ULL, buf, ns->lbasz);
if (pil) { if (pil) {
crc = crc64_nvme(crc, mbuf, pil); crc = crc64_nvme(~crc, mbuf, pil);
} }
dif->g64.guard = cpu_to_be64(crc); dif->g64.guard = cpu_to_be64(crc);
@ -246,7 +246,7 @@ static uint16_t nvme_dif_prchk_crc64(NvmeNamespace *ns, NvmeDifTuple *dif,
uint64_t crc = crc64_nvme(~0ULL, buf, ns->lbasz); uint64_t crc = crc64_nvme(~0ULL, buf, ns->lbasz);
if (pil) { if (pil) {
crc = crc64_nvme(crc, mbuf, pil); crc = crc64_nvme(~crc, mbuf, pil);
} }
trace_pci_nvme_dif_prchk_guard_crc64(be64_to_cpu(dif->g64.guard), crc); trace_pci_nvme_dif_prchk_guard_crc64(be64_to_cpu(dif->g64.guard), crc);