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target/riscv: add RVA23U64 profile

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Add RVA23U64 as described in [1]. Add it as a child of RVA22U64 since
all RVA22U64 mandatory extensions are also present in RVA23U64. What's
left then is to list the mandatory extensions that are RVA23 only.

A new "rva23u64" CPU is also added.

[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250115184316.2344583-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2025-01-15 15:43:15 -03:00 committed by Alistair Francis
parent 08dfc19454
commit a876221bd3
2 changed files with 34 additions and 0 deletions
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1
target/riscv/cpu-qom.h
View File

@ -40,6 +40,7 @@
#define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e")
#define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")

33
target/riscv/cpu.c
View File

@ -2391,9 +2391,34 @@ static RISCVCPUProfile RVA22S64 = {
}
};
/*
* All mandatory extensions from RVA22U64 are present
* in RVA23U64 so set RVA22 as a parent. We need to
* declare just the newly added mandatory extensions.
*/
static RISCVCPUProfile RVA23U64 = {
.u_parent = &RVA22U64,
.s_parent = NULL,
.name = "rva23u64",
.misa_ext = RVV,
.priv_spec = RISCV_PROFILE_ATTR_UNUSED,
.satp_mode = RISCV_PROFILE_ATTR_UNUSED,
.ext_offsets = {
CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zvbb),
CPU_CFG_OFFSET(ext_zvkt), CPU_CFG_OFFSET(ext_zihintntl),
CPU_CFG_OFFSET(ext_zicond), CPU_CFG_OFFSET(ext_zimop),
CPU_CFG_OFFSET(ext_zcmop), CPU_CFG_OFFSET(ext_zcb),
CPU_CFG_OFFSET(ext_zfa), CPU_CFG_OFFSET(ext_zawrs),
CPU_CFG_OFFSET(ext_supm),
RISCV_PROFILE_EXT_LIST_END
}
};
RISCVCPUProfile *riscv_profiles[] = {
&RVA22U64,
&RVA22S64,
&RVA23U64,
NULL,
};
@ -2880,6 +2905,13 @@ static void rva22s64_profile_cpu_init(Object *obj)
RVA22S64.enabled = true;
}
static void rva23u64_profile_cpu_init(Object *obj)
{
rv64i_bare_cpu_init(obj);
RVA23U64.enabled = true;
}
#endif
static const gchar *riscv_gdb_arch_name(CPUState *cs)
@ -3150,6 +3182,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init),
#endif /* TARGET_RISCV64 */
};