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target/arm: Add decodetree entry for DSB nXS variant

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The DSB nXS variant is always both a reads and writes request type.
Ignore the domain field like we do in plain DSB and perform a full
system barrier operation.

The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7.

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211144440.2700268-5-peter.maydell@linaro.org
[PMM: added missing "UNDEF unless feature present" check]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Manos Pitsidianakis 2024-12-11 14:44:38 +00:00 committed by Peter Maydell
parent 4278186a30
commit a65a24b9cf
2 changed files with 12 additions and 0 deletions
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3
target/arm/tcg/a64.decode
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@ -260,6 +260,9 @@ WFIT 1101 0101 0000 0011 0001 0000 001 rd:5
CLREX 1101 0101 0000 0011 0011 ---- 010 11111 CLREX 1101 0101 0000 0011 0011 ---- 010 11111
DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
# For the DSB nXS variant, types always equals MBReqTypes_All and we ignore the
# domain bits.
DSB_nXS 1101 0101 0000 0011 0011 -- 10 001 11111
ISB 1101 0101 0000 0011 0011 ---- 110 11111 ISB 1101 0101 0000 0011 0011 ---- 110 11111
SB 1101 0101 0000 0011 0011 0000 111 11111 SB 1101 0101 0000 0011 0011 0000 111 11111

9
target/arm/tcg/translate-a64.c
View File

@ -1986,6 +1986,15 @@ static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a)
return true; return true;
} }
static bool trans_DSB_nXS(DisasContext *s, arg_DSB_nXS *a)
{
if (!dc_isar_feature(aa64_xs, s)) {
return false;
}
tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
return true;
}
static bool trans_ISB(DisasContext *s, arg_ISB *a) static bool trans_ISB(DisasContext *s, arg_ISB *a)
{ {
/* /*