SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

hw/loongarch: fdt adds cpu interrupt controller node

Browse Source 
fdt adds cpu interrupt controller node,
we use 'loongson,cpu-interrupt-controller'.

See:
https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongarch-cpu.c
https://lore.kernel.org/r/20221114113824.1880-2-liupeibao@loongson.cn

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20240426091551.2397867-11-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2024-04-26 17:15:44 +08:00
parent b11f981452
commit a0663efd81
1 changed files with 21 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
hw/loongarch/virt.c
View File

@ -106,6 +106,23 @@ static void virt_flash_map(LoongArchMachineState *lams,
virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem);
} }
static void fdt_add_cpuic_node(LoongArchMachineState *lams,
uint32_t *cpuintc_phandle)
{
MachineState *ms = MACHINE(lams);
char *nodename;
*cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt);
nodename = g_strdup_printf("/cpuic");
qemu_fdt_add_subnode(ms->fdt, nodename);
qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle);
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
"loongson,cpu-interrupt-controller");
qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
g_free(nodename);
}
static void fdt_add_flash_node(LoongArchMachineState *lams) static void fdt_add_flash_node(LoongArchMachineState *lams)
{ {
MachineState *ms = MACHINE(lams); MachineState *ms = MACHINE(lams);
@ -528,6 +545,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
CPULoongArchState *env; CPULoongArchState *env;
CPUState *cpu_state; CPUState *cpu_state;
int cpu, pin, i, start, num; int cpu, pin, i, start, num;
uint32_t cpuintc_phandle;
/* /*
* The connection of interrupts: * The connection of interrupts:
@ -562,6 +580,9 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR, memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR,
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
/* Add cpu interrupt-controller */
fdt_add_cpuic_node(lams, &cpuintc_phandle);
for (cpu = 0; cpu < ms->smp.cpus; cpu++) { for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
cpu_state = qemu_get_cpu(cpu); cpu_state = qemu_get_cpu(cpu);
cpudev = DEVICE(cpu_state); cpudev = DEVICE(cpu_state);